xr XRK7933 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER MARCH 2005 REV. P1.0.1 GENERAL DESCRIPTION The XRK7933 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 3x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance. The XRK7933 Intelligent Dynamic Clock Switch circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the device will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. FEATURES • Fully Integrated PLL • Intelligent Dynamic Clock Switch • LVPECL Clock Outputs • LVCMOS Control I/O • 3.3V Operation • 32-Lead LQFP Packaging FIGURE 1. BLOCK DIAGRAM OF THE XRK7933 CLK_Selected INP1Bad INP0Bad Man_Override Alarm_Reset Sel_CLK Dynamic Switch Logic PLL_En Qb0 Qb0 Qb1 Qb1 OR CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR ÷4 PLL 200-400MHz ÷12 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com xr PRELIMINARY XRK7933 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER REV. P1.0.1 PRODUCT ORDERING INFORMATION PRODUCT NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRK7933 32-Lead LQFP -40°C to +85°C VCC Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 VCC 24 23 22 21 20 19 18 17 FIGURE 2. PIN OUT OF THE XRK7933 Qa1 25 16 VCC Qa1 26 15 Inp0bad Qa0 27 14 Inp1bad Qa0 28 13 CK_Selected VCC 29 12 GND VCC_PLL 30 11 Ext_FB Man_Override 31 10 Ext_FB PLL_En 32 9 2 8 GND 7 CLK1 6 CLK1 5 Sel_CLK 4 CLK0 3 CLK0 2 Alarm_Reset MR 1 XRK7933 GND XRK7933 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER xr REV. P1.0.1 PIN DESCRIPTIONS PIN NAME TYPE DESCRIPTION CLK0, CLK0 CLK1, CLK1 LVPECL Input LVPECL Input Differential PLL clock reference (CLK0 pulldown, CLK0 pullup) Differential PLL clock reference (CLK1 pulldown, CLK1 pullup) Ext_FB, Ext_FB LVPECL Input Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup) Qa[1:0], Qa[1:0] LVPECL Output Differential 1x output pairs Qb[2:0], Qb[2:0] LVPECL Output Differential 3x output pairs Inp0bad LVCMOS Output Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted. Inp1bad LVCMOS Output Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted. Clk_Selected LVCMOS Output 0 - if clock 0 is selected 1 - if clock 1 is selected Alarm_Reset LVCMOS Input 0 - will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is one-shotted (50KΩ pullup). Sel_Clk LVCMOS Input 0 - selects CLK0 1 - selects CLK1 (40kΩ pulldown) Manual_Override LVCMOS Input 1 - disables internal clock switch circuitry (40KΩ pulldown). PLL_En LVCMOS Input 0 - bypasses selected input reference around the phase-locked loop (50KΩ pullup). MR LVCMOS Input 0 - resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50KΩ pullup). VCCA Power Supply PLL power supply VCC Power Supply Digital power supply GNDA Power Supply PLL Ground GND Power Supply Digital Ground 3 xr PRELIMINARY XRK7933 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER REV. P1.0.1 ABSOLUTE MAXIMUM RATINGSa SYMBOL CHARACTERISTICS MIN MAX UNIT VCC Supply Voltage -0.3 3.6 V VIN DC Input Voltage -0.3 VCC+0.3 V DC Output Voltage -0.3 VCC+0.3 V DC Input Current +20 mA DC Output Current +50 mA 125 °C VOUT IIN IOUT TS Storage Temperature -65 CONDITION a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. GENERAL SPECIFICATIONS SYMBOL CHARACTERISTICS MIN TYP MAX VCC-2 UNIT VTT Output termination voltage MM ESD Protection (Machine model) 200 V HBM ESD Protection (Human body model) 2000 V LU Latch-up immunity 200 mA CIN Input Capacitance θJA Thermal resistance junction to ambient JESD 51-3, single layer test board V 4.0 pF Inputs 62.0 °C/W Natural convection 47.0 °C/W Natural convection Thermal resistance junction to case 14 °C/W Operating junction temperature 115 °C JESD 51-6, 2S2P multilayer test board θJC CONDITION 4 xr XRK7933 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER REV. P1.0.1 DC CHARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C) SYMBOL CHARACTERISTICS MIN TYP MAX UNIT VCC+0.3 V 0.8 V -150 µΑ CONDITION LVCMOS control inputs (MR, PLL_En, Sel_CLK, Man_Override, Alarm_Reset) VIH Input voltage high VIL Input voltage low IIN Input currenta 2.0 100 VIN =VCC or VIN =GND LVCMOS Control Outputs VOH Output High Voltage VOL Output Low Voltage 2.0 V IOH=-10mA 0.55 V IOL=10mA +100 µΑ VIN =VCC or VIN =GND LVPECL clock inputs (CLK, CLK)b IIN Input current LVPECL clock outputs (Qa[1:0], Qa[1:0], Qb[2:0], Qb[2:0]) VOH Output high voltage VCC-1.2 VCC-0.7 V Termination 50Ω to VTT VOL Output low voltage VCC-1.9 VCC-1.45 V Termination 50Ω to VTT Supply Current IGND Maximum ground supply current - gnd pins 180 mA GND pins ICCPLL Maximum PLL power supply - VCC_PLL pin 15 mA VCCPLL pin a. Inputs have internal pullup/pulldown resistors which affect the input current. b. Clock inputs driven by LVPECL compatible signals. 5 xr PRELIMINARY XRK7933 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER REV. P1.0.1 AC CHARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C) (NOTE 5) SYMBOL fref PARAMETER Input Reference Frequency fVCO PLL VCO Lock Range fMAX Output Frequency MIN MAX UNIT CONDITION 16.67 33.3 MHz Locked 200 400 MHz Qa Output used for feedback 16.67 50 33.3 100 25 75 % -150 150 5 ps ns 0.25 1.3 V VCC-1.7 VCC-0.3 V 50 80 ps ps Qa[1:0]d 50 ps/cycle Qb[2:0]d 25 Qa[1:0]e 400 Qb[2:0]e 200 ÷12 feedback MHz Qa[1:0] Qa[1:0] frefDC tpd Reference Input Duty Cycle Propagation Delay CLKn to Ext_FB (SPO) c CLKn to Q (Bypass) VPP Differential input voltage (peak-to-peak) VCMR Differential input crosspoint voltage tskew Output Skew Within Qa[1:0] or Qb[2:0] All outputs ∆per/cycle TYP PLL_EN = 1 PLL_EN = 0 Rate of change of periods tpw Output duty cycle tjitter 45 55 % Cycle-to-cyle jitter, Standard deviation (RMS) 40 ps tlock Maximum PLL lock time 10 ms tr/tf Output Rise/Fall time 700 ps 50 @fref = 25MHz c. Static phase offset between the selected reference clock and the feedback signal. d. Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. (See Applications Information section for more detail) e. Specification holds for a clock switch between two signals no greater than ±π out of phase. Delta period change per cycle is averaged over the clock switch excursion. f. PECL output termination is 50 ohms to VCC – 2.0V. g. VPP is the minimum differential input voltage swing required to maintain AC characteristic including SPO, device and part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB. h. VCMR is the crosspoint of the differential input signal. Normal operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP specification. Violation of VCMR or VPP impacts the SPO, device and part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB. 6 XRK7933 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER xr REV. P1.0.1 APPLICATIONS INFORMATION The XRK7933 is a dual clock PLL with on–chip Intelligent Dynamic Clock Switch circuitry. DEFINITIONS primary clock: The input CLK selected by Sel_Clk. secondary clock: The input CLK NOT selected by Sel_Clk. PLL reference signal: The CLK selected as the PLL reference signal by Sel_Clk or the Intelligent Dynamic Clock Switch. The Intelligent Dynamic Clock Switch can override Sel_Clk. STATUS FUNCTIONS Clk_Selected: Clk_Selected (L) indicates CLK0 is selected as the PLL reference signal. Clk_Selected (H) indicates CLK1 is selected as the PLL reference signal. Inp0bad, Inp1bad: Inp0bad is latched (H) when CLK0 is stuck (H) or (L) for at least one Ext_FB period, or if one of the inputs CLK0 or CLK0 is floating. Inp1bad is latched (H) when CLK1 is stuck (H) or (L) for at least one Ext_FB period, or if one of the inputs CLK1 or CLK1 is floating. Both Inp0bad and Inp1bad are latched (H) when Ext_FB is stuck (H) or (L) for at least one Qa period, or if one of the inputs Ext_FB or Ext _FB is floating. Both Inp0bad and Inp1bad are cleared (L) on assertion of Alarm_Reset. The status functions Inp0bad and Inp1bad are active for Man_Override (H) or (L). CONTROL FUNCTIONS Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock. Sel_Clk (H) selects CLK1 as the primary clock. Alarm_Reset: Asserted by a negative edge. Generates a one–shot reset pulse that clears INPUT_BAD latches and Clk_Selected latch. PLL_En: While (L), the PLL reference signal is substituted for the VCO output. MR: While (L), internal dividers are held in reset which holds all Q outputs LOW. MAN OVERRIDE (H) (IDCS is disabled, PLL functions normally). PLL reference signal (as indicated by Clk_Selected) will always be the CLK selected by Sel_Clk. If Ext_FB misses at least one pulse, Qa and Qb outputs will drop to a minimum frequency (~20MHz) for 1-uS, or until Ext_FB shows any activity, whichever is longer. This prevents the Qa and Qb frequencies from rising due the PLL incorrectly interpreting an intermittent Ext_FB as a VCO running too slow. MAN OVERRIDE (L) Intelligent Dynamic Clock Switch is enabled. The first CLK to fail will latch it’s INP_BAD (H) status flag and select the other input as the Clk_Selected for the PLL reference clock. Once latched, the Clk_Selected and INP_BAD remain latched until assertion of Alarm_Reset which clears all latches (INP_BADs are cleared and Clk_Selected = Sel_Clk). If both Inp0bad and Inp1bad are (H), either due to both CLK0 and CLK1 having missed at least 1 pulse each or Ext_FB having missed at least 1 pulse, then Qa and Qb outputs will drop to a minimum frequency (~20MHz) until such time as Alarm_Reset_b is asserted. NOTE: If both CLKs are bad when Alarm_Reset is asserted, both INP_BADs will be latched (H) after one Ext_FB period and Clk_Selected will be latched (L) indicating CLK0 is the PLL reference signal. While neither INP_BAD is latched (H), the Clk_Selected can be freely changed with Sel_Clk. Whenever a CLK switch occurs, (manually or by the Intelligent Dynamic Clock Switch), following the next negative edge of the newly selected PLL reference signal, the next positive edge pair of Ext_FB and the newly selected PLL reference signal will slew to alignment. To calculate the overall uncertainty between the input CLKs and the outputs from multiple XRK7933’s, the following procedure should be used. Assuming that the input CLKs to all XRK7933’s are exactly in phase, the total uncertainty will be the sum of the static phase offset, max I/O jitter, and output to output skew. During a dynamic switch, the output phase between two devices may be increased for a short period of time. If the two input CLKs are 400ps out of phase, a dynamic switch of an XRK7933 will result in an instantaneous phase change of 400ps to the PLL reference signal without a corresponding change in the output phase (due to the limited response of the PLL). As a result, the I/O phase of a device, undergoing this switch, will initially 7 xr REV. P1.0.1 PRELIMINARY XRK7933 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER be 400ps and diminish as the PLL slews to its new phase alignment. This transient timing issue should be considered when analyzing the overall skew budget of a system. HOT INSERTION AND WITHDRAWAL In PECL applications, a powered up driver will experience a low impedance path through an XRK7933 input to its powered down VCC pins. In this case, a 100 ohm series resistance should be used in front of the input pins to limit the driver current. The resistor will have minimal impact on the rise and fall times of the input signals. ACQUIRING FREQUENCY LOCK 1. While the XRK7933 is receiving a valid CLK signal, assert Man_Override HIGH. 2. The PLL will phase and frequency lock within the specified lock time. 3. Apply a HIGH to LOW transition to Alarm_Reset to reset Input Bad flags. 4. De–assert Man_Override LOW to enable Intelligent Dynamic Clock Switch mode. 8 xr XRK7933 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER REV. P1.0.1 PACKAGE DIMENSIONS 32 LEAD THIN QUAD FLAT PACK (7 x 7 x 1.4 mm TQFP) rev. 2.00 D D1 24 17 16 25 D D1 32 9 1 8 B A2 e C A α Seating Plane A1 L Note: The control dimension is the millimeter column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.055 0.063 1.40 1.60 A1 0.002 0.006 0.05 0.15 A2 0.053 0.057 1.35 1.45 B 0.012 0.018 0.30 0.45 C 0.004 0.008 0.09 0.20 D 0.346 0.362 8.80 9.20 D1 0.272 0.280 6.90 7.10 e 0.0315 BSC 0.80 BSC L 0.018 0.030 0.45 0.75 α 0° 7° 0° 7° 9 XRK7933 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER xr REV. P1.0.1 REVISION HISTORY REVISION # DATE DESCRIPTION A1.0.0 August 2004 Initial release. P1.0.0 January 2005 Revised Electrical characteristics, Application Section, changed to Preliminary. P1.0.1 March 2005 Minor style edits. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet March 2005. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 10