IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE LOW VOLTAGE PLL CLOCK DRIVER FEATURES: • • • • • • • • IDT5V9351 DESCRIPTION: Fully integrated PLL Output frequency up to 200MHz 2.5V and 3.3V Compatible Compatible with PowerPC™, Intel, and high performance RISC microprocessors Output frequency configurable Cycle-to-cycle jitter max. 22ps RMS Compatible with MPC9351 Available in TQFP package The IDT5V9351 is a high performance, zero delay, low skew, phase-lock loop (PLL) clock driver. It has four banks of configurable outputs. The IDT5V9351 uses a differential PECL reference input and an external feedback input. These features allow the IDT5V9351 to be used as a zero delay, low skew fan-out buffer. REF_SEL allows selection between PECL input or TCLK, a CMOS clock driver input. If PLL_EN is set to low and REF_SEL to high, it will bypass the PLL. By doing so, the IDT5V9351 will be in clock buffer mode. Any clock applied to TCLK will be divided down to four output banks. When PLL_EN is set high, PLL is enabled. Any clock applied to TCLK will be clocked in both phase and frequency to FBIN. PECL clock is activated by setting REF_SEL to low. FUNCTIONAL BLOCK DIAGRAM PECL_CLK (pullup) 0 PECL_CLK 0 ÷2 REF (pulldown) tCLK REF_SEL FBIN 1 1 (pulldown) (pulldown) ÷4 ÷8 PLL 0 D Q QA D Q QB 1 FB 200 - 400MHz 0 1 PLL_En (pullup) QC0 0 fSELA (pulldown) D Q QC1 1 fSELB (pulldown) fSELC (pulldown) QD0 QD1 fSELD 0 (pulldown) D Q QD2 1 QD3 QD4 OE (pulldown) The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE MARCH 2003 1 © 2003 Integrated Device Technology, Inc. DSC-5972/16 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) 32 31 30 29 28 27 GND QB VCC QA GND TCLK Symbol PLL_EN REF_SEL PIN CONFIGURATION 26 25 VCCA 1 24 QC0 FBIN 2 23 VCC fSELA 3 22 QC1 fSELB 4 21 GND fSELC 5 20 QD0 fSELD 6 19 VCC GND 7 18 QD1 PECL_CLK 8 17 GND Max. Unit –0.3 to +4.6 V Input Voltage –0.3 to VCC+0.3 V DC Output Voltage –0.3 to VCC+0.3 V ±20 mA ±50 mA –55 to +150 °C Supply Voltage VI VO IIN Input Current IO DC Output Current TSTG Storage Temperature NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C, F = 1.0MHz) 16 Symbol QD2 15 VCC 14 QD3 13 GND 12 QD4 11 VCC 10 OE PECL_CLK 9 Description VCC Parameter Min. Typ. Max. Unit CIN Input Capacitance 4 Power Dissipation Capacitance — — pF CPD — — 10 pF TQFP TOP VIEW GENERAL SPECIFICATIONS Symbol LOGIC DIAGRAM(1,2) RF VCCA VCC CF 10nF VCC 33...100nF NOTES: 1. IDT5V9351 requires an external RC filter for the analog power supply pin VCCA. 2. For VCC = 2.5V, RF = 9-10Ω, CF = 22µF. For VCC = 3.3V, RF = 5-15Ω, CF = 22µF. 2 Description Min. Typ. VCC/2 Max. Unit V TT Output Termination Voltage HBM ESD (Human Body Model) 2000 V V LU Latch-Up Immunity 200 mA IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION Terminal Name No. Type PECL-CLK 8, 9 I Description Differential clock reference, LOW voltage positive ECL input TCLK 30 I Single-ended reference clock signal or test clock FBIN 2 I Feedback signal input PECL-CLK REF_SEL 32 I Reference clock input fSEL(D:A) 3, 4, 5, 6 I Frequency control pin OE 10 I Output enable/disable QA 28 O Bank A clock output QB 26 O Bank B clock output QC (1:0) 22, 24 O Bank C clock output QD (4:0) 12, 14, 16, O Bank D clock output 18, 20 VCCA 1 PWR Positive power supply for PLL VCC 11, 15, 19, PWR Positive power supply for I/O and core GND 7, 13, 17, 21, 23, 27 Ground Negative power supply 25, 29 PLL_EN 31 I PLL enable input. When set HIGH, PLL is enabled. When set LOW, PLL is disabled. FUNCTIONALITY Control REF_SEL PLL_EN OE FSELA FSELB FSELC FSELD Default 0 1 0 0 0 0 0 0 Selects PECL_CLK as reference clock Test mode with PLL Disabled Outputs enabled QA = VCO ÷ 2 QB = VCO ÷ 4 QC = VCO ÷ 4 QD = VCO ÷ 4 1 Selects TCLK as reference clock PLL Enabled Outputs disabled QA = VCO ÷ 4 QB = VCO ÷ 8 QC = VCO ÷ 8 QD = VCO ÷ 8 NOTE: 1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to FBIN. 3 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE FUNCTION TABLE(1) INPUTS fSELA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 fSELB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 fSELC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 fSELD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA 2 * CLK 2 * CLK 4 * CLK 4 * CLK 2 * CLK 2 * CLK 4 * CLK 4 * CLK CLK CLK 2 * CLK 2 * CLK CLK CLK 2 * CLK 2 * CLK OUTPUTS QB CLK CLK 2 * CLK 2 * CLK CLK ÷ 2 CLK ÷ 2 CLK CLK CLK CLK 2 * CLK 2 * CLK CLK ÷ 2 CLK ÷ 2 CLK CLK QC CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK QD CLK CLK ÷ 2 2 * CLK CLK CLK CLK ÷ 2 2 * CLK CLK CLK CLK ÷ 2 2 * CLK CLK CLK CLK ÷ 2 2 * CLK CLK NOTE: 1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to FBIN. DC ELECTRICAL CHARACTERISTICS TA = -40°C to +85°C, VCC = 3.3V ± 5% Symbol VIH VIL VPP VCMR VOH VOL ZOUT IIN ICC ICCPLL Parameter Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode(1) Output HIGH Voltage(2) Output LOW Voltage(2) Output Impedance Input Leakage Current Maximum Quiescent Supply Current Maximum PLL Supply Current Test Conditions LVCMOS Inputs LVCMOS Inputs PECL_CLK PECL_CLK IOH = -24mA IOL = 24mA IOL = 12mA All VCC Pins VCCA Only Min. 2 — 250 1 2.4 — — — — — — Typ. — — — — — — — 14 - 17 — — 3 Max VCC + 0.3 0.8 — VCC - 0.6 — 0.55 0.3 — ±150 1 5 Unit V V mV V V V Ω µA mA mA NOTES: 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The IDT5V9351 outputs can drive series or paralell terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge. 4 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE PLL INPUT REFERENCE CHARACTERISTICS VCC = 3.3V ± 5%, TA = -40°C to +85°C Symbol tR, tF fREF fREFDC Parameter TCLK Input Rise/Fall Levels, 0.8V to 2V Reference Input Frequency (1) ÷ 2 feedback ÷ 4 feedback ÷ 8 feedback Static Test Mode Reference Input Duty Cycle Min. — Max 1 Unit ns 100 200 50 100 MHz 25 0 25 50 300 75 % NOTE: 1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs. AC ELECTRICAL CHARACTERISTICS (1) TA = -40°C to +85°C, VCC = 3.3V ± 5% Symbol tR, tF Parameter Output Rise/Fall Time Conditions 0.55V to 2.4V Min. 0.1 Typ. — Max 1 Unit ns 500 — 1000 mV — 50 50 50 — VCC - 0.9 55 52.5 51.75 150 V % MHz VPP Peak-to-Peak Input Voltage LVPECL VCMR Common Mode Range LVPECL 100-200 MHz 50-100 MHz 25-50 MHz tSK(O) Output to Output Skew 1.2 45 47.5 48.75 — fVCO PLL VCO Lock Range 200 — 400 — 200 Maximum Output Frequency ÷ 2 output ÷ 4 output ÷ 8 output 100 fMAX 50 — 100 25 — 50 tPD Propagation Delay (Static Phase Offset) TCLK to FBIN PECL_CLK to FBIN -50 25 — — 150 325 tPW (2) Output Duty Cycle ps MHz ps tPLZ, tPHZ Output Disable Time — — 10 ns tPZL, tPZH Output Enable Time — — 10 ns BW PLL Closed Loop Bandwidth ÷ 2 feedback ÷ 4 feedback ÷ 8 feedback -3db point of — 9 - 20 — PLL transfer — 3 - 9.5 — characteristic MHz — 1.2 - 2.1 — tJ Cycle-to-Cycle Jitter ÷ 4 feedback (Single Output Frequency Configuration) RMS Value — 10 22 ps tJIT (PER) RMS Value — 8 15 ps tJIT (φ) Period Jitter ÷ 4 feedback (Single Output Frequency Configuration) I/O Phase Jitter — 4 - 17 — ps tLOCK Maximum PLL Lock Time — — 1 ms RMS Value NOTES: 1. AC Characteristics apply for parallel output termination of 50Ω to VTT. 2. VCMR(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within VPP(AC) specifications. 5 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS TA = -40°C to +85°C, VCC = 2.5V ± 5% Symbol VIH VIL VPP VCMR VOH VOL IIN C IN ZOUT CPD ICC ICCPLL Parameter Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode(1) Output HIGH Voltage(2) Output LOW Voltage(2) Input Current Input Capacitance Output Impedance Power Dissipation Capacitance Maximum Quiescent Supply Current Maximum PLL Supply Current Test Conditions LVCMOS Inputs LVCMOS Inputs PECL_CLK PECL_CLK IOH = -15mA IOL = 15mA Min. 1.7 — 250 1 1.8 — — — — — — — All VCC Pins VCCA Only Typ. — — — — — — — 4 17 - 20 10 — 3 Max VCC + 0.3 0.7 — VCC - 0.6 — 0.6 ±150 — — — 1 5 Unit V V mV V V V µA pF Ω pF mA mA NOTES: 1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within the VCMR range and the input swing lies within the VPP specification. 2. The IDT5V9351 outputs can drive series or paralell terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge. PLL INPUT REFERENCE CHARACTERISTICS VCC = 2.5V ± 5%, TA = -40°C to +85°C Symbol tR, tF fREF fREFDC Parameter TCLK Input Rise/Fall Levels, 0.7V to 1.7V Reference Input Frequency (1) ÷ 2 feedback ÷ 4 feedback ÷ 8 feedback Reference Input Duty Cycle Min. — Max 1 100 200 50 100 MHz 25 25 50 75 % NOTE: 1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs. 6 Unit ns IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (1) TA = -40°C to +85°C, VCC = 2.5V ± 5% Symbol tR, tF Parameter Output Rise/Fall Time Conditions 0.6V to 1.8V Min. 0.1 Typ. — Max 1 Unit ns 500 — 1000 mV — 50 50 50 — VCC - 0.6 55 52.5 51.75 150 V % MHz VPP Peak-to-Peak Input Voltage LVPECL VCMR Common Mode Range LVPECL 100-200 MHz 50-100 MHz 25-50 MHz tSK(O) Output to Output Skew 1.2 45 47.5 48.75 — fVCO PLL VCO Lock Range 200 — 400 — 200 Maximum Output Frequency ÷ 2 output ÷ 4 output ÷ 8 output 100 fMAX 50 — 100 25 — 50 tPD Input to FBIN Delay TCLK to FBIN PECL_CLK to FBIN -100 0 — — 100 300 tPLZ, tPHZ Output Disable Time — — 12 ns tPZL, tPZH Output Enable Time — — 12 ns tPW BW (2) Output Duty Cycle PLL Closed Loop Bandwidth ÷ 2 feedback ÷ 4 feedback ÷ 8 feedback -3db point of — 4 - 15 — PLL to transfer — 2-7 — characteristic ps MHz ps MHz — 0.7 - 2 — tJ Cycle-to-Cycle Jitter ÷ 4 feedback (Single Output Frequency Configuration) RMS Value — 10 22 ps tJIT (PER) RMS Value — 8 15 ps tJIT (φ) Period Jitter ÷ 4 feedback (Single Output Frequency Configuration) I/O Phase Jitter RMS Value — 6 - 25 — ps tLOCK Maximum PLL Lock Time — — 1 ms NOTES: 1. AC Characteristics apply for parallel output termination of 50Ω to VTT. 2. VCMR(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within VPP(AC) specifications. 7 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS IDT5V9351 D.U.T. ZO = 50Ω Pulse Generator Z = 50Ω ZO = 50Ω RT = 50Ω RT = 50Ω V TT V TT TCLK AC Test Reference for VCC = 2.5V and VCC = 3.3V IDT5V9351 D.U.T. ZO = 50Ω ZO = 50Ω Pulse Generator Z = 50Ω RT = 50Ω RT = 50Ω VTT V TT PECL_CLK AC Test Reference VCC 2V 0.8V 0V 2V VCC/2 Input 0.8V 1ns VCC/2 tCLK 1ns Input Characteristics for 3.3V VCC/2 FBIN tPD VCC 1.7V 0.7V 0V 1.7V VCC/2 Input 0.7V 1ns PECL_CLK PECL_CLK 1ns Prop Delay Input Characteristics for 2.5V VOH 1.8V 1.8V VCC/2 Output tR VCC/2 0.6V VOL 0.6V VOH 2.4V 2.4V 0.55V VOL 0.55V Output tR tF Output Test Conditions for VCC = 2.5V ± 5% tF Output Test Conditions for VCC = 3.3V ± 5% 8 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE CCLK FBIN TJ(0) = T0 - T1 MEAN I/O Jitter VCC VCC/2 GND tP T0 tPW = tP/T0 x 100% Output Duty Cycle TJ = Tn - Tn+1 Tn Tn+1 Cycle-to-Cycle Jitter TJ(PER) = Tn - 1/f0 T0 Period Jitter 9 IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type XX Package X Process I -40°C to +85°C (Industriall) PR Thin Quad Flat Pack 5V9351 Low Voltage PLL Clock Driver CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 10 for Tech Support: [email protected] (408) 654-6459