Genesys Logic, Inc. GL9714 PCI ExpressTM PIPE x4 PHY Datasheet Revision 1.32 Apr. 16, 2007 GL9714 PCI ExpressTM PIPE x4 PHY Copyright: Copyright © 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Disclaimer: ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http ://www.genesyslogic.com ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 2 GL9714 PCI ExpressTM PIPE x4 PHY Revision History Revision Date Description 1.00 09/27/2004 First formal release 1.10 04/04/2005 Update for mass production version 1.11 04/12/2005 Revise register description(SW, DEM), p.19 1.12 04/20/2005 1. Add operating current for DC electrical characteristics in Table7.1 2. Correct Power Consumption 1.13 09/20/2005 Modify Package Dimension ,Ch9 , p.39 1. Add “Bottom View”, Ch3.1, p.10 2. Change Pin E15 from “TXDK1” to “TXDKA”, Table3.1, p.11 3. Change TXDKA~D type from “O” to “I”, Table3.4, p.15 4. Add a column “I/O Standard”, Table3.4, p.15 5. Change VDDPLL from “C18” to “C8”, Table3.4, p.16 6. Add comment for SCC and OPMODE[1:0], Table3.4 , p.17 1. Update Table3.4, p.15~p.17 2. Add Table3.5, p.17 3. Modify the default value of REG0 and REG1 in Table4.1, p.18 4. Modify Ch4.2 Registers Descriptions for REG0 and REG1, p.19 5. Add Ch 4.3, p.21~p.24 6. Update Table 7.5 and Table 7.6 for power consumption, p.36~p.37 7. Change TXDx to RXDx, Figure8.4, p.41 8. The minimum and maximum value of TCYCLE, Table8.2 and Table 8.5, p.42 1. Update Table 7.9 for temperature ranges (p.39) 2. Update Table 8.1~8.4 for output delay of RX bus (p.41~p.42) 1. Modify the description of OSC25MI and OSC25MO signals, Table 3.4, p.17 2. Update Table 7.1 for deleting IDD1-X4, IDD2-X4, IDD3-X4, IDD1-X2, IDD2-X2, and IDD3-X2 six items, p.34 3. Update Table 7.9 for deleting the ISUPPLY-1.8 item and adding θJA, ΨJT and θJC three items, p.39 1.14 10/13/2005 1.16 11/15/2005 1.17 12/15/2005 1.18 03/15/2006 1.19 03/28/2006 Swap the Pin Out of OSC25MI and OSC25MO in Table 3.1~Table 3.4. 1.20 03/30/2006 Update Table 7.9 for the illustration and the value of thermal parameters, p.39 1.21 04/26/2006 1.22 05/08/2006 1.23 06/09/2006 1.24 06/20/2006 1.25 07/31/2006 1.26 10/27/2006 Add Duty-H field for Table 8.3 and Table 8.5, p.43 1.30 02/06/2007 Update Table 8.1~8.5 for timing issue, p.42~44 1.31 03/19/2007 1. Add a note to Table 8.1, p.42 2. Update Table 7.4, 7.5 for the power consumption of reference voltage 1.25V, p37~p38, correct the index of table7.2, 7.3, p35 1.32 04/16/2007 Complies with PCI Express Base Specification rev. 1.1, p9 Divide Table 7.9 into Table 7.9(Temperature Range) and Table 7.10(Thermal Characteristics), p.39 Update Fig. 8.1, 8.2 and Table 8.1~8.5 for PIPE input and output timing characteristic, p.40~p.42 Update Table 8.1~8.5 for the description of TCO and TOH, p.41~p.42 1.Update Table 3.5 for the parameter of buffer I/O, p.17 2.Remove Table 7.2, p.34 1.Remove REN and PLPBK bits of SMBus register REGC, p.20 2.Add REG14 ~ REG17 for SLPBK error count result, p.21 3.Add “PS: Please write “0” to…….” description, p.21 ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 3 GL9714 PCI ExpressTM PIPE x4 PHY TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION................................................... 8 CHAPTER 2 FEATURES .............................................................................. 9 CHAPTER 3 PIN ASSIGNMENT .............................................................. 10 3.1 PINOUT ..................................................................................................... 10 3.2 BALL OUT ................................................................................................. 10 3.3 PIN LIST.................................................................................................... 11 3.4 PIN DESCRIPTIONS ................................................................................... 15 CHAPTER 4 REGISTERS .......................................................................... 18 4.1 REGISTERS BASE ADDRESS ...................................................................... 18 4.2 REGISTERS DESCRIPTIONS ...................................................................... 19 4.3 SMBUS PROTOCOL .................................................................................. 22 CHAPTER 5 BLOCK DIAGRAM.............................................................. 26 5.1 SIMPLIFIED DIAGRAM .............................................................................. 26 5.2 TRANSMITTER DATA PATH PER LANE .................................................... 27 5.3 RECEIVER DATA PATH PER LANE ........................................................... 28 CHAPTER 6 FUNCTION DESCRIPTION ............................................... 29 6.1 CLOCK AND RESET................................................................................... 29 6.2 RECEIVER DETECTION ............................................................................ 29 6.3 BEACON TRANSMITTING AND DETECTION.............................................. 29 6.4 RECEIVER STATUS REPORT ..................................................................... 29 6.5 LOOPBACK................................................................................................ 30 6.6 POLARITY INVERSION .............................................................................. 30 6.7 SETTING NEGATIVE DISPARITY............................................................... 30 6.8 BEHAVIOR SUMMARY .............................................................................. 31 6.9 POWER SAVING SUPPORT ........................................................................ 31 6.10 OPERATION MODE AND MULTI-FUNCTIONAL PINS ............................. 32 CHAPTER 7 ELECTRICAL CHARACTERISTICS............................... 35 7.1 DC ELECTRICAL CHARACTERISTICS ...................................................... 35 ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 4 GL9714 PCI ExpressTM PIPE x4 PHY 7.2 TRANSMIT AND RECEIVE LATENCY TIME .............................................. 35 7.3 TRANSITION TIME OF POWER STATE ...................................................... 35 7.4 POWER CONSUMPTION ............................................................................ 37 7.5 DIFFERENTIAL TRANSMITTER AND RECEIVER SERIAL OUTPUT ........... 39 7.6 RECOMMENDED OPERATING CONDITIONS ............................................. 40 CHAPTER 8 PIPE TIMING CHARACTERISTICS ............................... 41 8.1 INPUT SETUP, HOLD TIME AND OUTPUT TIMING ................................... 41 8.2 REFERENCE TIMING INFORMATION ........................................................ 44 CHAPTER 9 PACKAGE DIMENSION..................................................... 45 CHAPTER 10 ORDERING INFORMATION .......................................... 46 ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 5 GL9714 PCI ExpressTM PIPE x4 PHY LIST OF FIGURES FIGURE 3.1 - 233 PIN LFBGA PINOUT DIAGRAM ............................................................ 10 FIGURE 4.1 – SMBUS TOPOLOGY OF GL9714.................................................................. 22 FIGURE 4.2 – DATA VALIDITY ........................................................................................... 22 FIGURE 4.3 – START AND STOP CONDITION.................................................................. 23 FIGURE 4.4 – ACK AND NACK SIGNALING OF SMBUS ................................................... 23 FIGURE 4.5 – SMBUS PACKET PROTOCOL DIAGRAM ELEMENT KEY............................. 24 FIGURE 4.6 – WRITE BYTE PROTOCOL ............................................................................. 24 FIGURE 4.7 – READ BYTE PROTOCOL ............................................................................... 24 FIGURE 4.8 – THE MINIMUM WAIT TIME FROM POWER ON TO PROGRAMMING REGISTERS ......................................................................................................................... 25 FIGURE 5.1 - SIMPLIFIED DIAGRAM .................................................................................. 26 FIGURE 5.2 - TRANSMITTER DATA PATH PER LANE ......................................................... 27 FIGURE 5.3 - RECEIVER DATA PATH PER LANE ............................................................... 28 FIGURE 8.1 – DEFINITION OF INPUT SETUP AND HOLD TIME .......................................... 41 FIGURE 8.2 – DEFINITION OF OUTPUT TIMING................................................................. 42 FIGURE 9.1 - GL9714 233 PIN LFBGA PACKAGE ........................................................... 45 ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 6 GL9714 PCI ExpressTM PIPE x4 PHY LIST OF TABLES TABLE 3.1 - BALL OUT....................................................................................................... 10 TABLE 3.2 - NUMERIC PIN LIST ......................................................................................... 11 TABLE 3.3 - ALPHABETIC PIN LIST ................................................................................... 13 TABLE 3.4 - PIN DESCRIPTIONS ......................................................................................... 15 TABLE 3.5 - PARAMETER OF BUFFER I/O ......................................................................... 17 TABLE 4.1 - BASE ADDRESS FOR REGISTERS .................................................................... 18 TABLE 6.1 - PIN FUNCTIONS .............................................................................................. 32 TABLE 7.1 - DC ELECTRICAL CHARACTERISTICS ............................................................ 35 TABLE 7.2 - TRANSMIT AND RECEIVE LATENCY TIME .................................................... 35 TABLE 7.3 – TRANSITION TIME OF POWER STATE ........................................................... 35 TABLE 7.4 – TYPICAL POWER CONSUMPTION WITH 2-LANES, 4-LANES, AND 1.2V DIFFERENTIAL PEAK TO PEAK OUTPUT VOLTAGE .......................................................... 37 TABLE 7.5 – TYPICAL POWER CONSUMPTION WITH SINGLE-LANE AND 1.2V DIFFERENTIAL PEAK TO PEAK OUTPUT VOLTAGE .......................................................... 38 TABLE 7.6 – TRANSMITTER SERIAL OUTPUT.................................................................... 39 TABLE 7.7 – RECEIVER SERIAL OUTPUT .......................................................................... 40 TABLE 7.8 – TEMPERATURE RANGE ................................................................................. 40 TABLE 7.9 – THERMAL CHARACTERISTICS ...................................................................... 40 TABLE 8.1 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 8-BIT SDR MODE ... 42 TABLE 8.2 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 8-BIT DDR MODE .. 43 TABLE 8.3 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 16-BIT MODE .......... 43 TABLE 8.4 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 10-BIT SDR MODE . 43 TABLE 8.5 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 10-BIT DDR MODE 44 TABLE 8.6 – REFERENCE TIMING INFORMATION ............................................................. 44 TABLE 10.1 - ORDERING INFORMATION ........................................................................... 46 ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 7 GL9714 PCI ExpressTM PIPE x4 PHY CHAPTER 1 GENERAL DESCRIPTION The GL9714 is a 4-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel’s PHY Interface for the PCI Express Architecture rev. 1.0. It integrates a quad SerDes and the Physical Coding Sublayer (PCS) which performs 8b/10b encoding and decoding, elastic buffer and receiver detection, data serialization and deserialization for each lane. The quad SerDes in the GL9714 supports an effective serial interface speed (2.5 Gb/s) of data bandwidth for each lane, intended for use in ultrahigh-speed bi-directional data transmission system. The GL9714 can also be externally configured for various combinations of lane number and parallel bus width which is flexible and suitable for x1, x2 or x4 lane implementation. It also supports four operational states for power management to minimize power consumption. For production and self-test purposes, the GL9714 provides BIST and an internal loopback capability. The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over an on-chip termination resister of 50 Ohm +/- 10%. This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel. It is then reconstructed into its original parallel format. The maximum data transfer rate in each direction is 1 Giga byte per second with the 4-lane configuration. It also offers various power saving modes to significantly reduce power consumption as well as scalability for a higher data rate in the future. ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 8 GL9714 PCI ExpressTM PIPE x4 PHY CHAPTER 2 FEATURES Complies with PCI Express Base Specification rev. 1.1 Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0 Integrates quad 2.5 gigabit per second (Gbps) Serializer/Deserializer Supports 8-bit or 10-bit parallel interface @250MHz for x1, x2 and x4 implementation Supports 16-bit parallel interface @125MHz for x1 and x2 configuration Supports DDR configuration for 8-bit or 10-bit mode Beacon transmission and reception Receiver detection Transmission and detection of electrical idle Clock tolerance for 600 ppm in frequencies between bit rates at the two end of a Link On-chip 8-bit/10-bit encoding/decoding and comma alignment On-chip PLL provides clock synthesis 1.8-V power supply for core 2.5-V power supply for IO Above 2.0 kV ESD protection 0.18 µm process Available in LFBGA-233 package ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 9 GL9714 PCI ExpressTM PIPE x4 PHY CHAPTER 3 PIN ASSIGNMENT 3.1 Pinout 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U Bottom View Figure 3.1 - 233 Pin LFBGA Pinout Diagram 3.2 Ball Out Table 3.1 - Ball Out A B C D E F G H J K L M N P R 1 2 REFCLKP TXND TXPD RXDD7 VDD25 RXDD1 RXSTSD1 VDD25 TXDD6 VSS TXDD0 VSS RXDC7 VSS RXDC1 RXSTSC1 REFCLKN OSC25MO OSC25MI RXDKD VSS TXCMPD TXDD4 TXDD2 VDD25 VSS VSS RXDC5 VDD25 RXDC3 3 4 5 6 7 8 9 RXND VDDRXD TXNC VDDTXC RXNC VDDRXC VSSTXD RXPD VSSRXD TXPC VSSTXC RXPC VSSRXC NC VDD18 NC NC VSSTXC VDDPLL NC RXDD3 VSS VSS NC VDD18 RTERM VSSPLL RXDD4 RXDD5 RXDD2 RXDD6 RXSTSD2 RXDD0 VSS VSS VSS TXDD7 RXSTSD0 VSS VSS VSS TXDD5 TXDD3 VSS VSS VSS TXDD1 VDD12 VSS VSS VSS TXDKD VDD18 VSS VSS VSS VDD18 RXDC4 RXDC6 RXDC0 RXDC2 RXSTSC2 RXSTSC0 TXDC3 TXDKC RXIDLED VSS OPMODE0 TXCMPC TXDC7 TXDC5 TXDC1 VSS RXPLRD VDDTXD ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 10 GL9714 PCI ExpressTM PIPE x4 PHY T U VSS VDD25 TXDC4 TXDC6 VSS TXDC2 TXDC0 1 2 3 4 5 11 12 13 14 RXDKC 10 VDD25 VDD18 TXIDLED RXIDLEC RXPLRC PHYSTS RXVLDD RXVLDC TXIDLEC VDD25 RXNB VDDRXB TXNA A TXPB VSSTXB RXPB VSSRXB TXPA B NC VDD18 NC TXDA1 C VDD18 NC NC NC TXDA0 TXDA3 D TXDA5 E RXSTSA0 F RXSTSA1 VSS VSS G VSS VSS RXDA5 H VSS VSS VDD12 J VSS VSS TXDB2 K VSS VSS TXCMPB L RXSTSB1 M RXDB3 N PD1 RXVLDB RXVLDA RXDB7 RXDB5 P TXNB R SCC VDDTXB 6 7 15 16 RXNA VSSTXA RXPA VSSGR TXDA6 TXDA4 VDD25 TXDKA TXDA2 TXCMPA RXDA0 RXDA1 RXDA2 RXDA3 RXDA7 VSS RXDA6 VDD25 TXDKB TXDB6 TXDB1 TXDB4 TXDB3 RXDKB TXDB7 RXDB1 VSS VDDTXA TXDET/ TXIDLEB VDD25 TXIDLEA RXDB4 LPBK PD0 RXIDLEB RXIDLEA PCLK VSS T TESTD U OPMODE1 TESTC 10 11 RST_N RXPLRB VSS RXPLRA 12 13 14 15 RXDB0 8 9 17 VDDRXA VSSRXA TXDA7 RXSTSA2 RXDKA VDD25 RXDA4 VDD18 VDD18 NC TXDB0 VSS TXDB5 RXSTSB0 VDD25 RXDB2 RXSTSB2 RXDB6 VDD25 16 17 3.3 Pin List Table 3.2 - Numeric Pin List Pin# Pin Name Pin# Pin Name Pin# Pin Name Pin# Pin Name Pin# Pin Name A1 REFCLKP C1 OSC25MO E1 RXDKD G1 TXCMPD J1 TXDD2 A2 TXND C2 RXDD7 E2 RXDD1 G2 VDD25 J2 VSS A3 VDDTXD C3 NC E3 RXDD4 G3 RXSTSD2 J3 TXDD5 A4 RXND C4 VDD18 E4 RXDD5 G4 RXDD0 J4 TXDD3 A5 VDDRXD C5 NC E5 G5 J5 A6 TXNC C6 NC E6 G6 J6 A7 VDDTXC C7 VSSTXC E7 G7 VSS J7 VSS A8 RXNC C8 VDDPLL E8 G8 VSS J8 VSS A9 VDDRXC C9 NC E9 G9 VSS J9 VSS A10 TXNB C10 VDD18 E10 G10 VSS J10 VSS A11 VDDTXB C11 NC E11 G11 VSS J11 VSS A12 RXNB C12 VDD18 E12 G12 J12 A13 VDDRXB C13 NC E13 G13 J13 ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 11 GL9714 PCI ExpressTM PIPE x4 PHY A14 TXNA C14 TXDA1 E14 TXDA5 G14 RXSTSA1 J14 VDD12 A15 VDDTXA C15 VSSGR E15 TXDKA G15 RXDA1 J15 VSS A16 RXNA C16 TXDA6 E16 TXDA2 G16 RXDA2 J16 RXDA6 A17 VDDRXA C17 TXDA7 E17 RXDKA G17 RXDA4 J17 VDD18 B1 REFCLKN D1 OSC25MI F1 VSS H1 TXDD4 K1 VDD25 B2 TXPD D2 VDD25 F2 RXSTSD1 H2 TXDD6 K2 TXDD0 B3 VSSTXD D3 RXDD3 F3 RXDD2 H3 TXDD7 K3 TXDD1 B4 RXPD D4 VSS F4 RXDD6 H4 RXSTSD0 K4 VDD12 B5 VSSRXD D5 VSS F5 H5 K5 B6 TXPC D6 NC F6 H6 K6 B7 VSSTXC D7 VDD18 F7 H7 VSS K7 VSS B8 RXPC D8 RTERM F8 H8 VSS K8 VSS B9 VSSRXC D9 VSSPLL F9 H9 VSS K9 VSS B10 TXPB D10 NC F10 H10 VSS K10 VSS B11 VSSTXB D11 NC F11 H11 VSS K11 VSS B12 RXPB D12 NC F12 H12 K12 B13 VSSRXB D13 TXDA0 F13 H13 K13 B14 TXPA D14 TXDA3 F14 RXSTSA0 H14 RXDA5 K14 TXDB2 B15 VSSTXA D15 TXDA4 F15 TXCMPA H15 RXDA3 K15 VDD25 B16 RXPA D16 VDD25 F16 RXDA0 H16 RXDA7 K16 TXDKB B17 VSSRXA D17 RXSTSA2 F17 VDD25 H17 VDD18 K17 NC Pin# Pin Name Pin# Pin Name Pin# Pin Name L1 VSS N1 RXDC5 R1 RXDC3 L2 VSS N2 VSS R2 RXSTSC1 U2 TXDC4 L3 TXDKD N3 RXDC6 R3 TXCMPC U3 VSS L4 VDD18 N4 RXDC0 R4 TXDC7 U4 TXDC0 Pin Pin Name # U1 VSS L5 N5 R5 TXDC5 U5 PHYSTS L6 N6 R6 TXDC1 U6 RXVLDD U7 RXVLDC L7 VSS N7 R7 VSS L8 VSS N8 R8 RXPLRD L9 VSS N9 R9 OPMODE0 L10 VSS N10 R10 SCC L11 VSS N11 R11 TXDET/LPBK U11 TESTC L12 N12 R12 TXIDLEB RST_N L13 N13 R13 VDD25 L14 TXCMPB N14 RXDB3 R14 TXIDLEA L15 TXDB6 N15 RXDKB R15 RXDB4 ©2004-2007 Genesys Logic Inc. - All rights reserved. U8 TXIDLEC U9 VDD25 U10 OPMODE1 U12 U13 RXPLRB U14 VSS U15 RXPLRA Page 12 GL9714 PCI ExpressTM PIPE x4 PHY L16 TXDB1 N16 TXDB7 R16 RXDB0 U16 RXDB6 L17 TXDB0 N17 TXDB5 R17 VDD25 U17 VDD25 M1 VSS P1 VDD25 T1 RXDKC M2 RXDC7 P2 RXDC1 T2 VDD25 M3 VDD18 P3 RXDC2 T3 TXDC6 M4 RXDC4 P4 RXSTSC2 T4 TXDC2 M5 P5 RXSTSC0 T5 VDD25 M6 P6 TXDC3 T6 VDD18 M7 P7 TXDKC T7 TXIDLED M8 P8 RXIDLED T8 RXIDLEC M9 P9 VSS T9 RXPLRC M10 P10 PD1 T10 TESTD M11 P11 RXVLDB T11 PD0 M12 P12 RXVLDA T12 RXIDLEB M13 P13 RXDB7 T13 RXIDLEA M14 RXSTSB1 P14 RXDB5 T14 PCLK M15 TXDB4 P15 RXDB1 T15 VSS M16 TXDB3 P16 VSS T16 RXDB2 M17 VSS P17 RXSTSB0 T17 RXSTSB2 Blank Table 3.3 - Alphabetic Pin List Pin Name Pin# Pin Name Pin# Pin Name Pin# Pin Name Pin# Pin Name Pin# NC C3 RXDD0 G4 TXCMPA F15 TXNC A6 VSS H7 NC C5 RXDD1 E2 TXCMPB L14 TXND A2 VSS H8 NC C6 RXDD2 F3 TXCMPC R3 TXPA B14 VSS H9 NC C9 RXDD3 D3 TXCMPD G1 TXPB B10 VSS H10 NC C11 RXDD4 E3 TXDA0 D13 TXPC B6 VSS H11 NC C13 RXDD5 E4 TXDA1 C14 TXPD B2 VSS J2 NC D6 RXDD6 F4 TXDA2 E16 VDD12 J14 VSS J7 NC D10 RXDD7 C2 TXDA3 D14 VDD12 K4 VSS J8 NC D11 RXDKA E17 TXDA4 D15 VDD18 C4 VSS J9 NC D12 RXDKB N15 TXDA5 E14 VDD18 C10 VSS J10 NC K17 RXDKC T1 TXDA6 C16 VDD18 C12 VSS J11 OPMODE0 R9 RXDKD E1 TXDA7 C17 VDD18 D7 VSS J15 OPMODE1 U10 RXIDLEA T13 TXDB0 L17 VDD18 H17 VSS K7 OSC25MO C1 RXIDLEB T12 TXDB1 L16 VDD18 J17 VSS K8 OSC25MI D1 RXIDLEC T8 TXDB2 K14 VDD18 L4 VSS K9 PCLK T14 RXIDLED P8 TXDB3 M16 VDD18 M3 VSS K10 ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 13 GL9714 PCI ExpressTM PIPE x4 PHY PD0 T11 RXNA A16 TXDB4 M15 VDD18 T6 VSS K11 PD1 P10 RXNB A12 TXDB5 N17 VDD25 D2 VSS L1 PHYSTS U5 RXNC A8 TXDB6 L15 VDD25 D16 VSS L2 REFCLKN B1 RXND A4 TXDB7 N16 VDD25 F17 VSS L7 REFCLKP A1 RXPA B16 TXDC0 U4 VDD25 G2 VSS L8 RST_N U12 RXPB B12 TXDC1 R6 VDD25 K1 VSS L9 RTERM D8 RXPC B8 TXDC2 T4 VDD25 K15 VSS L10 RXDA0 F16 RXPD B4 TXDC3 P6 VDD25 P1 VSS L11 RXDA1 G15 RXPLRA U15 TXDC4 U2 VDD25 R13 VSS M1 RXDA2 G16 RXPLRB U13 TXDC5 R5 VDD25 R17 VSS M17 RXDA3 H15 RXPLRC T9 TXDC6 T3 VDD25 T2 VSS N2 RXDA4 G17 RXPLRD R8 TXDC7 R4 VDD25 T5 VSS P9 RXDA5 H14 RXSTSA0 F14 TXDD0 K2 VDD25 U9 VSS P16 RXDA6 J16 RXSTSA1 G14 TXDD1 K3 VDD25 U17 VSS R7 RXDA7 H16 RXSTSA2 D17 TXDD2 J1 VDDPLL C8 VSS T15 RXDB0 R16 RXSTSB0 P17 TXDD3 J4 VDDRXA A17 VSS U1 RXDB1 P15 RXSTSB1 M14 TXDD4 H1 VDDRXB A13 VSS U3 RXDB2 T16 RXSTSB2 T17 TXDD5 J3 VDDRXC A9 VSS U14 RXDB3 N14 RXSTSC0 P5 TXDD6 H2 VDDRXD A5 VSSGR C15 RXDB4 R15 RXSTSC1 R2 TXDD7 H3 VDDTXA A15 VSSPLL D9 RXDB5 P14 RXSTSC2 P4 TXDET/LPBK R11 VDDTXB A11 VSSRXA B17 RXDB6 U16 RXSTSD0 H4 TXDKA E15 VDDTXC A7 VSSRXB B13 RXDB7 P13 RXSTSD1 F2 TXDKB K16 VDDTXD A3 VSSRXC B9 RXDC0 N4 RXSTSD2 G3 TXDKC P7 VSS D4 VSSRXD B5 RXDC1 P2 RXVLDA P12 TXDKD L3 VSS D5 VSSTXA B15 RXDC2 P3 RXVLDB P11 TXIDLEA R14 VSS F1 VSSTXB B11 RXDC3 R1 RXVLDC U7 TXIDLEB R12 VSS G7 VSSTXC B7 RXDC4 M4 RXVLDD U6 TXIDLEC U8 VSS G8 VSSTXC C7 RXDC5 N1 SCC R10 TXIDLED T7 VSS G9 VSSTXD B3 RXDC6 N3 TESTC U11 TXNA A14 VSS G10 RXDC7 M2 TESTD T10 TXNB A10 VSS G11 ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 14 GL9714 PCI ExpressTM PIPE x4 PHY 3.4 Pin Descriptions Table 3.4 - Pin Descriptions PIPE Interface Pin Name I/O Standard Pin# Type Description RST_N LVCMOS2 U12 I PCLK SSTL2_I T14 O RXSTSA[2:0] RXSTSB[2:0] RXSTSC[2:0] RXSTSD[2:0] SSTL2_I D17, G14, F14 T17, M14, P17 P4, R2, P5 G3, F2, H4 O RXIDLEA~D LVCMOS2 T13, T12, T8, P8 O PHYSTS SSTL2_I U5 O RXVLDA~D LVCMOS2 P12, P11, U7, U6 O TXCMPA~D SSTL2_I F15, L14, R3, G1 I Global reset Parallel interface clock All data movement across the parallel interface is synchronous to this clock. 1. For 8-bit mode: PCLK operates at 250 MHz and is applied to synchronize all TXDx, RXDx data bus and all commands. 2. For 16-bit mode: PCLK operates at 125 MHz and is applied to synchronize all TXDx, RXDx data bus and all commands. 3. For 10-bit mode(TBC): PCLK operates at 250 MHz and is applied to synchronize the TXDx data bus and all commands. 1. For 8-bit and 16-bit modes: Encodes receiver status and error codes for the received data stream and receiver detection 000 Received data OK 001 1 SKP added 010 1 SKP removed 011 Receiver detected 100 8B/10B decode error 101 Elastic Buffer overflow 110 Elastic Buffer underflow 111 Receiver disparity error 2. For 10-bit modes: RXSTSx[2]: RBCx, synchronize the RXDx data bus RXSTSx[1]: RXPRSNTx, report the result of receiver detection RXSTSx[0]: RXDx9, bit 9 of RXDx data bus Indicates receiver detection of an electrical idle This is an asynchronous signal. Used to communicate completion of several PHY functions including power state transitions and receiver detection Indicates symbol lock and valid data on RXDx and RXDKx Sets the running disparity to negative TXIDLEA~D LVCMOS2 R14, R12, U8, T7 I Forces Tx output to electrical idle RXDKA~D SSTL2_I E17, N15, T1, E1 O K-code indication for the received symbols SSTL2_I H16, J16, H14, G17, H15, G16, G15, F16 O Parallel data output bus RXDA[7:0] ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 15 GL9714 PCI ExpressTM PIPE x4 PHY P13, U16, P14, R15, N14, T16, P15, R16 M2, N3, N1, M4, R1, P3, P2, N4 C2, F4, E4, E3, D3, F3, E2, G4 RXDB[7:0] RXDC[7:0] RXDD[7:0] TXDKA~D SSTL2_I E15, K16, P7, L3 I K-code indication for the transmitted symbols TXDA[7:0] TXDB[7:0] TXDC[7:0] TXDD[7:0] SSTL2_I C17, C16, E14, D15, D14, E16, C14, D13 N16, L15, N17, M15, M16, K14, L16, L17 R4, T3, R5, U2, P6, T4, R6, U4 H3, H2, J3, H1, J4, J1, K3, K2 I Parallel data input bus TXDET/LPBK LVCMOS2 R11 I PD[1:0] LVCMOS2 P10, T11 I Receiver detection/Loopback Sets the power states 00 P0, normal operation 01 P0s, low recovery time latency, power saving state 10 P1, longer recovery time(64us max) latency, lower power state RXPLRA~D LVCMOS2 U15, U13, T9, R8 I 11 P2, lowest power state Inverts the polarity on the RXP/RXN Power and Ground Signals Pin Name VDD25 VDD18 VDD12 VSS VDDPLL VSSPLL VDDRXA~D VSSRXA~D VDDTXA~D VSSTXA~D VSSGR Pin# Type D2, D16, F17, G2, K1, K15, P1, R13, R17, T2, T5, U9, U17 C4, C10, C12, D7, H17, J17, L4, M3, T6 J14, K4 D4, D5, F1, G7, G8, G9, G10, G11, H7, H8, H9, H10, H11, J2, J7, J8, J9, J10, J11, J15, K7, K8, K9, K10, K11, L1, L2, L7, L8, L9, L10, L11, M1, M17, N2, P9, P16, R7, T15, U1, U3, U14 C8 D9 A17, A13, A9, A5 B17, B13, B9, B5 A15, A11, A7, A3 B15, B11, B7, C7, B3 C15 Description P 2.5V Power Supplies for general I/O P 1.8V Power Supplies for core and bias voltage P 1.25V Reference Voltage for high speed I/O P Digital ground P 1.8V Power Supplies for internal PLL P Ground for internal PLL P 1.8V Power Supplies for receiver part P 1.8V Power Supplies for transceiver part P Ground for the guard ring of the SerDes block Serial Signals Pin Name Pin# Type RXNA~D A16, A12, A8, A4 I Received serial input, complement RXPA~D B16, B12, B8, B4 I Received serial input, true RTERM D8 I Connects an external 5.1KΩ resistor to ground ©2004-2007 Genesys Logic Inc. - All rights reserved. Description Page 16 GL9714 PCI ExpressTM PIPE x4 PHY for calibrating the on-chip termination resistors TXNA~D A14, A10, A6, A2 O Transmitted serial output, complement TXPA~D B14, B10, B6, B2 O Transmitted serial output, true Other Signals Pin Name I/O Standard Pin# Type REFCLKP Analogue A1 I Reference clock signal REFCLKN Analogue B1 I Reference clock signal OSC25MO Crystal C1 O OSC25MI Crystal/ Oscillator D1 I TESTC/SMC LVCMOS2 U11 I TESTD/SMD LVCMOS2 T10 SCC LVCMOS2 NC - Connect to 25MHz crystal when using crystal as the reference clock source Connect to 25MHz crystal/oscillator when using crystal/oscillator as the reference clock source Test clock/SMBus clock I/O Test data/SMBus data Configures clock input source When SCC=1, the chip clock sources from a pair of differential signals, REFCLKP and REFCLKN, I with a nominal frequency of 100 MHz. When SCC=0, the chip clock sources from a crystal at 25MHz. Operational Mode of the GL9714 00 4 lanes, 8 bit mode I 01 2 lanes, 16 bit mode 10 4 lanes, 10 bit mode 11 Internal use only R10 OPMODE[1:0] LVCMOS2 Description U10, R9 C3, C5, C6, C9, C11, C13, D6, D10, D11, D12, K17 - No connection Table 3.5 - Parameter of Buffer I/O Buffer type VIH VIL VOH VOL (Input High Voltage, (Input Low Voltage, (Output High Voltage, (Output Low Voltage, V) V) V) V) Min Norm Max Min Norm Max Min Norm Max Min Norm Max LVCMOS2 1.7 - - - - 0.7 2.4 - - - - 0.4 SSTL2 1.57 - - - - 0.93 1.76 - - - - 0.74 ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 17 GL9714 PCI ExpressTM PIPE x4 PHY CHAPTER 4 REGISTERS There are some registers built-in the GL9714 for test purpose. These registers can be accessed through a serial bus interface using pin TESTC and TESTD. Registers at Offset 05h ~ 0Bh are for internal test only. Please be careful to leave them as default values. 4.1 Registers Base Address Table 4.1 - Base Address for Registers Mnemonic Offset REVID 00h Revision ID and Auto-calibration Result Register XCVROPT 01h Transceiver Option Register 8’hE9 LPBKTEST 02h BIST and Beacon/Test Data Pattern Register, Part 1 8’h00 BCNPAT2 03h Beacon/Test Data Pattern Register, Part 2 8’h03 BCNPAT3 04h Beacon/Test Data Pattern Register, Part 3 8’hFF - 05h For internal test only - - 06h For internal test only - - 07h For internal test only - - 08h For internal test only - - 09h For internal test only - - 0Ah For internal test only - - 0Bh For internal test only - BT 0Ch Buffer Test Register 8’h00 SLCDT 0Dh Serial Loopback and Comma Detect Test Register 8’h00 Notation: R/W R/O W/O R/W1C R/W/C Description Default 8’bxxxx0xxx Read / Write Read Only Write Only Read / Write “1” to Clear Read / Write and hardware automatic Clear ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 18 GL9714 PCI ExpressTM PIPE x4 PHY 4.2 Registers Descriptions Offset 00h – REVID …………………………………………….………… Default value = 8’bxxxx0xxx REV3 REV2 REV1 REV0 BY1 RCAL0 RCAL1 RCAL2 R R R R R R R R 7-4 REV[3:0] 3 BY1 2-0 RCAL[0:2] Chip revision code x1 package Calibration result of on-chip termination resistors Offset 01h – XCVROPT ……………………………………………..…………. Default value = 8’hE9 SW1 SW0 DEM1 DEM0 BW0 BW1 RDEF FEVAL R/W R/W R/W R/W R/W R/W R/W R/W 7-6 SW[1:0] 5-4 DEM[1:0] 3-2 BW[0:1] 1 RDEF 0 FEVAL Swing control of transmitter output Output Swing (Differential, peak-to-peak) 00 0.6V 01 0.8V 10 1.0V 11 1.2V De-emphasis control of transmitter output Amount of De-emphasis 00 No de-emphasis 01 -1.6dB 10 -3.5dB 11 -6.0dB Bandwidth control of clock recovery circuit Relative Bandwidth 00 1 01 2 10 4 11 Reserved Disable calibration of on-chip termination resistors and leave the resistors to their default value Force calibration of on-chip termination resistors When RDEF=0, writing a one to this bit will make the resistors re-calibrated. This bit is auto-cleared and always read as zero. ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 19 GL9714 PCI ExpressTM PIPE x4 PHY Offset 02h – LPBKTEST …………………………………………..…………. Default value = 8’h00 BIST0 BIST1 BIST2 -- BCN19 BCN18 BCN17 BCN16 R/W R/W R/W -- R/W R/W R/W R/W 7-5 BIST[0:2] Select of built-in test pattern Bit Pattern 00x BIST disabled 100 0000000000 0000000000 010 1111111111 1111111111 110 0101010101 0101010101 101 0011111010 1010101010 1100000101 0101010101 011 0011111010 10100*01010 1100000101 01011*10101 111 PRBS pattern It should be noted that the expected pattern while BIST[0:2]=011 is the same as BIST[0:2]=101. But when coming out of the transmitter, the two bits with “*” in BIST[0:2]=011 are different from BIST[0:2]=101. As a result, even when there is no bit error, there will be bit errors intentionally introduced to verify the BIST circuit is functional. Data pattern for beacon and TXTEST 4 RESERVED 3-0 BCN[19:16] Offset 03h – BCNPAT2 ………………………………………………….……. Default value = 8’h03 BCN15 BCN14 BCN13 BCN12 BCN11 BCN10 BCN9 BCN8 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 BCN[15:8] Data pattern for beacon and TXTEST Offset 04h – BCNPAT3 ………………………………………………….……. Default value = 8’hFF BCN7 BCN6 BCN5 BCN4 BCN3 BCN2 BCN1 BCN0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 BCN[7:0] Data pattern for beacon and TXTEST Offset 0Ch – BT ……………...…………………………………………...……. Default value = 8’h00 -- -- DDR -- TXTEST -- SKPDEL SKPADD -- -- R/W -- R/W -- R/W R/W 7-6 RESERVED 5 DDR 3 TXTEST 1 SKPDEL 0 SKPADD Enable DDR at PIPE interface and make PCLK = 125MHz @ 8/10-bit mode Enable transmitter test with data pattern BCN[19:0], which are programmed in REG02h, 03h and 04h Enable SKP deleting test of SKP ordered sets Enable SKP adding test of SKP ordered sets ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 20 GL9714 PCI ExpressTM PIPE x4 PHY Offset 0Dh – SLCDT ………...…………………………………………...……. Default value = 8’h00 SLPBKA SLPBKB SLPBKC SLPBKD FENCDA FENCDB FENCDC FENCDD R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 SLPBKA SLPBKB SLPBKC SLPBKD FENCDA FENCDB FENCDC FENCDD Enable serial loopback of lane A Enable serial loopback of lane B Enable serial loopback of lane C Enable serial loopback of lane D Force comma detect of lane A Force comma detect of lane B Force comma detect of lane C Force comma detect of lane D Offset 14h – SECNTA ………...…………………………………………...……. Default value = 8’h00 SECNTA7 SECNTA6 SECNTA5 SECNTA4 SECNTA3 SECNTA2 SECNTA1 SECNTA0 R R R R R R R R 7-0 SECNTA[7:0] Error count of SLPBKA. Offset 15h – SECNTB ………...…………………………………………...……. Default value = 8’h00 SECNTB7 SECNTB6 SECNTB5 SECNTB4 SECNTB3 SECNTB2 SECNTB1 SECNTB0 R R R R R R R R 7-0 SECNTB[7:0] Error count of SLPBKB. Offset 16h – SECNTC ………...…………………………………………...……. Default value = 8’h00 SECNTC7 SECNTC6 SECNTC5 SECNTC4 SECNTC3 SECNTC2 SECNTC1 SECNTC0 R R R R R R R R 7-0 SECNTC[7:0] Error count of SLPBKC. Offset 17h – SECNTD ………...…………………………………………...……. Default value = 8’h00 SECNTD7 SECNTD6 SECNTD5 SECNTD4 SECNTD3 SECNTD2 SECNTD1 SECNTD0 R 7-0 R SECNTD[7:0] R R R R R R Error count of SLPBKD. PS: Please write “0” to the unused bits when programming a register. ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 21 GL9714 PCI ExpressTM PIPE x4 PHY 4.3 SMBus Protocol GL9714 registers are programmed by System Management Bus (SMBus). Fig. 4.1 shows the SMBus topology. The VDD power is 2.5V +/- 10% and the pull up resistor is 1KΩ. Both SMBCLK and SMBDAT lines are bi-directional, connected to 2.5V supply voltage through a pull-up resistor. The operating frequency is 10~100KHz and the SMBus address of GL9714 is 7’h2C. Figure 4.1 – SMBus Topology of GL9714 SMBus uses fixed voltage levels to define the logic “ZERO” and logic “ONE” on the bus respectively. The data on SMBDAT must be stable during the “HIGH” period of the clock. Data can change state only when SMBCLK is low. Fig. 4.2 illustrates the relationships. Figure 4.2 – Data Validity ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 22 GL9714 PCI ExpressTM PIPE x4 PHY Two unique bus situations define a message START and STOP condition. 1. A HIGH to Low transition of the SMBDAT line while SMBCLK is HIGH indicates a message START condition. 2. A LOW to HIGH transition of the SMBDAT line while SMBCLK is HIGH defines a message STOP condition. Figure 4.3 – START and STOP Condition Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an acknowledge bit. Bytes are transferred with the most significant bit (MSB) first. Fig. 4.4 illustrates the positioning of acknowledge (ACK) and not acknowledge (NACK) pulses relative to other data. Figure 4.4 – ACK and NACK Signaling of SMBus ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 23 GL9714 PCI ExpressTM PIPE x4 PHY Below is a key to the protocol diagrams. S Sr Rd Wr Start Condition Repeated Start Condition Read (bit value of 1) Write (bit value of 0) x Shown under a field indicates that that field is required to have the value of ‘x’ Acknowledge (this bit position may be ‘0’ for an ACK or ‘1’ for a NACK) ` A P Stop Condition Master-to-GL9714 GL9714-to-Master Figure 4.5 – SMBus Packet Protocol Diagram Element Key The first byte of a Write Byte access is the command code. The next one byte is the data to be written. In this example the master asserts GL9714’s address followed by the write bit. GL9714 acknowledges and the master delivers the command code. GL9714 again acknowledges before the master sends the data byte. GL9714 acknowledges the data byte, and the entire transaction is finished with a STOP condition. Figure 4.6 – Write Byte Protocol Reading data is slightly more complicated than writing data. First the host must write a command to GL9714. Then it must follow that command with a repeated START condition to denote a read from GL9714’s address. GL9714 then returns one byte of data. Note that there is no STOP condition before the repeated START condition, and that a NACK signified the end of the read transfer. Figure 4.7 – Read Byte Protocol ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 24 GL9714 PCI ExpressTM PIPE x4 PHY GL9714 requires a minimum time (16us) to reach the steady state after power on. So the master must start programming at least 16us later after power on. Figure 4.8 – The Minimum Wait Time from Power on to Programming Registers ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 25 GL9714 PCI ExpressTM PIPE x4 PHY CHAPTER 5 BLOCK DIAGRAM 5.1 Simplified Diagram PHY/MAC Interface PCS Quad SerDes Operational TXPA TXNA RXPA RXNA TXPC TXNC RXPC RXNC TXPB TXNB RXPB RXNB TXPD TXND RXPD RXND Registers Configuration Test Bus Controller PLL REFCLKP REFCLKN Figure 5.1 - Simplified Diagram ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 26 GL9714 PCI ExpressTM PIPE x4 PHY 5.2 Transmitter Data Path Per Lane Data x16 or x8 PCLK Optional 16, 8-bit x8 TXCMP 8b 10b Encoding 250 MHz TXDK0,TXDK1 From PLL x10 Loopback path from receiver Parallel to Serial Conversion 2.5 GHz TXIDLE Transmitter Differential Driver TXDET/LPBK TXP TXN Figure 5.2 - Transmitter Data Path per Lane ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 27 GL9714 PCI ExpressTM PIPE x4 PHY 5.3 Receiver Data Path Per Lane RXP RXN Differential Recieiver RXIDLE 2.5 GHz Clock Recovery Circuit Data Recovery Circuit (DRC) RXPLR Serial to Paralle K28.5 Detection RXVLD x10 Recovered Symbol Clock Elastic Buffer Buffer Overflow/Underflow SKP Added/Removed Decode Error x10 250 MHz Receiver Status RXSTS Disparity Error 8b 10b Decoder RXDK x8 Loopback path to transmitter Optional 8, 16-bit PCL Data x16 or x8 Figure 5.3 - Receiver Data Path per Lane ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 28 GL9714 PCI ExpressTM PIPE x4 PHY CHAPTER 6 FUNCTION DESCRIPTION 6.1 Clock and Reset The clock source of the GL9714 comes externally from either the 100 MHz differential clock pair or the 25MHz crystal, which is selectable by pin SCC. The GL9714 uses the clock source with its PLL to generate the 2.5 GHz bit rate for transmitting and receiving. The GL9714 also drives a clock output for the synchronization of MAC interface. Since the MAC interface can be configured to 8-bit and 16-bit mode, the clock, PCLK, runs at 250 MHz for 8-bit mode and 125 MHz for 16-bit mode. The MAC should use the rising edge of the clock to send and receive parallel data. To initialize the GL9714, the MAC should assert the reset of the GL9714 to low. While the reset is asserted, the MAC should also make TXDET/LPBK deasserted, TXIDLEx asserted, TXCMPx deasserted, RXPLRx deasserted and PD[1:0] = P1. When the GL9714 senses it reset asserted, it will drive its PHYSTS high immediately. After the reset deasserted, the GL9714 requires typically 16.7us for internal PLL stable and then transitions its PHYSTS to low. When MAC deasserts the reset, it should monitor the state of PHYSTS to make sure the GL9714 is ready for normal operation. 6.2 Receiver Detection The receiver detection can only be performed while the GL9714 is in P1 state. To instruct the GL9714 to enter a receiver detection sequence, the MAC asserts TXDET/LPBK and hold it asserted until the GL9714 asserts PHYSTS for response. While finishing the receiver detection, the GL9714 will assert PHYSTS and present a appropriate value to RXSTSx[2:0] to signal a detection completion. When the MAC detects PHYSTS asserted, it knows the detection result from RXSTSx[2:0] and can deassert TXDET/LPBK. 6.3 Beacon Transmitting and Detection Beacon transmitting is required for the GL9714 in P2 state to wake up the receiver in the other side of the link. When the GL9714 is in P2 state, the MAC can deassert TXIDLEx to instruct the GL9714 to repeatedly transmit a beacon. For the beacon receiving side, if the GL9714 receives a beacon, it will transition RXIDLEx to low to indicate an exit from electrical idle. When the GL9714 is in P2 state and MAC senses the RXIDLEx transitioned from high to low, it knows a beacon has been detected. 6.4 Receiver Status Report Add and Remove a SKP The GL9714 implements an elastic buffer to compensate the clock rate difference between the recovery clock and its transmit clock. While receiving a SKP ordered-set, compliant to PCI Express Base specification REV. 1.0a, the GL9714 can insert or remove one SKP symbol in the SKP ordered-set to avoid the buffer overrun or underrun. Whenever adding or removing a SKP symbol, the GL9714 will signal PHYSTS and corresponding RXSTS[2:0] to MAC. SKP Ordered-Set Received RXSTS Code Add a SKP Remove a SKP 001b 010b Detected Result RXSTS code Receiver not present Receiver present 000b 011b Receiver Detected ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 29 GL9714 PCI ExpressTM PIPE x4 PHY 8B/10B Decode Error When the GL9714 decodes the received 10-bit symbol and detects an error code which does not correspond to any valid data, it will replace the code with an EDB symbol, assert PHYSTS and encode RXSTSx[2:0] with the values of decode error status, 3’b100. Elastic Buffer Overrun and Underrun When the overrun or underrun of the elastic buffer occurs, the GL9714 will assert PHYSTS and encode RXSTSx[2:0] with the values of decode error status. Elastic Buffer RXSTS Code Overrun Underrun 101b 110b In the case of elastic buffer overrun, the GL9714 drops the symbol. For the elastic buffer underrun, the GL9714 inserts the EDB symbol. The PHYSTS and RXSTSx[2:0] are presented on the MAC interface during the clock cycle where GL9714 drops or inserts the symbol. Disparity Errors To report a disparity error detected, the GL9714 asserts PHYSTS and encodes RXSTSx[2:0] with the values of decode error status, 3’b111. 6.5 Loopback The GL9714 supports a Loopback mode to re-transmit its received data. When the MAC sets the GL9714 in P0 state and asserts TXDET/LPBK, the GL9714 enters a Loopback. In Loopback, the GL9714 transmits data from it received data instead of MAC interface. Meanwhile, it presents the received data on the MAC interface as normal operation. When set into Loopback mode and acting as a Loopback slave according to the PCI Express Base Specification Rev. 1.0a, the GL9714 received data from the Loopback master. If the master intends to end the Loopback, it sends an electrical idle ordered-set to the GL9714. When the MAC detects the electrical idle ordered-set, it de-asserts TXDET/LPBK and asserts TXIDLE to instruct the GL9714 to stop Loopback. The MAC should take care the GL9714 has retransmit at least three bytes of the electrical idle before it makes the GL9714’s transmitter into electrical idle. 6.6 Polarity Inversion The GL9714 supports lane polarity inversion. While pin RXPLRx asserted, the GL9714 inverts its received data on the MAC interface. 6.7 Setting Negative Disparity To set the running disparity to negative, the MAC asserts TXCMPx for one PCLK cycle that matches with the data that is to be transmitted where running disparity is negative. ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 30 GL9714 PCI ExpressTM PIPE x4 PHY 6.8 Behavior Summary PD[1:0] P0 P0S P1 P2 TXDET/LPBK TXIDLEx Behavior 0 0 GL9714 is transmitting data from MAC interface normally. 0 1 GL9714 is not transmitting and is in electrical idle. 1 0 GL9714 enters Loopback mode. 1 1 Illegal X 0 Illegal X 1 GL9714 is not transmitting and is in electrical idle. X 0 Illegal 0 1 GL9714 is idle. 1 1 GL9714 performs a receiver detection. X 0 GL9714 transmits a beacon. X 1 GL9714 is idle. 6.9 Power Saving Support The GL9714 supports four power states including P0, P0s, P1 and P2 and can be controlled to perform Active State Power Management on a PCI Express link. P0 is the normal operational state where data and control packets can be transmitted and received. When directed from P0 to a lower power state, the GL9714 can immediately take appropriate power saving actions. The power saving scheme of the GL9714 for various power down states is listed in the table below. PD[1:0] Transmitter Receiver PLL PCLK Output P0 On High-impedance Electrical Idle On On On On On On Off but exit from Electrical Idle is detectable On On Off but exit from Electrical Idle is detectable Off Off P0s P1 P2 High-impedance Electrical Idle High-impedance Electrical Idle (Capable of transmitting a Beacon) ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 31 GL9714 PCI ExpressTM PIPE x4 PHY 6.10 Operation Mode and Multi-Functional Pins There are four modes for GL9714 operation which is selected by pin OPMODE[1:0]. Mode [1] [0] 1 2 3 4 0 0 1 1 0 1 0 1 Description 4 lanes, 8 bit mode 2 lanes, 16 bit mode 4 lanes, 10 bit mode For scan test only Mode 1: The GL9714 is configured into an x4 lane, 8-bit parallel bus and acts as a 4-lane PCI Express PHY. The parallel bus is synchronous with PCLK at 250 MHz. By transitioning both TXCMPx and TXIDLEx to high for individual lane, the GL9714 in this mode is able to behave as an x1 or x2 PHY. Mode 2: The GL9714 acts as a 2-lane PHY with a 16-bit parallel interface at 125 MHz. In this mode, only lane B and lane C are activated. Again, by disabling either lane using TXCMPx and TXIDLEx, the GL9714 can be configured into an x1 PHY with16-bit parallel bus. Mode 3: The GL9714 is configured as a quad SerDes with 10-bit parallel bus. Mode 4: For scan test only Table 6.1 - Pin Functions Pin Number Mode 1 Mode 2 Mode 3 T14 C17 C16 E14 D15 D14 E16 C14 D13 N16 L15 N17 M15 M16 K14 L16 L17 R4 T3 R5 U2 P6 T4 R6 U4 H3 PCLK(O) TXDA7(I) TXDA6(I) TXDA5(I) TXDA4(I) TXDA3(I) TXDA2(I) TXDA1(I) TXDA0(I) TXDB7(I) TXDB6(I) TXDB5(I) TXDB4(I) TXDB3(I) TXDB2(I) TXDB1(I) TXDB0(I) TXDC7(I) TXDC6(I) TXDC5(I) TXDC4(I) TXDC3(I) TXDC2(I) TXDC1(I) TXDC0(I) TXDD7(I) PCLK(O) TXDB15(I) TXDB14(I) TXDB13(I) TXDB12(I) TXDB11(I) TXDB10(I) TXDB9(I) TXDB8(I) TXDB7(I) TXDB6(I) TXDB5(I) TXDB4(I) TXDB3(I) TXDB2(I) TXDB1(I) TXDB0(I) TXDC15(I) TXDC14(I) TXDC13(I) TXDC12(I) TXDC11(I) TXDC10(I) TXDC9(I) TXDC8(I) TXDC7(I) TBC(O) TDA7(I) TDA6(I) TDA5(I) TDA4(I) TDA3(I) TDA2(I) TDA1(I) TDA0(I) TDB7(I) TDB6(I) TDB5(I) TDB4(I) TDB3(I) TDB2(I) TDB1(I) TDB0(I) TDC7(I) TDC6(I) TDC5(I) TDC4(I) TDC3(I) TDC2(I) TDC1(I) TDC0(I) TDD7(I) ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 32 GL9714 PCI ExpressTM PIPE x4 PHY H2 J3 H1 J4 J1 K3 K2 E15 K16 P7 L3 R14 R12 U8 T7 F15 L14 R3 G1 U15 U13 T9 R8 H16 J16 H14 G17 H15 G16 G15 F16 P13 U16 P14 R15 N14 T16 P15 R16 M2 N3 N1 M4 R1 P3 TXDD6(I) TXDD5(I) TXDD4(I) TXDD3(I) TXDD2(I) TXDD1(I) TXDD0(I) TXDKA(I) TXDKB(I) TXDKC(I) TXDKD(I) TXIDLEA(I) TXIDLEB(I) TXIDLEC(I) TXIDLED(I) TXCMPA(I) TXCMPB(I) TXCMPC(I) TXCMPD(I) RXPLRA(I) RXPLRB(I) RXPLRC(I) RXPLRD(I) RXDA7(O) RXDA6(O) RXDA5(O) RXDA4(O) RXDA3(O) RXDA2(O) RXDA1(O) RXDA0(O) RXDB7(O) RXDB6(O) RXDB5(O) RXDB4(O) RXDB3(O) RXDB2(O) RXDB1(O) RXDB0(O) RXDC7(O) RXDC6(O) RXDC5(O) RXDC4(O) RXDC3(O) RXDC2(O) ©2004-2007 Genesys Logic Inc. - All rights reserved. TXDC6(I) TXDC5(I) TXDC4(I) TXDC3(I) TXDC2(I) TXDC1(I) TXDC0(I) TXDKB1(I) TXDKB0(I) TXDKC1(I) TXDKC0(I) TXIDLEB(I) TXIDLEC(I) TXCMPB(I) TXCMPC(I) RXPLRB(I) RXPLRC(I) RXDB15(O) RXDB14(O) RXDB13(O) RXDB12(O) RXDB11(O) RXDB10(O) RXDB9(O) RXDB8(O) RXDB7(O) RXDB6(O) RXDB5(O) RXDB4(O) RXDB3(O) RXDB2(O) RXDB1(O) RXDB0(O) RXDC15(O) RXDC14(O) RXDC13(O) RXDC12(O) RXDC11(O) RXDC10(O) TDD6(I) TDD5(I) TDD4(I) TDD3(I) TDD2(I) TDD1(I) TDD0(I) TDA8(I) TDB8(I) TDC8(I) TDD8(I) TXIDLEA(I) TXIDLEB(I) TXIDLEC(I) TXIDLED(I) TDA9(I) TDB9(I) TDC9(I) TDD9(I) RXPLRA(I) RXPLRB(I) RXPLRC(I) RXPLRD(I) RDA7(O) RDA6(O) RDA5(O) RDA4(O) RDA3(O) RDA2(O) RDA1(O) RDA0(O) RDB7(O) RDB6(O) RDB5(O) RDB4(O) RDB3(O) RDB2(O) RDB1(O) RDB0(O) RDC7(O) RDC6(O) RDC5(O) RDC4(O) RDC3(O) RDC2(O) Page 33 GL9714 PCI ExpressTM PIPE x4 PHY P2 N4 C2 F4 E4 E3 D3 F3 E2 G4 E17 N15 T1 E1 P12 P11 U7 U6 D17 G14 F14 T17 M14 P17 P4 R2 P5 G3 F2 H4 U5 T13 T12 T8 P8 RXDC1(O) RXDC0(O) RXDD7(O) RXDD6(O) RXDD5(O) RXDD4(O) RXDD3(O) RXDD2(O) RXDD1(O) RXDD0(O) RXDKA(O) RXDKB(O) RXDKC(O) RXDKD(O) RXVLDA(O) RXVLDB(O) RXVLDC(O) RXVLDD(O) RXSTSA2(O) RXSTSA1(O) RXSTSA0(O) RXSTSB2(O) RXSTSB1(O) RXSTSB0(O) RXSTSC2(O) RXSTSC1(O) RXSTSC0(O) RXSTSD2(O) RXSTSD1(O) RXSTSD0(O) PHYSTS(O) RXIDLEA(O) RXIDLEB(O) RXIDLEC(O) RXIDLED(O) ©2004-2007 Genesys Logic Inc. - All rights reserved. RXDC9(O) RXDC8(O) RXDC7(O) RXDC6(O) RXDC5(O) RXDC4(O) RXDC3(O) RXDC2(O) RXDC1(O) RXDC0(O) RXDKB1(O) RXDKB0(O) RXDKC1(O) RXDKC0(O) RXVLDB(O) RXVLDC(O) RXSTSB2(O) RXSTSB1(O) RXSTSB0(O) RXSTSC2(O) RXSTSC1(O) RXSTSC0(O) PHYSTS(O) RXIDLEB(O) RXIDLEC(O) RDC1(O) RDC0(O) RDD7(O) RDD6(O) RDD5(O) RDD4(O) RDD3(O) RDD2(O) RDD1(O) RDD0(O) RDA8(O) RDB8(O) RDC8(O) RDD8(O) RXVLDA(O) RXVLDB(O) RXVLDC(O) RXVLDD(O) RBCA(O) RXPRSNTA(O) RDA9(O) RBCB(O) RXPRSNTB(O) RDB9(O) RBCC(O) RXPRSNTC(O) RDC9(O) RBCD(O) RXPRSNTD(O) RDD9(O) PHYSTS(O) RXIDLEA(O) RXIDLEB(O) RXIDLEC(O) RXIDLED(O) Page 34 GL9714 PCI ExpressTM PIPE x4 PHY CHAPTER 7 ELECTRICAL CHARACTERISTICS 7.1 DC Electrical Characteristics Table 7.1 - DC Electrical Characteristics Symbol Parameter Min Typ Max Unit VDD25 PHY Interface Voltage 2.375 2.5 2.625 V VDD18 Core Voltage 1.71 1.8 1.89 V 1.1875 1.25 1.3125 V Voltage for Transmitters 1.71 1.8 1.89 V Voltage for Receivers 1.71 1.8 1.89 V Voltage for PLL 1.71 1.8 1.89 V VDD12 VDDTXA VDDTXB VDDTXC VDDTXD VDDRXA VDDRXB VDDRXC VDDRXD VDDPLL Reference Voltage for PHY Interface 7.2 Transmit and Receive Latency Time Table 7.2 - Transmit and Receive Latency Time Symbol TTX-LAT TRX-LAT Parameter Transmit Latency, time for data moving from MAC interface (PCLK rising edge) to TX serial lines (the first bit of 10-bit symbol) Receive Latency, time for data moving from RX serial lines (the first bit of 10-bit symbol) to MAC interface (PCLK rising edge) Min Typ Max Unit 25 - 30 ns 48 - 54 ns 7.3 Transition Time of Power State Table 7.3 – Transition Time of Power State Symbol TP0S-P0 TP1-P0 TP2-P1 TP0-P0S TP0-P1 Parameter Time for PHY to return to P0, after having been in P0s. Time is measured when PD[1:0] are set to P0 until the PHY asserts PHYSTS Time for PHY to return to P0, after having been in P1. Time is measured when PD[1:0] are set to P0 until the PHY asserts PHYSTS Time for PHY to return to P0, after having been in P2. Time is measured when PD[1:0] are set to P0 until the PHY asserts PHYSTS Time for PHY to return to P0s, after having been in P0. Time is measured when PD[1:0] are set to P0 until the PHY asserts PHYSTS Time for PHY to return to P1, after having been ©2004-2007 Genesys Logic Inc. - All rights reserved. Min Typ Max Unit 52 - 74 ns 52 - 74 ns 16 - 17 µs 52 - 74 ns 52 - 74 ns Page 35 GL9714 PCI ExpressTM PIPE x4 PHY TP0-P2 in P0. Time is measured when PD[1:0] are set to P0 until the PHY asserts PHYSTS Time for PHY to return to P2, after having been in P0. Time is measured when PD[1:0] are set to P0 until the PHY asserts PHYSTS ©2004-2007 Genesys Logic Inc. - All rights reserved. 16 - 17 µs Page 36 GL9714 PCI ExpressTM PIPE x4 PHY 7.4 Power Consumption Power Consumption with 2-Lanes and 4-Lanes Operation Table 7.4 – Typical Power Consumption with 2-Lanes, 4-Lanes, and 1.2V Differential Peak to Peak Output Voltage Current at 2.5V (mA) 184 Current at Current at Current at Analogue Digital 1.8V Reference Voltage 1.8V (mA) (mA) 1.25V (mA) 285 128 0 Operation Power Condition State All on P0 PLL on 14 207 89 0 TX idle P0s RX on PLL on 14 174 48 0 TX idle P1 RX idle PLL off 9 146 10 0 TX idle P2 RX idle 107 161 81 0 All on P0 PLL on 17 117 65 0 TX idle P0s RX on PLL on 17 101 45 0 TX idle P1 RX idle PLL off 9 74 9 0 TX idle RX idle ©2004-2007 Genesys Logic Inc. - All rights reserved. P2 Power Operation Mode Consumption (mW) 8-bit @250MHz PCLK, 4-Lanes 8-bit @250MHz PCLK, 4-Lanes 8-bit @250MHz PCLK, 4-Lanes 8-bit @3.13MHz PCLK, 4-Lanes 16-bit @125MHz PCLK, 2-Lanes 16-bit @125MHz PCLK, 2-Lanes 16-bit @125MHz PCLK, 2-Lanes 16-bit @1.56MHz PCLK, 2-Lanes 1203.4 567.8 434.6 303.3 703.1 370.1 305.3 171.9 Page 37 GL9714 PCI ExpressTM PIPE x4 PHY Power Consumption with Single-Lane Operation Table 7.5 – Typical Power Consumption with Single-Lane and 1.2V Differential Peak to Peak Output Voltage Current at 2.5V (mA) 51 Current at Current at Current at Analogue Digital 1.8V Reference Voltage 1.8V (mA) (mA) 1.25V (mA) 90 65 0 Operation Power Condition State All on P0 PLL on 10 72 56 0 TX idle P0s RX on PLL on 10 65 45 0 TX idle P1 RX idle PLL off 6 37 7 0 TX idle P2 RX idle 59 90 57 0 All on P0 PLL on 12 71 49 0 TX idle P0s RX on PLL on 12 64 38 0 TX idle P1 RX idle PLL off 6 36 6 0 TX idle RX idle ©2004-2007 Genesys Logic Inc. - All rights reserved. P2 Power Operation Mode Consumption (mW) 8-bit @250MHz PCLK 8-bit @250MHz PCLK 8-bit @250MHz PCLK 8-bit @3.13MHz PCLK 16-bit @125MHz PCLK 16-bit @125MHz PCLK 16-bit @1.56MHz PCLK 16-bit @125MHz PCLK 406.5 255.4 223 94.2 412.1 246 213.6 90.6 Page 38 GL9714 PCI ExpressTM PIPE x4 PHY 7.5 Differential Transmitter and Receiver Serial Output Transmitter Serial Output Table 7.6 – Transmitter Serial Output Symbol Min Typ Max Unit 399.88 400 400.12 ps 0.8 - 1.2 V -3.0 -3.5 -4.0 dB 0.7 - - UI - - 0.15 UI 0.125 - - UI - - 20 mV 0 - 100 mV 0 - 25 mV 0 - 20 mV - - 600 mV 0 - 3.6 V - - 90 mA 50 - - UI - - 20 UI - - 20 UI RLTX-DIFF Minimum time spent in electrical idle Maximum time to transition to a valid electrical idle after sending an electrical idle ordered set Maximum time to transition to valid TX specifications after leaving an electrical idle condition Differential return loss 12 - - dB RLTX-CM Common mode return loss 6 - - dB DC differential TX impedance 80 100 120 Ω - - 500 + 2UI ps AC coupling capacitor 75 - 200 nF Crosslink random timeout 0 - 1 ms UI VTX-DIFFp-p VTX-DE-RATIO TTX-EYE TTX-EYE-MEDIAN-to-MAX-JITTER TTX-RISE, TTX-FALL Parameter Unit interval Differential peak to peak output voltage De-emphasized differential output voltage (Ratio) Minimum TX eye width Maximum time between the jitter median and maximum deviation from the median D+/D- TX output rise/fall time VTX-DC-CM RMS AC peak common mode output voltage Absolute delta of DC common mode voltage during L0 and electrical idle Absolute delta of DC common mode voltage between D+ and DElectrical idle differential peak output voltage The amount of voltage change allowed during receiver detection The TX DC common mode voltage ITX-SHORT TX short circuit current limit VTX-CM-ACp VTX-CM-DC-ACTIVE-IDLE-DELTA VTX-CM-DC-LINE-DELTA VTX-IDLE-DIFFp VTX-RCV-DETECT TTX-IDLE-MIN TTX-IDLE-SET-TO-IDLE TTX-IDLE-TO-DIFF-DATA ZTX-DIFF-DC LTX-SKEW CTX Tcrosslink Lane-to-lane output skew ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 39 GL9714 PCI ExpressTM PIPE x4 PHY Receiver Serial Output Table 7.7 – Receiver Serial Output Symbol UI VRX-DIFFp-p Parameter Min Typ Max Unit Unit interval 399.88 400 400.12 ps Differential input peak to peak voltage 0.175 - 1.2 V 0.4 - - UI - - 0.3 UI - - 150 mV TRX-EYE Minimum receiver eye width Maximum time between the jitter TRX-EYE-MEDIAN-to-MAX-JITTER median and maximum deviation from the median VRX-CM-ACp AC peak common mode input voltage RLRX-DIFF Differential return loss 15 - - dB RLRX-CM Common mode return loss 6 - - dB DC differential input impedance 80 100 120 DC input impedance 40 50 60 200k - - Ω Ω Ω 65 - 175 mV - - 10 ms - - 20 ns Unit ZRX-DIFF-DC ZRX-DC ZRX-HIGH-IMP-DC VRX-IDLE-DET-DIFFp-p TRX-IDLE-DET-DIFF-ENTERTIME LRX-SKEW Powered down DC input impedance Electrical idle detect threshold Unexpected electrical idle enter detect threshold integration time Total skew 7.6 Recommended Operating Conditions Table 7.8 – Temperature Range Symbol Parameter TJUNCTOIN Junction operating temperature range TA TSTG Operating ambient temperature range Storage temperature range Min Typ Max 0 - 125 0 - 75 -40 - 150 ℃ ℃ ℃ Min Typ Max Unit - 33.2 - - 28.7 - - 27.5 - ℃/W ℃/W ℃/W - 0.39 - ℃/W - 12.3 - ℃/W Table 7.9 – Thermal Characteristics Symbol Parameter θJA (0 m/s) Thermal resistance from junction to ambient PS: “(x m/s)” means the air flow velocity θJA (1 m/s) (JEDEC JESD51-6 moving air, maximum reflow θJA (2 m/s) temperature for SMT is 255 ~260 ) ℃ ΨJT θJC ℃ Thermal characterization parameter from junction-to-top center (JEDEC JESD51-2 still air, maximum reflow temperature for SMT is 255 ~260 ) Thermal resistance from junction to case (JEDEC JESD51-2 still air, maximum reflow temperature for SMT is 255 ~260 ) ℃ ℃ ℃ ℃ ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 40 GL9714 PCI ExpressTM PIPE x4 PHY CHAPTER 8 PIPE TIMING CHARACTERISTICS 8.1 Input Setup, Hold Time and Output Timing Figure 8.1 – Definition of Input Setup and Hold Time ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 41 GL9714 PCI ExpressTM PIPE x4 PHY Figure 8.2 – Definition of Output Timing Table 8.1 – Input Setup, Hold Time and Output Timing for 8-bit SDR Mode Symbol Parameter TCYCLE PCLK cycle time Duty-H Duty cycle for PCLK high TIS Input setup time requirement TIH Input hold time requirement TCO TOH Clock to output delay Output hold time 1 1 2 2 Min Typ Max Unit 3.99 4 4.01 ns 35 - 50 % 0.8 - - ns 1 - - ns - - 3.2 ns 1 - - ns Note: 1. Based on data rise time=1.9ns, fall time=1.3ns, and the slew rate is based on 20%~80% measuring. 2. The test load is 10 pf. 3. All setup, hold and Tco numbers include PCLK jitter and SSO, which is about +/- 250ps. ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 42 GL9714 PCI ExpressTM PIPE x4 PHY Table 8.2 – Input Setup, Hold Time and Output Timing for 8-bit DDR Mode Symbol Parameter TCYCLE PCLK cycle time Duty-H Duty cycle for PCLK high Min Typ Max Unit 7.98 8 8.02 ns 48 - 50 % TIS Input setup time - - 1.4 ns TIH Input hold time 0.5 - - ns TCO Clock to output delay - 1.5 1.6 ns TOH Output hold time 0.8 1 - ns Note: This table is based on design target, correlation data will be posted later. Table 8.3 – Input Setup, Hold Time and Output Timing for 16-bit Mode Symbol Parameter TCYCLE PCLK cycle time Duty-H Duty cycle for PCLK high Min Typ Max Unit 7.98 8 8.02 ns 48 - 50 % TIS Input setup time - - 1.4 ns TIH Input hold time 0.5 - - ns TCO Clock to output delay - 5.3 5.6 ns TOH Output hold time 4.3 4.7 - ns Note: This table is based on design target, correlation data will be posted later. Table 8.4 – Input Setup, Hold Time and Output Timing for 10-bit SDR Mode Symbol Parameter TCYCLE PCLK cycle time Duty-H Duty cycle for PCLK high Min Typ Max Unit 3.99 4 4.01 ns 35 - 50 % TIS Input setup time - - 1 ns TIH Input hold time 1 - - ns TCO Clock to output delay - 4 4.2 ns TOH Output hold time 3.4 3.7 - ns Note: This table is based on design target, correlation data will be posted later. ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 43 GL9714 PCI ExpressTM PIPE x4 PHY Table 8.5 – Input Setup, Hold Time and Output Timing for 10-bit DDR Mode Symbol Parameter TCYCLE PCLK cycle time Duty-H Duty cycle for PCLK high Min Typ Max Unit 7.98 8 8.02 ns 48 - 50 % TIS Input setup time - - 1.4 ns TIH Input hold time 0.5 - - ns TCO Clock to output delay - 4.1 4.3 ns TOH Output hold time 3.5 3.7 - ns Note: This table is based on design target, correlation data will be posted later. 8.2 Reference Timing Information Table 8.6 – Reference Timing Information Symbol Parameter Min Typ Max Unit TRECDET Time for receiver detection Timing from de-asserting RST_N to the falling edge of PHYSTS Reset Assertion Time to GL9714 - 10 - us - 16.7 - us 10 - - us TPHYSTS-RESET TRESET ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 44 GL9714 PCI ExpressTM PIPE x4 PHY CHAPTER 9 PACKAGE DIMENSION Figure 9.1 - GL9714 233 Pin LFBGA Package ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 45 GL9714 PCI ExpressTM PIPE x4 PHY CHAPTER 10 ORDERING INFORMATION Table 10.1 - Ordering Information Part Number Package Green Version Status GL9714-TgGxx 233-pin LFBGA Green Package xx Engineering Sample ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 46