Genesys Logic, Inc.
GL9711
PCI ExpressTM PIPE x1 PHY
Datasheet
Revision 1.10
Jul. 04, 2006
GL9711 PCI ExpressTM PIPE x1 PHY
Copyright:
Copyright © 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be
reproduced in any form or by any means without prior written consent of Genesys Logic Inc..
Disclaimer:
ALL MATERIALS ARE PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY
KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF
GENESYS LOGIC INC..
GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND
CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS,
OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT
OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY
DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF
INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN
ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO
THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE.
Trademarks:
is a registered trademark of Genesys Logic, Inc.
All trademarks are the properties of their respective owners.
Office:
Genesys Logic, Inc.
12F, No. 205, Sec. 3, Beishin Rd., Shindian City,
Taipei, Taiwan
Tel: (886-2) 8913-1888
Fax: (886-2) 6629-6168
http://www.genesyslogic.com
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 2
GL9711 PCI ExpressTM PIPE x1 PHY
Revision History
Revision
Date
0.95
7/11/2005
Preliminary release
0.96
7/27/2005
1. Modify Table3.1–Ball Out, p.11
2. Modify “PIPE Interface” and “Other Signals”, Table3.4–Pin
Descriptions, p.15~p.17
3. Modify Ch4.2 Registers Descriptions, p.19
4. Modify Ch6.10 Operation Mode and Multi-Functional Pins, p.28
5. Modify Table6.1-Pin Functions, p.28~p.30
6. Modify Table8.1~8.5, p.36~p.37
0.97
09/20/2005 Modify Package Dimension,Ch9 , p.40
0.98
11/15/2005
1.00
12/15/2005
1.01
04/13/2006
1.02
04/26/2006
1.10
07/04/2006
Description
1. Add “Bottom View”, Figures.3.1, p.10
2. Update Table3.4, p.15~p.18
3. Update Table3.5, p.18
4. Modify the default value of REG0 and REG1, Table4.1, p.19
5. Modify Ch4.2 Registers Descriptions for REG0 and REG1, p.20
6. Add Ch 4.3, p.22~p.25
7. Update Table 7.5 for power consumption, p.35
8. Change TXDx to RXDx, Figure 8.4, p.39
9. The minimum and maximum value of TCYCLE, Table8.2 and Table 8.5,
p.40
1. Update Table 7.8 for temperature ranges (p.37)
2. Update Table 8.1~8.4 for output delay of RX bus (p.39~p.40)
1. Modify the description of OSC25MI and OSC25MO signals, Table
3.4, p.15
2. Swap the Pin Out of OSC25MI and OSC25MO in Table 3.1~Table
3.4.
3. Update Table 7.1 for deleting IDD1-X4, IDD2-X4, IDD3-X4, IDD1-X2, IDD2-X2,
and IDD3-X2 six items, p.34
4. Update Table 7.8 for deleting the ISUPPLY-1.8 item and adding θJA, ΨJT
and θJC three items, p.37
Divide Table 7.8 into Table 7.8(Temperature Range) and Table
7.9(Thermal Characteristics), p.37
1. Update Table 3.5 for the parameter of buffer I/O, p.18
2. Remove Table 7.2, p.34
3. Update Fig. 8.1, 8.2 and Table 8.1~8.5 for PIPE input and output
timing characteristic, p.38~p.40
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 3
GL9711 PCI ExpressTM PIPE x1 PHY
TABLE OF CONTENTS
CHAPTER 1
GENERAL DESCRIPTION................................................. 8
CHAPTER 2
FEATURES ........................................................................... 9
CHAPTER 3
PIN ASSIGNMENT ............................................................ 10
3.1 PINOUT .................................................................................................. 10
3.2 BALL OUT ............................................................................................. 10
3.3 PIN LIST ................................................................................................ 11
3.4 PIN DESCRIPTIONS ................................................................................ 15
CHAPTER 4
REGISTERS........................................................................ 19
4.1 REGISTERS BASE ADDRESS ................................................................... 19
4.2 REGISTERS DESCRIPTIONS .................................................................... 20
4.3 SMBUS PROTOCAL ............................................................................... 22
CHAPTER 5
BLOCK DIAGRAM............................................................ 26
5.1 SIMPLIFIED DIAGRAM ........................................................................... 26
5.2 TRANSMITTER DATA PATH PER LANE .................................................. 27
5.3 RECEIVER DATA PATH PER LANE......................................................... 28
CHAPTER 6
FUNCTION DESCRIPTION ............................................. 29
6.1 CLOCK AND RESET................................................................................ 29
6.2 RECEIVER DETECTION .......................................................................... 29
6.3 BEACON TRANSMITTING AND DETECTION ............................................ 29
6.4 RECEIVER STATUS REPORT .................................................................. 29
6.5 LOOPBACK ............................................................................................ 30
6.6 POLARITY INVERSION ........................................................................... 30
6.7 SETTING NEGATIVE DISPARITY ............................................................ 30
6.8 BEHAVIOR SUMMARY............................................................................ 31
6.9 POWER SAVING SUPPORT...................................................................... 31
6.10 OPERATION MODE AND MULTI-FUNCTIONAL PINS ............................ 32
CHAPTER 7
ELECTRICAL CHARACTERISTICS.............................. 34
7.1 DC VOLTAGE SPECIFICATIONS ............................................................. 34
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 4
GL9711 PCI ExpressTM PIPE x1 PHY
7.2 TRANSMIT AND RECEIVE LATENCY TIME ............................................. 34
7.3 TRANSITION TIME OF POWER STATE .................................................... 34
7.4 POWER CONSUMPTION.......................................................................... 35
7.5 DIFFERENTIAL TRANSMITTER AND RECEIVER SERIAL OUTPUT ........... 35
7.6 RECOMMENDED OPERATING CONDITIONS ........................................... 37
CHAPTER 8
PIPE TIMING CHARACTERISTICS .............................. 38
8.1 INPUT SETUP, HOLD TIME AND OUTPUT TIMING .................................. 38
8.2 REFERENCE TIMING INFORMATION ...................................................... 40
CHAPTER 9
PACKAGE DIMENSION................................................... 41
CHAPTER 10
ORDERING INFORMATION......................................... 42
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 5
GL9711 PCI ExpressTM PIPE x1 PHY
LIST OF FIGURES
FIGURE 3.1 - 233 PIN LFBGA PINOUT DIAGRAM ..........................................................10
FIGURE 4.1 – SMBUS TOPOLOGY OF GL9711................................................................22
FIGURE 4.2 – DATA VALIDITY ........................................................................................23
FIGURE 4.3 – START AND STOP CONDITION ...............................................................23
FIGURE 4.4 – ACK AND NACK SIGNALING OF SMBUS .................................................24
FIGURE 4.5 – SMBUS PACKET PROTOCOL DIAGRAM ELEMENT KEY ............................24
FIGURE 4.6 – WRITE BYTE PROTOCOL ..........................................................................25
FIGURE 4.7 – READ BYTE PROTOCOL ............................................................................25
FIGURE 4.8 – THE MINIMUM WAIT TIME FROM POWER ON TO PROGRAMMING
REGISTERS .....................................................................................................................25
FIGURE 5.1 - SIMPLIFIED DIAGRAM ...............................................................................26
FIGURE 5.2 - TRANSMITTER DATA PATH PER LANE .......................................................27
FIGURE 5.3 - RECEIVER DATA PATH PER LANE .............................................................28
FIGURE 8.1 – DEFINITION OF INPUT SETUP AND HOLD TIME ..........................................38
FIGURE 8.2 – DEFINITION OF OUTPUT TIMING ..............................................................39
FIGURE 9.1 - GL9711 233 PIN LFBGA PACKAGE ..........................................................41
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 6
GL9711 PCI ExpressTM PIPE x1 PHY
LIST OF TABLES
TABLE 3.1 - BALL OUT ...................................................................................................10
TABLE 3.2 - NUMERIC PIN LIST......................................................................................11
TABLE 3.3 - ALPHABETIC PIN LIST ................................................................................13
TABLE 3.4 - PIN DESCRIPTIONS ......................................................................................15
TABLE 3.5 - PARAMETER OF BUFFER I/O.......................................................................18
TABLE 4.1 - BASE ADDRESS FOR REGISTERS ..................................................................19
TABLE 6.1 - PIN FUNCTIONS ...........................................................................................32
TABLE 7.1 - DC VOLTAGE SPECIFICATIONS...................................................................34
TABLE 7.2 - TRANSMIT AND RECEIVE LATENCY TIME...................................................34
TABLE 7.3 – TRANSITION TIME OF POWER STATE .........................................................34
TABLE 7.4 - POWER CONSUMPTION OF EACH POWER STATE IN DIFFERENT OPERATION
MODE .............................................................................................................................35
TABLE 7.5 – TRANSMITTER SERIAL OUTPUT .................................................................35
TABLE 7.6 – RECEIVER SERIAL OUTPUT ........................................................................36
TABLE 7.7 – TEMPERATURE RANGE...............................................................................36
TABLE 7.8 – THERMAL CHARACTERISTICS ....................................................................36
TABLE 8.1 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 8-BIT SDR MODE ...39
TABLE 8.2 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 8-BIT DDR MODE...40
TABLE 8.3 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 16-BIT MODE..........40
TABLE 8.4 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 10-BIT SDR MODE .40
TABLE 8.5 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 10-BIT DDR MODE.40
TABLE 8.6 – REFERENCE TIMING INFORMATION ...........................................................40
TABLE 10.1 - ORDERING INFORMATION .........................................................................42
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 7
GL9711 PCI ExpressTM PIPE x1 PHY
CHAPTER 1
GENERAL DESCRIPTION
The GL9711 is a 1-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base
Specification rev. 1.0a and Intel’s PHY Interface for the PCI Express Architecture rev. 1.0. It integrates one
SerDes and the Physical Coding Sublayer (PCS) which performs 8b/10b encoding and decoding, elastic buffer
and receiver detection, data serialization and deserialization. The SerDes in the GL9711 supports an effective
serial interface speed (2.5 Gb/s) of data bandwidth, intended for use in ultrahigh-speed bi-directional data
transmission system. The GL9711 can also be externally configured for various parallel bus width which is
flexible and suitable for implementation. It also supports four operational states for power management to
minimize power consumption. For production and self-test purposes, the GL9711 provides BIST and an internal
loopback capability.
The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband
data transmission over an on-chip termination resister of 50 Ohm +/- 10%.
This device can also be used to replace parallel data transmission architectures by providing a reduction in the
number of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is delivered
to the receiver over a serial channel. It is then reconstructed into its original parallel format. The maximum data
transfer rate in each direction is 256M bytes per second. It also offers various power saving modes to
significantly reduce power consumption as well as scalability for a higher data rate in the future.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 8
GL9711 PCI ExpressTM PIPE x1 PHY
CHAPTER 2
FEATURES
l
Complies with PCI Express Base Specification rev. 1.0a
l
Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0
l
Integrates 2.5 gigabit per second (Gpbs) Serializer/Deserializer
l
Supports 8-bit or 10-bit parallel interface @250MHz
l
Supports 16-bit parallel interface @125MHz
l
Supports DDR configuration for 8-bit or 10-bit mode
l
Beacon transmission and reception
l
Receiver detection
l
Transmission and detection of electrical idle
l
Clock tolerance for 600 ppm in frequencies between bit rates at the two end of a Link
l
On-chip 8-bit/10-bit encoding/decoding and comma alignment
l
On-chip PLL provides clock synthesis
l
1.8-V power supply for core
l
2.5-V power supply for IO
l
Above 2.0 kV ESD protection
l
0.18 µm process
l
Available in LFBGA-233 package
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 9
GL9711 PCI ExpressTM PIPE x1 PHY
CHAPTER 3
PIN ASSIGNMENT
3.1 Pinout
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Bottom View
Figure 3.1 - 233 Pin LFBGA Pinout Diagram
3.2 Ball Out
Table 3.1 - Ball Out
1
A REFCLKP
B REFCLKN
C OSC25MO
2
NC
NC
NC
3
VDDTX
5
VDDRX
VSSTX
NC
4
NC
NC
VDD18
D OSC25MI
7
VDDTX
VSSRX
NC
6
NC
NC
NC
VDD25
NC
VSS
8
9
VDDRX
NC
VSSTX
NC
VSSRX
VSSTX VDDPLL
NC
VSS
NC
VDD18
RTERM
VSSPLL
E
NC
NC
NC
NC
F
VSS
NC
NC
NC
G
NC
VDD25
NC
NC
VSS
VSS
VSS
H
NC
NC
NC
NC
VSS
VSS
VSS
J
NC
VSS
NC
NC
VSS
VSS
VSS
K
VDD25
NC
NC
VDD12
VSS
VSS
VSS
L
VSS
VSS
NC
VDD18
VSS
VSS
VSS
NC
VSS
NC
VDD18
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
M
NC
N
P VDD25
©2000-2006 Genesys Logic Inc. - All rights reserved.
NC
NC
Page 10
GL9711 PCI ExpressTM PIPE x1 PHY
NC
NC
VSS
NC
VDD25
NC
NC
NC
VSS
NC
NC
NC
NC
VDD25
PHYSTS
NC
VDD18
NC
VSS
NC
NC
NC
NC
NC
OPMODE0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A
TXN
VDDTX
RXN
VDDRX
NC
VDDTX
NC
VDDRX
B
TXP
VSSTX
RXP
VSSRX
NC
VSSTX
NC
VSSRX
C
D
E
VDD18
NC
NC
NC
VDD18
NC
NC
TXD8
TXD9
TXD11
TXD13
VSSGR
TXD12
TXDK1
TXD14
VDD25
TXD10
TXD15
NC
RXDK1
NC
NC
RXD8
VDD25
R
T
U
F
G
VSS
VSS
NC
RXD9
RXD10
RXD12
H
J
K
L
M
N
P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PD1
RXVLD
NC
RXD7
RXD13
VDD12
TXD2
TXCMP
RXSTS1
RXD3
RXD5
RXD11
VSS
VDD25
TXD6
TXD4
RXDK0
RXD1
RXD15
RXD14
TXDK0
TXD1
TXD3
TXD7
VSS
VDD18
VDD18
NC
TXD0
VSS
TXD5
RXSTS0
SCC
TXDET/
LPBK
TXIDLE
VDD25
NC
RXD4
RXD0
VDD25
PD0
T TESTD
U OPMODE1 TESTC
RXIDLE
RST_N
NC
RXPLR
PCLK
VSS
VSS
NC
RXD2
RXD6
RXSTS2
12
13
14
15
16
17
R
10
11
NC
VDD25
VDD25
3.3 Pin List
Table 3.2 - Numeric Pin List
Pin#
Pin Name
Pin#
Pin Name
Pin#
Pin Name
Pin#
Pin Name
Pin#
Pin Name
A1
REFCLKP
C1
OSC25MO
E1
NC
G1
NC
J1
NC
A2
NC
C2
NC
E2
NC
G2
VDD25
J2
VSS
A3
VDDTX
C3
NC
E3
NC
G3
NC
J3
NC
A4
NC
C4
VDD18
E4
NC
G4
NC
J4
NC
A5
VDDRX
C5
NC
E5
G5
J5
A6
NC
C6
NC
E6
G6
J6
A7
VDDTX
C7
VSSTX
E7
G7
VSS
J7
VSS
A8
NC
C8
VDDPLL
E8
G8
VSS
J8
VSS
A9
VDDRX
C9
NC
E9
G9
VSS
J9
VSS
A10
TXN
C10
VDD18
E10
G10
VSS
J10
VSS
A11
VDDTX
C11
NC
E11
G11
VSS
J11
VSS
A12
RXN
C12
VDD18
E12
G12
©2000-2006 Genesys Logic Inc. - All rights reserved.
J12
Page 11
GL9711 PCI ExpressTM PIPE x1 PHY
A13
VDDRX
C13
NC
E13
G13
J13
A14
NC
C14
TXD9
E14
TXD13
G14
NC
J14
VDD12
A15
VDDTX
C15
VSSGR
E15
TXDK1
G15
RXD9
J15
VSS
A16
NC
C16
TXD14
E16
TXD10
G16
RXD10
J16
RXD14
A17
VDDRX
C17
TXD15
E17
RXDK1
G17
RXD12
J17
VDD18
B1
REFCLKN
D1
OSC25MI
F1
VSS
H1
NC
K1
VDD25
B2
NC
D2
VDD25
F2
NC
H2
NC
K2
NC
B3
VSSTX
D3
NC
F3
NC
H3
NC
K3
NC
B4
NC
D4
VSS
F4
NC
H4
NC
K4
VDD12
B5
VSSRX
D5
VSS
F5
H5
K5
B6
NC
D6
NC
F6
H6
K6
B7
VSSTX
D7
VDD18
F7
H7
VSS
K7
VSS
B8
NC
D8
RTERM
F8
H8
VSS
K8
VSS
B9
VSSRX
D9
VSSPLL
F9
H9
VSS
K9
VSS
B10
TXP
D10
NC
F10
H10
VSS
K10
VSS
B11
VSSTX
D11
NC
F11
H11
VSS
K11
VSS
B12
RXP
D12
NC
F12
H12
K12
B13
VSSRX
D13
TXD8
F13
H13
K13
B14
NC
D14
TXD11
F14
NC
H14
RXD13
K14
TXD2
B15
VSSTX
D15
TXD12
F15
NC
H15
RXD11
K15
VDD25
B16
NC
D16
VDD25
F16
RXD8
H16
RXD15
K16
TXDK0
B17
VSSRX
D17
NC
F17
VDD25
H17
VDD18
K17
NC
Pin#
Pin Name
Pin#
Pin Name
Pin#
Pin Name
L1
VSS
N1
NC
R1
NC
U1
VSS
L2
VSS
N2
VSS
R2
NC
U2
NC
L3
NC
N3
NC
R3
NC
U3
VSS
L4
VDD18
N4
NC
R4
NC
U4
NC
Pin# Pin Name
L5
N5
R5
NC
U5
PHYSTS
L6
N6
R6
NC
U6
NC
L7
VSS
N7
R7
VSS
U7
NC
L8
VSS
N8
R8
NC
U8
NC
L9
VSS
N9
R9
OPMODE0
U9
VDD25
L10
VSS
N10
R10
SCC
L11
VSS
N11
R11 TXDET/LPBK U11
TESTC
L12
N12
R12
TXIDLE
U12
RST_N
L13
N13
R13
VDD25
U13
RXPLR
R14
NC
U14
VSS
L14
TXCMP
N14
RXD3
©2000-2006 Genesys Logic Inc. - All rights reserved.
U10 OPMODE1
Page 12
GL9711 PCI ExpressTM PIPE x1 PHY
L15
TXD6
N15
RXDK0
R15
RXD4
U15
NC
L16
TXD1
N16
TXD7
R16
RXD0
U16
RXD6
L17
TXD0
N17
TXD5
R17
VDD25
U17
VDD25
M1
VSS
P1
VDD25
T1
NC
M2
NC
P2
NC
T2
VDD25
M3
VDD18
P3
NC
T3
NC
M4
NC
P4
NC
T4
NC
M5
P5
NC
T5
VDD25
M6
P6
NC
T6
VDD18
M7
P7
NC
T7
NC
M8
P8
NC
T8
NC
M9
P9
VSS
T9
NC
M10
P10
PD1
T10
TESTD
M11
P11
RXVLD
T11
PD0
M12
P12
NC
T12
RXIDLE
M13
P13
RXD7
T13
NC
M14
RXSTS1
P14
RXD5
T14
PCLK
M15
TXD4
P15
RXD1
T15
VSS
M16
TXD3
P16
VSS
T16
RXD2
M17
VSS
P17
RXSTS0
T17
RXSTS2
Blank
Table 3.3 - Alphabetic Pin List
Pin Name
Pin#
Pin Name
Pin#
Pin Name
Pin#
Pin Name
Pin#
Pin Name
Pin#
NC
C3
NC
G4
NC
F15
NC
A6
VSS
H7
NC
C5
NC
E2
TXCMP
L14
NC
A2
VSS
H8
NC
C6
NC
F3
NC
R3
NC
B14
VSS
H9
NC
C9
NC
D3
NC
G1
TXP
B10
VSS
H10
NC
C11
NC
E3
TXD8
D13
NC
B6
VSS
H11
NC
C13
NC
E4
TXD9
C14
NC
B2
VSS
J2
NC
D6
NC
F4
TXD10
E16
VDD12
J14
VSS
J7
NC
D10
NC
C2
TXD11
D14
VDD12
K4
VSS
J8
NC
D11
RXDK1
E17
TXD12
D15
VDD18
C4
VSS
J9
NC
D12
RXDK0
N15
TXD13
E14
VDD18
C10
VSS
J10
NC
K17
NC
T1
TXD14
C16
VDD18
C12
VSS
J11
OPMODE0
R9
NC
E1
TXD15
C17
VDD18
D7
VSS
J15
OPMODE1
U10
NC
T13
TXD0
L17
VDD18
H17
VSS
K7
OSC25MO
C1
RXIDLE
T12
TXD1
L16
VDD18
J17
VSS
K8
OSC25MI
D1
NC
T8
TXD2
K14
VDD18
L4
VSS
K9
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 13
GL9711 PCI ExpressTM PIPE x1 PHY
PCLK
T14
NC
P8
TXD3
M16
VDD18
M3
VSS
K10
PD0
T11
NC
A16
TXD4
M15
VDD18
T6
VSS
K11
PD1
P10
RXN
A12
TXD5
N17
VDD25
D2
VSS
L1
PHYSTS
U5
NC
A8
TXD6
L15
VDD25
D16
VSS
L2
REFCLKN
B1
NC
A4
TXD7
N16
VDD25
F17
VSS
L7
REFCLKP
A1
NC
B16
NC
U4
VDD25
G2
VSS
L8
RST_N
U12
RXP
B12
NC
R6
VDD25
K1
VSS
L9
RTERM
D8
NC
B8
NC
T4
VDD25
K15
VSS
L10
RXD8
F16
NC
B4
NC
P6
VDD25
P1
VSS
L11
RXD9
G15
NC
U15
NC
U2
VDD25
R13
VSS
M1
RXD10
G16
RXPLR
U13
NC
R5
VDD25
R17
VSS
M17
RXD11
H15
NC
T9
NC
T3
VDD25
T2
VSS
N2
RXD12
G17
NC
R8
NC
R4
VDD25
T5
VSS
P9
RXD13
H14
NC
F14
NC
K2
VDD25
U9
VSS
P16
RXD14
J16
NC
G14
NC
K3
VDD25
U17
VSS
R7
RXD15
H16
NC
D17
NC
J1
VDDPLL
C8
VSS
T15
RXD0
R16
RXSTS0
P17
NC
J4
VDDRX
A17
VSS
U1
RXD1
P15
RXSTS1
M14
NC
H1
VDDRX
A13
VSS
U3
RXD2
T16
RXSTS2
T17
NC
J3
VDDRX
A9
VSS
U14
RXD3
N14
NC
P5
NC
H2
VDDRX
A5
VSSGR
C15
RXD4
R15
NC
R2
NC
H3
VDDTX
A15
VSSPLL
D9
RXD5
P14
NC
P4
TXDET/LPBK
R11
VDDTX
A11
VSSRX
B17
RXD6
U16
NC
H4
TXDK1
E15
VDDTX
A7
VSSRX
B13
RXD7
P13
NC
F2
TXDK0
K16
VDDTX
A3
VSSRX
B9
NC
N4
NC
G3
NC
P7
VSS
D4
VSSRX
B5
NC
P2
NC
P12
NC
L3
VSS
D5
VSSTX
B15
NC
P3
RXVLD
P11
NC
R14
VSS
F1
VSSTX
B11
NC
R1
NC
U7
TXIDLE
R12
VSS
G7
VSSTX
B7
NC
M4
NC
U6
NC
U8
VSS
G8
VSSTX
C7
NC
N1
SCC
R10
NC
T7
VSS
G9
VSSTX
B3
NC
N3
TESTC
U11
NC
A14
VSS
G10
NC
M2
TESTD
T10
TXN
A10
VSS
G11
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 14
GL9711 PCI ExpressTM PIPE x1 PHY
3.4 Pin Descriptions
Table 3.4 - Pin Descriptions
PIPE Interface
Pin Name
I/O Standard
Pin#
Type
Description
RST_N
LVCMOS2
U12
I
PCLK
SSTL2_I
T14
O
RXSTS[2:0]
SSTL2_I
T17, M14, P17
O
RXIDLE
LVCMOS2
T12
O
PHYSTS
SSTL2_I
U5
O
RXVLD
LVCMOS2
P11
O
TXCMP
SSTL2_I
L14
I
TXIDLE
LVCMOS2
R12
I
Global reset
Parallel interface clock
All data movement across the parallel
interface is synchronous to this clock.
1. For 8-bit mode:
PCLK operates at 250 MHz and is
applied to synchronize all TXD, RXD
data bus and all commands.
2. For 16-bit mode:
PCLK operates at 125 MHz and is
applied to synchronize all TXD, RXD
data bus and all commands.
3. For 10-bit mode(TBC):
PCLK operates at 250 MHz and is
applied to synchronize the TXD data bus
and all commands.
1. For 8-bit and 16-bit modes:
Encodes receiver status and error codes
for the received data stream and receiver
detection
000 Received data OK
001 1 SKP added
010 1 SKP removed
011 Receiver detected
100 8B/10B decode error
101 Elastic Buffer overflow
110 Elastic Buffer underflow
111 Receiver disparity error
2. For 10-bit modes:
RXSTS[2]: RBC, synchronize the RXD
data bus
RXSTS[1]: RXPRSNT, report the result
of receiver detection
RXSTS[0]: RXD9, bit 9 of RXD data
bus
Indicates receiver detection of an electrical
idle
This is an asynchronous signal.
Used to communicate completion of several
PHY functions including power state
transitions and receiver detection
Indicates symbol lock and valid data on
RXDx and RXDKx
1. For 8-bit and 16-bit modes:
Sets the running disparity to negative
2. For 10-bit mode:
TXD9, bit 9 of TXD data bus
Forces Tx output to electrical idle
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 15
GL9711 PCI ExpressTM PIPE x1 PHY
RXDK[1:0]
SSTL2_I
E17, N15
O
RXD[15:0]
SSTL2_I
H16, J16, H14, G17,
H15, G16, G15, F16,
P13, U16, P14, R15,
N14, T16, P15, R16
O
TXDK[1:0]
SSTL2_I
E15, K16
I
TXD[15:0]
TXDET/LPBK
PD[1:0]
C17, C16, E14, D15,
D14, E16, C14, D13,
SSTL2_I
N16, L15, N17, M15,
M16, K14, L16, L17
LVCMOS2
R11
LVCMOS2
P10, T11
I
I
I
1. For 8-bit and 16-bit modes:
K-code indication for the received
symbols
In 8-bit mode, RXDK = RXDK0
In 16-bit mode, RXDK = {RXDK1,
RXDK0}
2. For 10-bit mode:
RXDK[0]: RXD8, bit 8 of RXD data bus
RXD[7:0]: Parallel data output bus for all
8-bit, 16-bit and 10-bit modes
RXD[15:0]: Parallel data output bus for
16-bit mode only
1. For 8-bit and 16-bit modes:
K-code indication for the transmitted
symbols
In 8-bit mode, TXDK = TXDK0
In 16-bit mode, TXDK = {TXDK1,
TXDK0}
2. For 10-bit mode:
TXDK[0]: TXD8, bit 8 of TXD data bus
TXD[7:0]: Parallel data input bus for all
8-bit, 16-bit and 10-bit modes
TXD[15:0]: Parallel data input bus for
16-bit mode only
Receiver detection/Loopback
Sets the power states
00 P0, normal operation
01 P0s, low recovery time latency,
power saving state
10
RXPLR
LVCMOS2
I
U13
P1, longer recovery time(64us max)
latency, lower power state
11 P2, lowest power state
Inverts the polarity on the RXP/RXN
Power and Ground Signals
Pin Name
VDD25
VDD18
Pin#
D2, D16, F17, G2, K1, K15, P1,
R13, R17, T2, T5, U9, U17
C4, C10, C12, D7, H17, J17, L4,
M3, T6
VDD12
J14, K4
D4, D5, F1, G7, G8, G9, G10, G11,
H7, H8, H9, H10, H11, J2, J7, J8,
J9, J10, J11, J15, K7, K8, K9, K10,
VSS
K11, L1, L2, L7, L8, L9, L10, L11,
M1, M17, N2, P9, P16, R7, T15, U1,
U3, U14
VDDPLL
C8
VSSPLL
VDDRX
VSSRX
VDDTX
VSSTX
D9
A17, A13, A9, A5
B17, B13, B9, B5
A15, A11, A7, A3
B15, B11, B7, C7, B3
©2000-2006 Genesys Logic Inc. - All rights reserved.
Type
Description
P
2.5V Power Supplies for general I/O
P
1.8V Power Supplies for core and bias voltage
P
1.25V Reference Voltage for high speed I/O
P
Digital ground
P
1.8V Power Supplies for internal PLL
P
Ground for internal PLL
P
1.8V Power Supplies for receiver part
P
1.8V Power Supplies for transceiver part
Page 16
GL9711 PCI ExpressTM PIPE x1 PHY
VSSGR
C15
P
Ground for the guard ring of the SerDes block
Serial Signals
Pin Name
Pin#
Type
Description
RXN
A12
I
Received serial input, complement
RXP
B12
I
Received serial input, true
RTERM
D8
I
TXN
A10
O
Connects an external 5.1KΩ resistor to ground for calibrating the
on-chip termination resistors
Transmitted serial output, complement
TXP
B10
O
Transmitted serial output, true
Other Signals
Pin Name
I/O
Standard
Pin#
Type
REFCLKP
Analogue
A1
I
Reference clock signal
REFCLKN
Analogue
B1
I
Reference clock signal
OSC25MO
Crystal
C1
O
OSC25MI
Crystal/
Oscillator
D1
I
TESTC/SMC LVCMOS2
U11
I
TESTD/SMD LVCMOS2
T10
SCC
LVCMOS2
OPMODE[1:0] LVCMOS2
NC
-
R10
U10, R9
A2, A4, A6, A8,
A14, A16, B2, B4,
B6, B8, B14, B16,
C2, C3, C5, C6,
C9, C11, C13, D3,
D6, D10, D11,
D12, D17, E1, E2,
E3, E4, F2, F3, F4,
F14, F15, G1, G3,
G4, G14, H1, H2,
H3, H4, J1, J3, J4,
K2, K3, K17, L3,
©2000-2006 Genesys Logic Inc. - All rights reserved.
Description
Connect to 25MHz crystal when using
crystal as the reference clock source
Connect to 25MHz crystal/oscillator
when using crystal/oscillator as the
reference clock source
Test clock/SMBus clock
I/O Test data/SMBus data
Configures clock input source
When SCC=1, the chip clock sources from a
pair of differential signals, REFCLKP and
I REFCLKN, with a nominal frequency of 100
MHz.
When SCC=0, the chip clock sources from a
crystal at 25MHz.
Operational Mode of the GL9711
00 8-bit mode
01 16-bit mode
I
10 10-bit mode
11 Internal use only
-
No connection
Page 17
GL9711 PCI ExpressTM PIPE x1 PHY
M2, M4, N1, N3,
N4, P2, P3, P4, P5,
P6, P7, P8, P12,
R1, R2, R3, R4,
R5, R6, R8, R14,
T1, T3, T4, T7, T8,
T9, T13, U2, U4,
U6, U7, U8, U15
Note: ”NC” pins should be left open on circuit board.
Table 3.5 - Parameter of Buffer I/O
Buffer type
VIH
VIL
VOH
VOL
(Input High Voltage, (Input Low Voltage, (Output High Voltage, (Output Low Voltage,
V)
V)
V)
V)
Min
Norm
Max
Min
Norm
Max
Min
Norm
Max
Min
Norm
Max
LVCMOS2
1.7
-
-
-
-
0.7
2.4
-
-
-
-
0.4
SSTL2
1.57
-
-
-
-
0.93
1.76
-
-
-
-
0.74
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 18
GL9711 PCI ExpressTM PIPE x1 PHY
CHAPTER 4
REGISTERS
There are some registers built-in the GL9711 for test purpose. These registers can be accessed through a serial
bus interface using pin TESTC and TESTD. Registers at Offset 05h ~ 0Bh are for internal test only. Please be
careful to leave them as default values.
4.1 Registers Base Address
Table 4.1 - Base Address for Registers
Mnemonic
Offset
REVID
00h
Revision ID and Auto-calibration Result Register
XCVROPT
01h
Transceiver Option Register
8’hE9
LPBKTEST
02h
BIST and Beacon/Test Data Pattern Register, Part 1
8’h00
BCNPAT2
03h
Beacon/Test Data Pattern Register, Part 2
8’h03
BCNPAT3
04h
Beacon/Test Data Pattern Register, Part 3
8’hFF
-
05h
For internal test only
-
-
06h
For internal test only
-
-
07h
For internal test only
-
-
08h
For internal test only
-
-
09h
For internal test only
-
-
0Ah
For internal test only
-
-
0Bh
For internal test only
-
BT
0Ch
Buffer Test Register
8’h00
SLCDT
0Dh
Serial Loopback and Comma Detect Test Register
8’h00
Notation:
R/W
R/O
W/O
R/W1C
R/W/C
Description
Default
8’bxxxx1xxx
Read / Write
Read Only
Write Only
Read / Write “1” to Clear
Read / Write and hardware automatic Clear
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 19
GL9711 PCI ExpressTM PIPE x1 PHY
4.2 Registers Descriptions
Offset 00h – REVID …………………………………………….………… Default value = 8’bxxxx1xxx
REV3
REV2
REV1
REV0
BY1
RCAL0
RCAL1
RCAL2
R
R
R
R
R
R
R
R
7-4 REV[3:0]
3 BY1
2-0 RCAL[0:2]
Chip revision code
x1 package
Calibration result of on-chip termination resistors
Offset 01h – XCVROPT ……………………………………………..…………. Default value = 8’hE9
SW1
SW0
DEM1
DEM0
BW0
BW1
RDEF
FEVAL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-6 SW[1:0]
5-4 DEM[1:0]
3-2 BW[0:1]
1 RDEF
0 FEVAL
Swing control of transmitter output
Output Swing (Differential, peak-to-peak)
00 0.6V
01 0.8V
10 1.0V
11 1.2V
De-emphasis control of transmitter output
Amount of De-emphasis
00 No de-emphasis
01 -1.6dB
10 -3.5dB
11 -6.0dB
Bandwidth control of clock recovery circuit
Relative Bandwidth
00 1
01 2
10 4
11 Reserved
Disable calibration of on-chip termination resistors and leave the resistors to
their default value
Force calibration of on-chip termination resistors
When RDEF=0, writing a one to this bit will make the resistors re-calibrated. This
bit is auto-cleared and always read as zero.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 20
GL9711 PCI ExpressTM PIPE x1 PHY
Offset 02h – LPBKTEST …………………………………………..…………. Default value = 8’h00
BIST0
BIST1
BIST2
--
BCN19
BCN18
BCN17
BCN16
R/W
R/W
R/W
--
R/W
R/W
R/W
R/W
7-5 BIST[0:2]
Select of built-in test pattern
Bit
Pattern
00x BIST disabled
100 0000000000 0000000000
010 1111111111
1111111111
110 0101010101 0101010101
101 0011111010 1010101010
1100000101 0101010101
011 0011111010 10100*01010
1100000101 01011*10101
111 PRBS pattern
It should be noted that the expected pattern while BIST[0:2]=011 is the same as
BIST[0:2]=101. But when coming out of the transmitter, the two bits with “*” in
BIST[0:2]=011 are different from BIST[0:2]=101. As a result, even when there is
no bit error, there will be bit errors intentionally introduced to verify the BIST
circuit is functional.
Data pattern for beacon and TXTEST
4 RESERVED
3-0 BCN[19:16]
Offset 03h – BCNPAT2 ………………………………………………….……. Default value = 8’h03
BCN15
BCN14
BCN13
BCN12
BCN11
BCN10
BCN9
BCN8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 BCN[15:8]
Data pattern for beacon and TXTEST
Offset 04h – BCNPAT3 ………………………………………………….……. Default value = 8’hFF
BCN7
BCN6
BCN5
BCN4
BCN3
BCN2
BCN1
BCN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 BCN[7:0]
Data pattern for beacon and TXTEST
Offset 0Ch – BT ……………...…………………………………………...……. Default value = 8’h00
--
--
DDR
REN
TXTEST
PLPBK
SKPDEL
SKPADD
--
--
R/W
R/W
R/W
R/W
R/W
R/W
7-6 RESERVED
5 DDR
4 REN
3 TXTEST
2 PLPBK
Enable DDR at PIPE interface and make PCLK = 125MHz @ 8/10-bit mode
Enable terminator for REFCLKP/N
Enable transmitter test with data pattern BCN[19:0], which are programmed in
REG02h, 03h and 04h
Enable parallel loopback of PCS
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 21
GL9711 PCI ExpressTM PIPE x1 PHY
1 SKPDEL
0 SKPADD
Enable SKP deleting test of SKP ordered sets
Enable SKP adding test of SKP ordered sets
Offset 0Dh – SLCDT ………...…………………………………………...……. Default value = 8’h00
7
6
5-3
2
1-0
--
SLPBK
--
--
--
FENCD
--
--
--
R/W
--
--
--
R/W
--
--
RESERVED
SLPBK
RESERVED
FENCD
RESERVED
Enable serial loopback
Force comma detect
-
4.3 SMBus Protocal
GL9711 registers are programmed by System Management Bus (SMBus). Fig. 4.1 shows the SMBus
topology. The VDD power is 2.5V +/- 10% and the pull up resistor is 1KΩ. Both SMBCLK and SMBDAT
lines are bi-directional, connected to 2.5V supply voltage through a pull-up resistor. The operating frequency
is 10~100KHz and the SMBus address of GL9711 is 7’h2C.
Figure 4.1 – SMBus Topology of GL9711
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 22
GL9711 PCI ExpressTM PIPE x1 PHY
SMBus uses fixed voltage levels to define the logic “ZERO” and logic “ONE” on the bus respectively. The data
on SMBDAT must be stable during the “HIGH” period of the clock. Data can change state only when SMBCLK
is low. Fig. 4.2 illustrates the relationships.
Figure 4.2 – Data Validity
Two unique bus situations define a message START and STOP condition.
1. A HIGH to Low transition of the SMBDAT line while SMBCLK is HIGH indicates a message START
condition.
2. A LOW to HIGH transition of the SMBDAT line while SMBCLK is HIGH defines a message STOP
condition.
Figure 4.3 – START and STOP Condition
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 23
GL9711 PCI ExpressTM PIPE x1 PHY
Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an acknowledge bit. Bytes
are transferred with the most significant bit (MSB) first. Fig. 4.4 illustrates the positioning of acknowledge
(ACK) and not acknowledge (NACK) pulses relative to other data.
Figure 4.4 – ACK and NACK Signaling of SMBus
Below is a key to the protocol diagrams.
S
Sr
Rd
Wr
x
`
A
P
Start Condition
Repeated Start Condition
Read (bit value of 1)
Write (bit value of 0)
Shown under a field indicates that that
field is required to have the value of ‘x’
Acknowledge (this bit position may be
‘0’ for an ACK or ‘1’ for a NACK)
Stop Condition
Master-to-GL9711
GL9711-to-Master
Figure 4.5 – SMBus Packet Protocol Diagram Element Key
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 24
GL9711 PCI ExpressTM PIPE x1 PHY
The first byte of a Write Byte access is the command code. The next one byte is the data to be written. In this
example the master asserts GL9711’s address followed by the write bit. GL9711 acknowledges and the master
delivers the command code. GL9711 again acknowledges before the master sends the data byte. GL9711
acknowledges the data byte, and the entire transaction is finished with a STOP condition.
Figure 4.6 – Write Byte Protocol
Reading data is slightly more complicated than writing data. First the host must write a command to GL9711.
Then it must follow that command with a repeated START condition to denote a read from GL9711’s address.
GL9711 then returns one byte of data.
Note that there is no STOP condition before the repeated START condition, and that a NACK signified the end
of the read transfer.
Figure 4.7 – Read Byte Protocol
GL9711 requires a minimum time (16us) to reach the steady state after power on. So the master must start
programming at least 16us later after power on.
Figure 4.8 – The Minimum Wait Time from Power on to Programming Registers
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 25
GL9711 PCI ExpressTM PIPE x1 PHY
CHAPTER 5
BLOCK DIAGRAM
5.1 Simplified Diagram
Figure 5.1 - Simplified Diagram
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 26
GL9711 PCI ExpressTM PIPE x1 PHY
5.2 Transmitter Data Path Per Lane
Data
x16 or x8
PCLK
Optional 16, 8-bit
x8
TXCMP
8b 10b Encoding
250 MHz
TXDK0,TXDK1
From PLL
x10
Loopback path from receiver
Parallel to Serial Conversion
2.5 GHz
TXIDLE
Transmitter Differential Driver
TXDET/LPBK
TXP
TXN
Figure 5.2 - Transmitter Data Path per Lane
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 27
GL9711 PCI ExpressTM PIPE x1 PHY
5.3 Receiver Data Path Per Lane
RXP
RXN
Differential Recieiver
RXIDLE
2.5 GHz
Clock Recovery Circuit
Data Recovery Circuit
(DRC)
RXPLR
Serial to Paralle
K28.5 Detection
RXVLD
x10
Recovered Symbol Clock
Elastic Buffer
Buffer Overflow/Underflow
SKP Added/Removed
Decode Error
x10
250 MHz
Receiver
Status
RXSTS
Disparity
Error
8b 10b Decoder
RXDK
x8
Loopback path to transmitter
Optional 8, 16-bit
PCL
Data
x16 or x8
Figure 5.3 - Receiver Data Path per Lane
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 28
GL9711 PCI ExpressTM PIPE x1 PHY
CHAPTER 6
FUNCTION DESCRIPTION
6.1 Clock and Reset
The clock source of the GL9711 comes externally from either the 100 MHz differential clock pair or the 25MHz
crystal, which is selectable by pin SCC. The GL9711 uses the clock source with its PLL to generate the 2.5 GHz
bit rate for transmitting and receiving.
The GL9711 also drives a clock output for the synchronization of MAC interface. Since the MAC interface can
be configured to 8-bit, 16-bit and 10-bit mode, the clock, PCLK, runs at 250 MHz for 8-bit mode and 125 MHz
for 16-bit mode. The MAC should use the rising edge of the clock to send and receive parallel data.
To initialize the GL9711, the MAC should assert the reset of the GL9711 to low. While the reset is asserted, the
MAC should also make TXDET/LPBK deasserted, TXIDLE asserted, TXCMP deasserted, RXPLR deasserted
and PD[1:0] = P1. When the GL9711 senses its reset asserted, it will drive its PHYSTS high immediately. After
the reset deasserted, the GL9711 requires typically 16.7us for internal PLL stable and then transitions its
PHYSTS to low. When MAC deasserts the reset, it should monitor the state of PHYSTS to make sure the
GL9711 is ready for normal operation.
6.2 Receiver Detection
The receiver detection can only be performed while the GL9711 is in P1 state. To instruct the GL9711 to enter a
receiver detection sequence, the MAC asserts TXDET/LPBK and hold it asserted until the GL9711 asserts
PHYSTS for response. While finishing the receiver detection, the GL9711 will assert PHYSTS and present a
appropriate value to RXSTS[2:0] to signal a detection completion. When the MAC detects PHYSTS asserted, it
knows the detection result from RXSTS[2:0] and can deassert TXDET/LPBK.
6.3 Beacon Transmitting and Detection
Beacon transmitting is required for the GL9711 in P2 state to wake up the receiver in the other side of the link.
When the GL9711 is in P2 state, the MAC can deassert TXIDLE to instruct the GL9711 to repeatedly transmit a
beacon.
For the beacon receiving side, if the GL9711 receives a beacon, it will transition RXIDLE to low to indicate an
exit from electrical idle. When the GL9711 is in P2 state and MAC senses the RXIDLE transitioned from high to
low, it knows a beacon has been detected.
6.4 Receiver Status Report
l
l
Add and Remove a SKP
The GL9711 implements an elastic buffer to compensate the clock rate difference between the recovery clock
and its transmit clock. While receiving a SKP ordered-set, compliant to PCI Express Base specification
REV. 1.0a, the GL9711 can insert or remove one SKP symbol in the SKP ordered-set to avoid the buffer
overrun or underrun. Whenever adding or removing a SKP symbol, the GL9711 will signal PHYSTS and
corresponding RXSTS[2:0] to MAC.
SKP Ordered-Set Received
RXSTS Code
Add a SKP
Remove a SKP
001b
010b
Detected Result
RXSTS code
Receiver not present
Receiver present
000b
011b
Receiver Detected
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 29
GL9711 PCI ExpressTM PIPE x1 PHY
l
8B/10B Decode Error
When the GL9711 decodes the received 10-bit symbol and detects an error code which does not
correspond to any valid data, it will replace the code with an EDB symbol, assert PHYSTS and encode
RXSTS[2:0] with the values of decode error status, 3’b100.
l
Elastic Buffer Overrun and Underrun
When the overrun or underrun of the elastic buffer occurs, the GL9711 will assert PHYSTS and encode
RXSTS[2:0] with the values of decode error status.
Elastic Buffer
RXSTS Code
Overrun
Underrun
101b
110b
In the case of elastic buffer overrun, the GL9711 drops the symbol. For the elastic buffer underrun, the
GL9711 inserts the EDB symbol. The PHYSTS and RXSTS[2:0] are presented on the MAC interface
during the clock cycle where GL9711 drops or inserts the symbol.
l
Disparity Errors
To report a disparity error detected, the GL9711 asserts PHYSTS and encodes RXSTS[2:0] with the values
of decode error status, 3’b111.
6.5 Loopback
The GL9711 supports a Loopback mode to re-transmit its received data. When the MAC sets the GL9711 in P0
state and asserts TXDET/LPBK, the GL9711 enters a Loopback. In Loopback, the GL9711 transmits data from it
received data instead of MAC interface. Meanwhile, it presents the received data on the MAC interface as
normal operation.
When set into Loopback mode and acting as a Loopback slave according to the PCI Express Base Specification
Rev. 1.0a, the GL9711 received data from the Loopback master. If the master intends to end the Loopback, it
sends an electrical idle ordered-set to the GL9711. When the MAC detects the electrical idle ordered-set, it
de-asserts TXDET/LPBK and asserts TXIDLE to instruct the GL9711 to stop Loopback. The MAC should take
care the GL9711 has retransmit at least three bytes of the electrical idle before it makes the GL9711’s transmitter
into electrical idle.
6.6 Polarity Inversion
The GL9711 supports lane polarity inversion. While pin RXPLR asserted, the GL9711 inverts its received data
on the MAC interface.
6.7 Setting Negative Disparity
To set the running disparity to negative, the MAC asserts TXCMP for one PCLK cycle that matches with the
data that is to be transmitted where running disparity is negative.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 30
GL9711 PCI ExpressTM PIPE x1 PHY
6.8 Behavior Summary
PD[1:0]
P0
P0S
P1
P2
TXDET/LPBK
TXIDLEx
Behavior
0
0
GL9711 is transmitting data from MAC interface normally.
0
1
GL9711 is not transmitting and is in electrical idle.
1
0
GL9711 enters Loopback mode.
1
1
Illegal
X
0
Illegal
X
1
GL9711 is not transmitting and is in electrical idle.
X
0
Illegal
0
1
GL9711 is idle.
1
1
GL9711 performs a receiver detection.
X
0
GL9711 transmits a beacon.
X
1
GL9711 is idle.
6.9 Power Saving Support
The GL9711 supports four power states including P0, P0s, P1 and P2 and can be controlled to perform Active
State Power Management on a PCI Express link. P0 is the normal operational state where data and control
packets can be transmitted and received. When directed from P0 to a lower power state, the GL9711 can
immediately take appropriate power saving actions. The power saving scheme of the GL9711 for various power
down states is listed in the table below.
PD[1:0]
Transmitter
Receiver
PLL
PCLK Output
P0
On
High-impedance
Electrical Idle
On
On
On
On
On
On
Off but exit from
Electrical Idle is
detectable
On
On
Off but exit from
Electrical Idle is
detectable
Off
Off
P0s
P1
P2
High-impedance
Electrical Idle
High-impedance
Electrical Idle
(Capable of transmitting
a Beacon)
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 31
GL9711 PCI ExpressTM PIPE x1 PHY
6.10 Operation Mode and Multi-Functional Pins
There are four modes for GL9711 operation which is selected by pin OPMODE[1:0].
Mode
[1]
[0]
1
2
3
4
0
0
1
1
0
1
0
1
Description
8 bit mode
16 bit mode
10 bit mode
Internal use only
Mode 1: The GL9711 is configured into 8-bit parallel bus.
The parallel bus is synchronous with PCLK at 250 MHz.
Mode 2: The GL9711 acts as a 1-lane PHY with a 16-bit parallel interface at 125 MHz.
Mode 3: The GL9711 is configured as a SerDes with 10-bit parallel bus.
Mode 4: For internal use only
Table 6.1 - Pin Functions
Pin Number
T14
C17
C16
E14
D15
D14
E16
C14
D13
N16
L15
N17
M15
M16
K14
L16
L17
E15
K16
R12
L14
U13
H16
J16
H14
G17
H15
Mode 1
PCLK(O)
TXD7(I)
TXD6(I)
TXD5(I)
TXD4(I)
TXD3(I)
TXD2(I)
TXD1(I)
TXD0(I)
TXDK(I)
TXIDLE(I)
TXCMP(I)
RXPLR(I)
©2000-2006 Genesys Logic Inc. - All rights reserved.
Mode 2
PCLK(O)
TXD15(I)
TXD14(I)
TXD13(I)
TXD12(I)
TXD11(I)
TXD10(I)
TXD9(I)
TXD8(I)
TXD7(I)
TXD6(I)
TXD5(I)
TXD4(I)
TXD3(I)
TXD2(I)
TXD1(I)
TXD0(I)
TXDK1(I)
TXDK0(I)
TXIDLE(I)
TXCMP(I)
RXPLR(I)
RXD15(O)
RXD14(O)
RXD13(O)
RXD12(O)
RXD11(O)
Mode 3
TBC(O)
TXD7(I)
TXD6(I)
TXD5(I)
TXD4(I)
TXD3(I)
TXD2(I)
TXD1(I)
TXD0(I)
TXD8(I)
TXIDLE(I)
TXD9(I)
RXPLR(I)
Page 32
GL9711 PCI ExpressTM PIPE x1 PHY
G16
G15
F16
P13
U16
P14
R15
N14
T16
P15
R16
E17
N15
P11
T17
M14
P17
U5
T12
RXD7(O)
RXD6(O)
RXD5(O)
RXD4(O)
RXD3(O)
RXD2(O)
RXD1(O)
RXD0(O)
RXDK(O)
RXVLD(O)
RXSTS2(O)
RXSTS1(O)
RXSTS0(O)
PHYSTS(O)
RXIDLE(O)
©2000-2006 Genesys Logic Inc. - All rights reserved.
RXD10(O)
RXD9(O)
RXD8(O)
RXD7(O)
RXD6(O)
RXD5(O)
RXD4(O)
RXD3(O)
RXD2(O)
RXD1(O)
RXD0(O)
RXDK1(O)
RXDK0(O)
RXVLD(O)
RXSTS2(O)
RXSTS1(O)
RXSTS0(O)
PHYSTS(O)
RXIDLE(O)
RXD7(O)
RXD6(O)
RXD5(O)
RXD4(O)
RXD3(O)
RXD2(O)
RXD1(O)
RXD0(O)
RXD8(O)
RXVLD(O)
RBC(O)
RXPRSNT(O)
RXD9(O)
PHYSTS(O)
RXIDLE(O)
Page 33
GL9711 PCI ExpressTM PIPE x1 PHY
CHAPTER 7
ELECTRICAL CHARACTERISTICS
7.1 DC Voltage Specifications
Table 7.1 - DC Voltage Specifications
Symbol
Parameter
Min
Typ
Max
Unit
VDD25
PHY Interface Voltage
2.375
2.5
2.625
V
VDD18
Core Voltage
1.71
1.8
1.89
V
VDD12
Reference Voltage for PHY Inerface
1.1875
1.25
1.3125
V
VDDTX
Voltage for Transmitters
1.71
1.8
1.89
V
VDDRX
Voltage for Receivers
1.71
1.8
1.89
V
1.71
1.8
1.89
V
VDDPLL Voltage for PLL
7.2 Transmit and Receive Latency Time
Table 7.2 - Transmit and Receive Latency Time
Symbol
TTX-LAT
TRX-LAT
Parameter
Transmit Latency, time for data moving from
MAC interface (PCLK rising edge) to TX serial
lines (the first bit of 10-bit symbol)
Receive Latency, time for data moving from RX
serial lines (the first bit of 10-bit symbol) to
MAC interface (PCLK rising edge)
Min
Typ
Max
Unit
25
-
30
ns
48
-
54
ns
Min
Typ
Max
Unit
52
-
74
ns
52
-
74
ns
16
-
17
µs
52
-
74
ns
52
-
74
ns
16
-
17
µs
7.3 Transition Time of Power State
Table 7.3 – Transition Time of Power State
Symbol
TP0S-P0
TP1-P0
TP2-P1
TP0-P0S
TP0-P1
TP0-P2
Parameter
Time for PHY to return to P0, after having been
in P0s. Time is measured when PD[1:0] are set to
P0 until the PHY asserts PHYSTS
Time for PHY to return to P0, after having been
in P1. Time is measured when PD[1:0] are set to
P0 until the PHY asserts PHYSTS
Time for PHY to return to P1, after having been
in P2. Time is measured when PD[1:0] are set to
P1 until the PHY asserts PHYSTS
Time for PHY to return to P0s, after having been
in P0. Time is measured when PD[1:0] are set to
P0s until the PHY asserts PHYSTS
Time for PHY to return to P1, after having been
in P0. Time is measured when PD[1:0] are set to
P1 until the PHY asserts PHYSTS
Time for PHY to return to P2, after having been
in P0. Time is measured when PD[1:0] are set to
P2 until the PHY asserts PHYSTS
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 34
GL9711 PCI ExpressTM PIPE x1 PHY
7.4 Power Consumption
l
Power Consumption
Table 7.4 - Power Consumption of Each Power State in Different Operation Mode
Current at
Current at
Analogue 1.8V
Digital 1.8V
(mA)
(mA)
90
57
Current at 2.5V
(mA)
59
Power
Operation Power
Condition State
Operation Mode Consumption
(mW)
All on
P0
16-bit @125MHz
412.1
PCLK
PLL on
12
71
49
TX idle
16-bit @125MHz
P0s
246
PCLK
RX on
PLL on
12
64
38
TX idle
16-bit @125MHz
P1
213.6
PCLK
RX idle
PLL off
6
36
6
TX idle
16-bit @3.13MHz
P2
90.6
PCLK
RX idle
7.5 Differential Transmitter and Receiver Serial Output
l
Transmitter Serial Output
Table 7.5 – Transmitter Serial Output
Symbol
UI
VTX-DIFFp-p
VTX-DE-RATIO
TTX-EYE
TTX-EYE-MEDIAN-to-MAX-JITTER
TTX-RISE,
TTX-FALL
VTX-CM-ACp
VTX-CM-DC-ACTIVE-IDLE-DELTA
VTX-CM-DC-LINE-DELTA
VTX-IDLE-DIFFp
Parameter
Unit interval
Differential peak to peak output voltage
De-emphasized
differential
output
voltage (Ratio)
Minimum TX eye width
Maximum time between the jitter
median and maximum deviation from
the median
D+/D- TX output rise/fall time
RMS AC peak common mode output
voltage
Absolute delta of DC common mode
voltage during L0 and electrical idle
Absolute delta of DC common mode
voltage between D+ and DElectrical idle differential peak output
©2000-2006 Genesys Logic Inc. - All rights reserved.
Min
Typ
Max
Unit
399.88
400
400.12
ps
0.8
-
1.2
UI
-3.0
-3.5
-4.0
dB
0.7
-
-
UI
-
-
0.15
UI
0.125
-
-
UI
-
-
20
mA
0
-
100
mA
0
-
25
mA
0
-
20
mA
Page 35
GL9711 PCI ExpressTM PIPE x1 PHY
voltage
-
-
600
mA
VTX-DC-CM
The amount of voltage change allowed
during receiver detection
The TX DC common mode voltage
0
-
3.6
V
ITX-SHORT
TX short circuit current limit
-
-
90
mA
50
-
-
UI
-
-
20
UI
-
-
20
UI
RLTX-DIFF
Minimum time spent in electrical idle
Maximum time to transition to a valid
electrical idle after sending an electrical
idle ordered set
Maximum time to transition to valid TX
specifications after leaving an electrical
idle condition
Differential return loss
12
-
-
dB
RLTX-CM
Common mode return loss
6
-
-
dB
DC differential TX impedance
80
100
120
Ω
AC coupling capacitor
75
-
200
nF
Crosslink random timeout
0
-
1
ms
VTX-RCV-DETECT
TTX-IDLE-MIN
TTX-IDLE-SET-TO-IDLE
TTX-IDLE-TO-DIFF-DATA
ZTX-DIFF-DC
CTX
Tcrosslink
l
Receiver Serial Output
Table 7.6 – Receiver Serial Output
Symbol
Min
Typ
Max
Unit
Unit interval
399.88
400
400.12
ps
Differential input peak to peak voltage
0.175
-
1.2
V
0.4
-
-
UI
-
-
0.3
UI
VRX-CM-ACp
Minimum receiver eye width
Maximum time between the jitter
median and maximum deviation from
the median
AC peak common mode input voltage
-
-
150
mV
RLRX-DIFF
Differential return loss
15
-
-
dB
RLRX-CM
Common mode return loss
6
-
-
dB
DC differential input impedance
80
100
120
Ω
DC input impedance
40
50
60
Ω
200k
-
-
Ω
65
-
175
mV
-
-
10
ms
UI
VRX-DIFFp-p
TRX-EYE
TRX-EYE-MEDIAN-to-MAX-JITTER
ZRX-DIFF-DC
ZRX-DC
ZRX-HIGH-IMP-DC
VRX-IDLE-DET-DIFFp-p
TRX-IDLE-DET-DIFF-ENTERTIME
Parameter
Powered down DC input impedance
Electrical idle detect threshold
Unexpected electrical idle enter detect
threshold integration time
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 36
GL9711 PCI ExpressTM PIPE x1 PHY
7.6 Recommended Operating Conditions
Table 7.7 – Temperature Range
Symbol
Parameter
TJUNCTOIN Junction operating temperature range
TA
TSTG
Operating ambient temperature range
Storage temperature range
Min
Typ
Max
Unit
0
-
125
℃
0
-
75
℃
-40
-
150
℃
Min
Typ
Max
Unit
-
33.2
-
℃/W
-
28.7
-
℃/W
-
27.5
-
℃/W
-
0.39
-
℃/W
-
12.3
-
℃/W
Table 7.8 – Thermal Characteristics
Symbol
Parameter
θJA (0 m/s) Thermal resistance from junction to ambient
PS: “(x m/s)” means the air flow velocity
θJA (1 m/s) (JEDEC JESD51-6 moving air, maximum reflow
θJA (2 m/s) temperature for SMT is 255℃~260℃)
ΨJT
θJC
Thermal characterization parameter from
junction-to-top center
(JEDEC JESD51-2 still air, maximum reflow
temperature for SMT is 255℃~260℃)
Thermal resistance from junction to case
(JEDEC JESD51-2 still air, maximum reflow
temperature for SMT is 255℃~260℃)
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 37
GL9711 PCI ExpressTM PIPE x1 PHY
CHAPTER 8
PIPE TIMING CHARACTERISTICS
8.1 Input Setup, Hold Time and Output Timing
Figure 8.1 – Definition of Input Setup and Hold Time
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 38
GL9711 PCI ExpressTM PIPE x1 PHY
Figure 8.2 – Definition of Output Timing
Table 8.1 – Input Setup, Hold Time and Output Timing for 8-bit SDR Mode
Symbol
Parameter
TCYCLE
PCLK cycle time
Duty-H
Duty cycle for PCLK high
Min
Typ
Max
Unit
3.99
4
4.01
ns
35
-
50
%
TIS
Input setup time
-
-
1
ns
TIH
Input hold time
1
-
-
ns
TCO
Clock to output delay
-
2.7
3.2
ns
TOH
Output hold time
1
2.1
-
ns
Table 8.2 – Input Setup, Hold Time and Output Timing for 8-bit DDR Mode
Symbol
Parameter
Min
Typ
Max
Unit
TCYCLE
PCLK cycle time
7.98
8
8.02
ns
TIS
Input setup time
-
-
1.4
ns
TIH
Input hold time
0.5
-
-
ns
TCO
Clock to output delay
-
1.5
1.6
ns
TOH
Output hold time
0.8
1
-
ns
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Page 39
GL9711 PCI ExpressTM PIPE x1 PHY
Table 8.3 – Input Setup, Hold Time and Output Timing for 16-bit Mode
Symbol
Parameter
TCYCLE
PCLK cycle time
Duty-H
Duty cycle for PCLK high
Min
Typ
Max
Unit
7.98
8
8.02
ns
48
-
50
%
TIS
Input setup time
-
-
1.4
ns
TIH
Input hold time
0.5
-
-
ns
TCO
Clock to output delay
-
5.3
5.6
ns
TOH
Output hold time
4.3
4.7
-
ns
Table 8.4 – Input Setup, Hold Time and Output Timing for 10-bit SDR Mode
Symbol
Parameter
TCYCLE
PCLK cycle time
Duty-H
Duty cycle for PCLK high
Min
Typ
Max
Unit
3.99
4
4.01
ns
35
-
50
%
TIS
Input setup time
-
-
1
ns
TIH
Input hold time
1
-
-
ns
TCO
Clock to output delay
-
4
4.2
ns
TOH
Output hold time
3.4
3.7
-
ns
Table 8.5 – Input Setup, Hold Time and Output Timing for 10-bit DDR Mode
Symbol
Parameter
Min
Typ
Max
Unit
TCYCLE
PCLK cycle time
7.98
8
8.02
ns
TIS
Input setup time
-
-
1.4
ns
TIH
Input hold time
0.5
-
-
ns
TCO
Clock to output delay
-
4.1
4.3
ns
TOH
Output hold time
3.5
3.7
-
ns
8.2 Reference Timing Information
Table 8.6 – Reference Timing Information
Symbol
Parameter
Min
Typ
Max
Unit
TRECDET
Time for receiver detection
Timing from de-asserting RST_N to the falling
edge of PHYSTS
Reset Assertion Time to GL9711
-
10
-
us
-
16.7
-
us
10
-
-
us
TPHYSTS-RESET
TRESET
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 40
GL9711 PCI ExpressTM PIPE x1 PHY
CHAPTER 9
PACKAGE DIMENSION
Figure 9.1 - GL9711 233 Pin LFBGA Package
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 41
GL9711 PCI ExpressTM PIPE x1 PHY
CHAPTER 10
ORDERING INFORMATION
Table 10.1 - Ordering Information
Part Number
GL9711-TgGXX
Package
Green
233-pin LFBGA Green Package
©2000-2006 Genesys Logic Inc. - All rights reserved.
Version
Status
XX
Engineering Sample
Page 42