GENLINX ™ GS9002A Serial Digital Encoder FEATURES DEVICE DESCRIPTION • fully compatible with SMPTE-259M serial digital standard The GS9002A is a monolithic bipolar integrated circuit designed to serialize SMPTE 125M and SMPTE 244M bit parallel digital signals as well as other 8 or 10 bit parallel formats. This device performs the functions of sync detection, 9 parallel to serial conversion, data scrambling (using the X + 4 X +1 algorithm), 10x parallel clock multiplication and conversion of NRZ to NRZI serial data. It supports any of four selectable serial data rates from 100 Mb/s to over 360 Mb/s. The data rates are set by resistors and are selected by an on-board 2:4 decoder having two TTL level input address lines. • supports up to four serial bit rates to 400 Mb/s • accepts 8 bit and 10 bit TTL and CMOS compatible parallel data inputs 9 4 • X + X + 1 scrambler, NRZI converter and sync detector may be disabled for transparent data transmission • pseudo-ECL serial data and clock outputs • single +5 or -5 volt supply Other features such as a sync detector output, a sync detector disable input, and a lock detect output are also provided. The 9 4 X + X + 1 scrambler and NRZ to NRZI converter may be bypassed to allow the output of the parallel to serial converter to be directly routed to the output drivers. • 713 mW typical power dissipation (including ECL pull-down loads). • 44 pin PLCC packaging • Pb-free and Green The GS9002A provides pseudo-ECL outputs for the serial data and serial clock as well as a single-ended pseudo-ECL output of the regenerated parallel clock. APPLICATIONS • 4ƒSC, 4:2:2 and 360 Mb/s serial digital interfaces for Video cameras, VTRs, Signal generators The GS9002A directly interfaces with cable drivers GS9007A, GS9008A and GS9009A. The device requires a single +5 volt or -5 volt supply and typically consumes 713 mW of power while driving 100 Ω loads. The 44 pin PLCC packaging assures a small footprint for the complete encoder function. ORDERING INFORMATION Part Number Package Temperature Pb-Free and Green GS9002ACPM 44 Pin PLCC o°C to 70°C No GS9002ACPME3 44 Pin PLCC o°C to 70°C Yes SCRAMBLER/ SERIALIZER SELECT 26 PARALLEL DATA IN (10 BITS) 3 6 SYNC DETECT DISABLE 2:1 MUX 7-16 INPUT LATCH SYNC DETECT 38 39 P/S CONVERTER SYNC DETECT SERIAL DATA SERIAL DATA SCRAMBLER NRZ NRZI 42 PLD SCLK 43 LOCK DETECT PCLK IN LOOP FILTER PCLK OUT PHASE FREQUENCY DETECT 17 CHARGE PUMP 20 29 VCO 22 36 DATA RATE SWITCH 19 DIV BY 10 GENERATOR 35 34 33 32 GS9002A 31 SERIAL CLOCK SERIAL CLOCK LOCK DETECT REGULATOR CAP DRS0 DRS1 RVC00 RVC01 RVC02 RVC03 Patent No.5,357,220 FUNCTIONAL BLOCK DIAGRAM Document No. 24149 - 1 Revision Date: June 2004 GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946 Gennum Japan: Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo 160-0023 Japan Tel: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505 NOT RECOMMENDED FOR NEW DESIGNS DATA SHEET GS9002A - ENCODER DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX 4.75 5.0 5.25 V - 690 870 mW Same as above with SCK/SCK also connected to (V CC-2V) thru 100Ω resistors. - 710 900 mW SDO/SDO connected to (VCC-2V) thru 100ý resistors, PCK OUT connected to VEE via 1kΩ - 155 190 mA - 170 205 mA Supply Voltage VS Operating Range Power Consumption PD SDO/SDO connected to (V CC -2V) thru 100ý resistors, PCK OUT connected to V EE via 1kΩ IS Supply Current Same as above with SCK/SCK to (VCC-2V) V thru 100Ω resistors. UNITS TTL Inputs-HIGH VIHmin TA = 25°C 2.0 - - V TTL Inputs-LOW VILmax TA = 25°C - - 0.8 V Logic Input Current IINmax - 2.5 10 µA TTL Outputs-HIGH VOHmin TA = 25°C 2.4 - - V TTL Outputs-LOW VOLmax TA = 25°C - - 0.5 V IOSYNC Sync Detect O/P Serial Outputs High VOH TA=25°C, RL=100Ω to VCC-2V (SDO & SCK) Low VOL (VCC-2V) - - 4.0 mA -0.875 - -0.7 V -1.8 - -1.5 V NOTES see Figure 15 SINK & SOURCE with respect to V CC GS9002A - ENCODER AC ELECTRICAL CHARACTERISTICS VCC = 5V, V EE = 0V, T A = 0°C to 70°C, V LOOP FILTER =2.6 V unless otherwise shown, PARAMETER Serial Data Outputs (SDO and SDO) Serial Clock Outputs (SCK and SCK) SYMBOL bit rates BRSDO signal swing VSDO rise/fall times tR, tF jitter t J(SDO) frequency ƒSCK signal swing VSCK CONDITIONS MIN TYP RL = 100Ω to (VCC-2 volts) 100 - 400 Mb/s 700 850 1000 mV p-p - 500 - ps 20% - 80% - 400 300 - ps p-p ps p-p see Note 1 see Fig. 16 RL = 100Ω to (VCC-2 volts) 100 - 400 MHz see Fig. 12, 13 - 800 - mV p-p see Fig. 14 Data lags Clock TA = 25°C 143 Mb/s 270 Mb/s MAX UNITS Serial Data to Clock Timing tD See Figure 9 - 1.4 - ns Lock Time tLOCK CLOOP FILT = 0.1µF RLOOP FILT = 3.9kΩ - 1 1.2 ms frequency ƒPCKO RL = 1kΩ to VEE 10 - 40 MHz signal swing VPCKO - 800 - mV p-p rise/fall times tR, tF - 700 - ps - 400 - ps p-p 500 - - ps Parallel Clock Output (PCK OUT) jitter Parallel Data & Clock Inputs risetime t JPCKO tR TA = 25°C setup tSU 3 - - ns hold tHOLD 3 - - ns NOTE 1: Measured using PCK-IN as trigger source on 1GHz analog oscilloscope. 24149 - 1 2 of 11 NOTES ƒPCKO = ƒSCK/10 20% - 80% NOT RECOMMENDED FOR NEW DESIGNS VCC = 5V, V EE = 0V, TA = 0°C to 70°C unless otherwise shown ≤ ABSOLUTE MAXIMUM RATINGS VALUE/UNITS Supply Voltage 5.5 V Input Voltage Range (any input) -VEE < VI < VCC DC Input Current (any one input) 10 mA Power Dissipation (VS = 5.25 V) 1W 0°C ≤ TA ≤ 70°C Operating Temperature Range -65°C ≤ TS ≤ 150°C Storage Temperature Range 260°C Lead Temperature (soldering 10 seconds) SYNC DET. DIS. VCC1 6 PARALLEL DATA INPUTS 5 SYNC DET. VCC3 VEE 4 3 VEE 2 VEE SCK SCK 44 43 42 VCC2a 41 VCC2b 40 PD0 7 39 SDO PD1 8 38 SDO PD2 9 37 VEE PD3 10 36 DRS0 PD4 11 35 DRS1 PD5 12 34 RVC00 PD6 13 33 RVC01 PD7 14 32 RVC02 PD8 15 31 RVC03 PD9 16 30 VEE PCK IN 17 29 C. REG GS9002A TOP VIEW 18 19 20 VEE PCK OUT LOCK DET. 21 22 VCC3 LOOP FILT. 23 24 25 26 VEE NC VEE SSS 27 VEE VCO FREQUENCY SET RESISTORS 28 VCC3 Fig. 1 GS9002A Encoder Pin Connections 3 of 11 24149 - 1 NOT RECOMMENDED FOR NEW DESIGNS PARAMETER GS9002A Serial Digital Encoder - Detailed Device Description Functional blocks within the device include the input latches, sync detector, parallel to serial converter, scrambler, NRZ to NRZI converter, ECL output buffers for data and clock, PLL for 10x parallel clock multiplication and lock detect. The parallel data (PD0-PD9) and parallel clock (PCK-IN) are applied via pins 7 through 17 respectively. VCO Centre Frequency Selection The wide VCO pull range allows the PLL to compensate for variations in device processing, temperature variations and changes in power supply voltage, without external adjustment. A single external resistor is used to set the VCO current for each of four centre frequencies as selected by a two bit code through a 2:4 decoder. The current setting resistors are connected to the RVCO0 through RVCO3 inputs (34, 33, 32 and 31). The decoder inputs DRS0 and DRS1 (36, 35) are TTL compatible inputs and select the four resistors according to the following truth table. Sync Detector DRS1 The Sync Detector looks for the reserved words 000-003 and 3FC-3FF, in ten bit Hex, or 00 and FF in eight bit Hex, used in the TRS-ID sync word. When the occurrence of either all zeros or ones at inputs PD2-PD9 is detected, the lower two bits PD0 and PD1 are forced to zeros or ones, respectively. This makes the system compatible with eight or ten bit data. For non SMPTE standard parallel data, a logic input, Sync Disable (6) is available to disable this feature. Scrambler The Scrambler is a linear feedback shift register used to pseudo-randomize the incoming serial data according to the fixed polynomial (X9+X4+1). This minimizes the DC component in the output serial data stream. The NRZ to NRZI converter uses another polynomial (X+1) to convert a long sequence of ones to a series of transitions, minimizing polarity effects. Phase Locked Loop The PLL performs parallel clock multiplication and provides the timing signal for the serializer. It is composed of a phase/frequency detector, charge pump, VCO and a divide-by-ten counter. The phase/frequency detector allows a wider capture range and faster lock time than that which can be achieved with a phase discriminator alone. The discrimination of frequency also eliminates harmonic locking. With this type of discriminator, the PLL can be over-damped for good stability without sacrificing lock time. The charge pump delivers a 'charge packet' to the loop filter which is proportional to the system phase error. Internal voltage clamps are used to constrain the loop filter voltage between approximately 1.8 and 3.4 volts. Resistor Selected 0 0 RVCO0 (34) 0 1 RVCO1 (33) 1 0 RVCO2 (32) 1 1 RVCO3 (31) A 2:1 multiplexer (MUX) selects either the direct data from the P/S Converter (Serializer) or the NRZI data from the Scrambler. This MUX is controlled by the Scrambler/Serializer Select (SSS) input pin 26. When this input is LOW the MUX selects the Scrambler output. (This is the mode used for SMPTE 259M data). When this input is HIGH the MUX directly routes the serialized data to the output buffer with no scrambling or NRZ to NRZI conversion. The lock detect circuit disables the serial data output when the loop is not locked by turning off the 2:1 MUX. The Lock Detect output is available from pin 20 and is HIGH when the loop is locked. The true and complement serial data, SDO and SDO are available from pins 38 and 39 while the true and complement serial clock, SCK and SCK are available from pins 43 and 42 respectively. If the serial clock is not used pins 43 and 42 can be connected to VCC. The regenerated parallel clock (PCK OUT) is available at pin 19. This output is a single ended pseudo-ECL output requiring a pull down resistor. If regenerated parallel clock is not used pin 19 can be connected to VCC. The VCO, constructed from a current-controlled multivibrator, features operation in excess of 400 Mb/s and a wide pull range (≈±40% of centre frequency). 24149 - 1 DRS0 4 of 11 NOT RECOMMENDED FOR NEW DESIGNS The GS9002A Encoder is a bipolar integrated circuit used to convert parallel data into a serial format according to the SMPTE 259M standard. The device encodes both eight and ten bit TTL-compatible parallel signals producing serial data rates up to 400 Mb/s. It operates from a single five volt supply and is packaged in a 44 pin PLCC. GS9002A PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION 1 VEE Power Supply: Most negative power supply connection. 2 VCC3 Power Supply: Most positive power supply connection for the PLL and scrambler. 3 SYNC DET. 4 VEE Power Supply: Most negative power supply connection. 5 VCC1 Power Supply: Most positive power supply connection for the input data latches and serializer. 6 SYNC DET. DISABLE I TTL level input that disables the internal Sync Detector when HIGH. This allows the GS9002 to serialize 8 or 10 bit non - SMPTE Standard parallel data. 7-16 PD0-PD9 I TTL level inputs of the parallel data words. PD0 is the LSB and PD9 is the MSB. 17 PCK-IN I TTL level input of the Parallel Clock. 18 VEE 19 PCK OUT 20 21 22 LOCK DET. O Power Supply: Most negative power supply connection. O Pseudo-ECL output representing the re-clocked Parallel Clock and is derived from the internal VCO. The VCO is divided by 10 in order to produce this output. O TTL level output which goes HIGH when the internal PLL is locked. VCC3 LOOP FILT. TTL output level that detects the occurrence of all zero’s or all one’s at inputs PD2-PD9 and pulses LOW for three PCK-IN durations. Used to detect SMPTE 259M reserved words (000-003 and 3FC-3FF) in TRS sync word. Parallel data bits PD0 and PD1 are set Low or High when PD2 - PD9 are Low or High respectively. Power Supply: Most positive power supply connection for the PLL and scrambler. I Connection for the R-C loop filter components. The loop filter sets the PLL loop parameters. Power Supply: Most negative power supply connection. 23 VEE 24 NC 25 VEE 26 SSS 27 VEE Power Supply: Most negative power supply connection. 28 VCC3 Power Supply: Most positive power supply connection for the PLL and scrambler. 29 CREG 30 VEE 31 RVCO3 I VCO Resistor 3: Analog current input used to set the centre frequency of the VCO when the two Data Rate Select bits (pins 35 and 36) are both set to logic 1. A resistor is connected from this pin to VEE. 32 RVCO2 I VCO Resistor 2: Analog current input used to set the centre frequency of the VCO when the Data Rate Select Bit 0 (pin 36) is set to logic 0 and the Data Rate Select Bit 1 (pin 35) is set to logic 1. A resistor is connected from this pin to VEE. 33 RVCO1 I VCO Resistor 1: Analog current input used to set the centre frequency of the VCO when the Data Rate Select Bit 0 (pin 36) is set to logic 1 and the Data Rate Select Bit 1 (pin 35) is set to logic 0. A resistor is connected from this pin to VEE. 34 RVCO0 I VCO Resistor 0: Analog current input used to set the centre frequency of the VCO when the two Data Rate Select bits (pins 35 and 36) are both set to logic 0. A resistor is connected from this pin to VEE. 35,36 DRS0, 1 I TTL level inputs to the internal 2:4 demultiplexer used to select one of four VCO frequency setting resistors (RVCO0 - RVCO3). (See above) Power Supply: Most negative power supply connection. I I Scrambler/Serializer Select. TTL level input that selects scrambled NZRI output when logic LOW or direct serializer output when logic HIGH. Compensation RC network for internal voltage regulator that requires decoupling with a series 0.1µF capacitor and 820Ω resistor. Components should be located as close as possible to the pin. Power Supply: Most negative power supply connection. 5 of 11 24149 - 1 NOT RECOMMENDED FOR NEW DESIGNS PIN NO. GS9002A PIN DESCRIPTIONS (Continued) SYMBOL 37 VEE 38,39 SDO/SDO TYPE DESCRIPTION Power Supply: Most negative power supply connection. O Serial Data Outputs (true and inverse). Pseudo-ECL differential outputs representing the serialized data. These outputs require 390Ω pull down resistors. 40 VCC2b Power Supply: Most positive power supply connection for the Serial Data ECL output buffers. 41 VCC2a Power Supply: Most positive power supply connection for the Serial Clock ECL output buffers. 42,43 SCK/SCK O Serial Clock Outputs (inverse and true). Pseudo-ECL differential outputs of the Serial Clock (10x Parallel Clock). These outputs require 390Ω pull-down resistors. 44 VEE Power Supply: Most negative power supply connection. INPUT / OUTPUT CIRCUITS VCC VCC 5k 1k 1k INPUT SYNC DET VR1 VEE VEE Fig. 2 Pin No. 3 Sync Detect Fig. 3 Pins No. 6, 7 - 16, 17,26 Sync Disable, Parallel Data, Parallel Clock, Scrambler/Serializer Select VCC VCC VCC 1k 1k 10k PCK OUT LOCK DETECT VEE VEE Fig. 5 Pin No. 20 Lock Detect Fig. 4 Pin No. 19 Parallel Clock Out 24149 - 1 6 of 11 NOT RECOMMENDED FOR NEW DESIGNS PIN NO IVCO VCC VCC DRS0 800 DRS1 RVCOX VR1 VEE Fig. 7 Pins No. 31 - 34 Frequency Setting Registors RVCO0-RVCO3 VEE Fig. 6 Pins No. 35, 36 Data Rate Select VCC 200 200 SDO SDO VEE Fig. 8 Pins No. 38, 39, 42, 43 Serial Outputs (Data & Clock) tCLKL = tCLKH 50% PARALLEL CLOCK PLCK PARALLEL DATA PDn SERIAL DATA OUT (SD0) SERIAL CLOCK OUT (SCK) tSU tD tD 50% 50% tHOLD Fig. 9 Waveforms 7 of 11 24149 - 1 NOT RECOMMENDED FOR NEW DESIGNS VR2=2.15V VSELECT 4ƒsc T R S T R S ACTIVE VIDEO & H BLANKING T R S ACTIVE VIDEO & H BLANKING SYNC DETECT 4:2:2 DATA STREAM E A V H BLNK S A V E A V ACTIVE VIDEO H BLNK S A V 000 000 SYNC DETECT PCLK IN PDN XXX 3FF 000 000 XXX ••• ••• XXX 3FF XXX ••• SYNC DETECT Fig. 10 Timing Diagram +5V LOOP LOCKED L.E.D. +10 2N4400 0.1 330 82 10k +5V 20 7 DATA 0 DATA 1 8 DATA 2 9 DATA 4 DATA 5 DATA 6 DATA 7 DATA 9 SSS 6 2,5,21,28,40,41 SYNC (6x VCC) DIS. 100 10k 10k 100 100 100 38 PDI DATA SDO PD2 39 DATA SDO 43 CLOCK SCK GS9002A SCK 42 CLOCK +5V 1M 17 PCK IN 36 DRS0 *150 *10p DATA RATE SELECT DIP SWITCH (SEE TRUTH TABLE, FIG. 2) LOCK DET. 26 15 PD8 16 PD9 DATA 8 CLOCK PD0 10 PD3 11 PD4 12 PD5 13 PD6 14 PD7 DATA 3 6x100n 5k 19 PCK-OUT 35 DRS1 22 LOOP FILT 29 CREG RVCO1 RVCO2 RVCO3 RVCO4 VEE 34 33 32 31 1,4 18,23 0.1 25,27 30,37 1 2 3 4 44 820 4x0.1 PARALLEL CLOCK OUT 0.1 3.9k 1k COMMON +5V NOTES: Resistors 1, 2, 3 and 4 are used to set the VCO centre frequency. For 143/177 Mb/s ≈ 6kΩ, 270 Mb/s ≈ 2.7kΩ, 360 Mb/s ≈ 1.8kΩ All resistors in ohms, all capacitors in microfarads unless otherwise stated. represent test points. * This RC network is used to slow down fast PCLK risetimes ( ≤ 500ps). It is not required if risetimes exceed 500ps. Fig. 11 GS9002A Test Circuit 24149 - 1 8 of 11 NOT RECOMMENDED FOR NEW DESIGNS DATA STREAM 600 550 550 500 500 450 450 FREQUENCY (MHz) 600 400 350 300 V =2.6V LOOP 250 200 OPTIMAL LOOP FILTER VOLTAGE RVCO = 1.8k 400 350 300 RVCO = 2.7k 250 200 150 150 RVCO = 6.3k 100 100 50 50 0 0 1 2 3 4 5 6 7 8 9 10 1.8 2.0 FREQUENCY SETTING RESISTANCE (ký) 2.2 2.4 2.6 2.8 3.0 3.2 3.4 LOOP FILTER VOLTAGE (V) Fig. 12 VCO Frequency Fig. 13 VCO Frequency vs Loop Filter Voltage 1000 200 V = 5.25V V = 5.25V S 950 S 900 V = 5.0V CURRENT (mA) SERIAL OUTPUT (mV) 190 S 850 800 V = 4.75V S 750 V = 5.0V S 180 170 V = 4.75V S 160 700 0 10 20 30 40 50 60 150 70 0 10 20 30 40 50 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) Fig. 14 Serial Output Level (Data & Clock) Fig. 15 Supply Current 60 70 800 700 JITTER p-p (ps) 600 500 143 Mb/s 400 270 Mb/s 300 200 100 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 LOOP FILTER VOLTAGE (V) Fig. 16 Output Jitter 9 of 11 24149 - 1 NOT RECOMMENDED FOR NEW DESIGNS VCO FREQUENCY (MHz) TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25° C unless otherwise shown) 10 of 11 100 100 100 100 100 100 100 10k 10pF 10k +5V 9 100 PD2 PDI PD0 LOOP FILT PCK-OUT SCK SCK SDO SDO 4x0.1 820 1 2 3 4 25,27 30,37 44 22 19 42 43 39 38 3.9k 0.1 390 2,5,21,28,40,41 SYNC (6x VCC) DIS. 6 GS9002A SSS 26 6x100n 10 CREG RVCO0 RVCO1 RVCO2 RVCO3 VEE 34 33 32 31 1,4 0.1 18,23 36 DRS0 35 DRS1 29 20 5k LOCK DET. 16 PD9 17 PCK IN 10 PD3 11 PD4 12 PD5 13 PD6 14 PD7 15 PD8 8 100 100 7 *100 10k 2N4400 + 1k 180 100 1M +5V 390 0.1 47 47 100 100 18p 6 7 0.1µ 27 SER . IN SER. IN Fig. 17 GENLINX ™ Serial Digital Chipset GS9002/7A Application Circuit NOTES: Resistors 1, 2, 3 and 4 are used to set the VCO centre frequency. See Figures 12 and 13. All resistors in ohms, all capacitors in microfarads unless otherwise stated. represent test points. * These resistors are used to slow down fast INPUT edges ( ≤500ps ) and prevent the input signals from ringing below the VEE rail. DATA RATE SELECT DIP SWITCH (SEE TRUTH TABLE) CLOCK DATA 9 DATA 8 DATA 7 DATA 6 DATA 5 DATA 4 DATA 3 DATA 2 DATA 1 DATA 0 +5V 330 LOOP LOCKED L.E.D. 4x150 OUT 2 4 1 0 1 0 1 1 3 2 1 0 RVCO NO. DATA RATE SELECT TRUTH TABLE 0 DRS0 0 DRS1 0.1 2 1 OUT 2 3 OUT 1 OUT 1 PARALLEL CLOCK T.P. 5 VEE CABLE DRIVER GS9007A VCC 8 + 10 1.0 68 1.0 68 68 1.0 1.0 68 1p8 1p8 This signal is 12dB below actual SCK level and is used for test purposes 1p8 SERIAL CLOCK (50Ω) SDO2 (75Ω) SDO2 (75Ω) 1p8 SDO1 (75Ω) SDO1 (75Ω) +5V NOT RECOMMENDED FOR NEW DESIGNS 24149 - 1 APPLICATION CIRCUIT DOCUMENT IDENTIFICATION PRODUCT PROPOSAL This data has been compiled for market investigation purposes only, and does not constitute an offer for sale. ADVANCE INFORMATION NOTE This product is in development phase and specifications are subject to change without notice. Gennum reserves the right to remove the product at any time. Listing the product does not constitute an offer for sale. REVISION NOTES Added lead-free and green information. For latest product information, visit www.gennum.com PRELIMINARY The product is in a preproduction phase and specifications are subject to change without notice. CAUTION ELECTROSTATIC DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright March 1991 Gennum Corporation. All rights reserved. Printed in Canada. 11 of 11 24149 - 1 NOT RECOMMENDED FOR NEW DESIGNS Figure 17 shows a typical application circuit of the GS9002A driving a GS9007A cable driver.