ETC GS9000B

GENLINX™ GS9000B
Serial Digital Decoder
DATA SHEET
•
fully compatible with SMPTE 259M
•
decodes 8 and 10 bit serial digital signals for data
rates to 370 Mb/s
The GS9000B is a CMOS integrated circuit specifically
designed to deserialize SMPTE 259M serial digital signals
at data rates to 370 Mbps.
•
pin and function compatible with GS9000S and
GS9000
•
250 mW power dissipation at 270 MHz clock rates
•
incorporates an automatic standards selection
function with the GS9005A Receiver or GS9015A
Reclocker
•
operates from single +5 or -5 volt supply
•
enables an adjustment-free Deserializer system
when used with GS9010A and GS9005A or GS9015A
•
28 pin PLCC packaging
The device incorporates a descrambler, serial to parallel
convertor, sync processing unit, sync warning unit and
automatic standards select circuitry.
Differential pseudo-ECL inputs for both serial clock and
data are internally level shifted to CMOS levels. Digital
outputs such as parallel data, parallel clock, HSYNC, Sync
Warning and Standard Select are all TTL compatible.
APPLICATIONS
•
4ƒSC, 4:2:2 and 360 Mb/s serial digital interfaces
•
Automatic standards select controller for serial routing
and distribution applications using GS9005A Receiver
or GS9015A Reclocker
The GS9000B is designed to directly interface with the
GS9005A Reclocking Receiver to form a complete
SMPTE-serial-in to CMOS level parallel-out deserializer.
The GS9000B may also be used with the GS9010A and the
GS9005A to form an adjustment-free receiving system
which automatically adapts to all serial digital data rates.
The GS9015A can replace the GS9005A in GS9000B
applications where cable equalization is not required.
The GS9000B is packaged in a 28 pin PLCC and operates
from a single 5 volt, ± 5% power supply.
GS9000B
SERIAL DATA IN
SERIAL DATA IN
SERIAL CLOCK IN
5
6
LEVEL
SHIFT
DESCRAMBLER
30 - BIT
SHIFT REG
7
8
SERIAL CLOCK IN
LEVEL
SHIFT
SYNC DETECT
(3FF 000 000 HEX)
ICLK
Sync
SYNC CORRECTION
ENABLE
PARALLEL DATA
OUT (10 BITS)
SP
14
Word
Boundary
PARALLEL
TIMING
GENERATOR
PARALLEL CLOCK
OUT
SYNC CORRECTION
Sync Error
HSYNC OUTPUT
SYNC WARNING
CONTROL
SYNC WARNING
(Schmitt Trigger
Comparator)
15
SYNC WARNING
FLAG
AUTO STANDARD SELECT
STANDARDS SELECT
CONTROL
11
OSC
SS0
2 BIT
COUNTER
SS1
Hsync Reset
FUNCTIONAL BLOCK DIAGRAM
Revision Date: December 1999
Document No. 521- 79 - 01
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
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Gennum Japan
Corporation A-302
Miyamae
Village,
2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan
tel. (03) 3334-7700
fax (03) 3247-8839
NOT RECOMMENDED FOR NEW DESIGNS
DEVICE DESCRIPTION
GS9000B
FEATURES
GS9000B DECODER - DC ELECTRICAL CHARACTERISTICS
VDD = 5V, TA = 0°C to 70°C unless otherwise shown
GS9000B
PARAMETER
SYMBOL
MIN
Supply Voltage
VS
Operating Range
Power Consumption
PC
ƒ = 270 MHz (see Fig. 8)
Input Resistance
RIN
Input Capacitance
CIN
CMOS Input Voltage
o
VIHMIN
TA = 25 C
VILMAX
Output Voltage
NOT RECOMMENDED FOR NEW DESIGNS
CONDITIONS
Input Leakage Current
o
TYP
MAX
UNITS
4.75
5.00
5.25
V
-
250
-
mW
-
10
-
MΩ
-
5
10
pF
3.4
-
-
V
-
-
1.5
V
2.4
4.5
-
V
VOHMIN
TA = 25 C
VOL MAX
IOH = 4 mA
-
0.2
0.5
V
IIN
VIN = VDD or VSS
-
-
± 10
µA
NOTES
Serial Clock & Data Inputs
Signal Swing
V IN
700
800
1000
mV p-p
Signal Offset
V INOS
3.0
-
4.2
V
centre
of swing
TYP
MAX
UNITS
NOTES
GS9000B DECODER - AC ELECTRICAL CHARACTERISTICS
VDD = 5V, TA = 0°C to 70°C unless otherwise shown
PARAMETER
SYMBOL
Serial Input Clock Frequency
ƒSCI
100
370
MHz
Serial Input Data Rate
DRSDI
100
370
Mb/s
Serial Data & Clock Inputs:
CONDITIONS
MIN
TA = 25°C
Risetime
tR
Setup
TCLKL
-
-
1.0
ns
tSU
1.0
-
-
ns
Hold
tHOLD
1.0
-
-
ns
Parallel Clock: Jitter
tJCLK
TA = 25°C
-
1.0
-
ns p-p
Parallel Data: Risetime
tR-PDn
TA = 25°C, CL = 10pF
-
1.0
-
ns
20% to 80%
PDn to PCLK delay tolerance
tD
-
-
±3
ns
rising edge of
PCLK to bit
period centre
ORDERING INFORMATION
PART NUMBER
PACKAGE
ABSOLUTE MAXIMUM RATINGS
PARAMETER
TEMPERATURE
GS9000BCPJ
28 Pin PLCC
O°C to 70°C
GS9000BCTJ
28 Pin PLCC Tape
O°C to 70°C
Supply Voltage (V =VDD-V )
s
ss
Input Voltage Range (any input)
DC Input Current (any one input)25 mW
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
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VALUE/UNITS
7V
-0.3 to (VDD+0.3) V
± 10 µA
400 mW
0°C to 70°C
-65°C to +150°C
260°C
VSS
4
(MSB)
SWF VSS HSYNC PD9
3
2
28
PD8
VSS
27
26
25
PD7
SD1
6
24
PD6
SC1
7
23
PD5
SC1
8
22
PD4
SS1
9
21
PD3
SS0
10
20
PD2
SSC
11
19
PD1
GS9000B
TOP VIEW
12
13
14
VDD
VDD
SCE
15
16
SWC PCLK
17
18
PD0 VDD
(LSB)
Fig. 1 GS9000B Pin Outs, 28 Pin PLCC Package
GS9000B PIN DESCRIPTIONS
PIN NO.
SYMBOL
TYPE
DESCRIPTION
1
HSYNC
Output
2
VSS
3
SWF
4
VSS
5,6
SDI/SDI
Inputs
Differential, pseudo-ECL serial data inputs. ECL voltage levels with offset of 3V to 4.2V
for operation up to 370 MHz. See AC characteristics for details.
7,8
SCI/SCI
Inputs
Differential, pseudo-ECL serial clock inputs. ECL voltage levels with offset of 3V to 4.2V
for operation up to 370 MHz. See AC characteristics for details.
9,10
SS1/SS0
Output
Standard Select Outputs. CMOS (TTL compatible) outputs used with the GS9005A Receiver in
order to perform an automatic standards select function. These outputs are generated by a 2 bit
internal binary counter which stops cycling when there is no CARRIER present at the GS9005A
Receiver input or when a valid TRS is detected by the GS9000B.
11
SSC
Input
Standards Select Control. Analog input used to set a time constant for the standards select hunt
period. An external RC sets the time constant. When a GS9005A Receiver is used, the open
collector CARRIER DETECT output also connects to this pin in order to enable or disable the
internal 2 bit binary counter which controls the hunting process.
12
VDD
Power Supply. Most positive power supply connection.
13
VDD
Power Supply. Most positive power supply connection.
14
SCE
Horizontal Sync Output. CMOS (TTL compatible) output that toggles for each TRS detected.
Power Supply. Most negative power supply connection.
Output
Sync Error Warning Flag. CMOS (TTL compatible) active high output that indicates the
preselected HSYNC Error Rate (HER). The HER is set with an RC time constant on the
SWC input.
Power Supply. Most negative power supply connection.
Input
Sync Correction Enable. Active high CMOS input which enables sync correction by not resetting
the GS9000B’s internal parallel timing on the first sync error. If the next incoming sync is in error,
internal parallel timing will be reset. This is to guard against spurious HSYNC errors. When SCE
is low, a valid sync will always reset the GS9000B’s parallel timing generator.
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NOT RECOMMENDED FOR NEW DESIGNS
5
GS9000B
SD1
GS9000B PIN DESCRIPTIONS
NOT RECOMMENDED FOR NEW DESIGNS
GS9000B
PIN NO.
SYMBOL
TYPE
DESCRIPTION
15
SWC
Input
Sync Warning Control. Analog input used to set the HSYNC Error Rate (HER). This is
accomplished by an external RC time constant connected to this pin.
16
PCLK
Output
Parallel Clock Output. CMOS (TTL compatible) clock output where the rising edge of the clock is
located at the centre of the parallel data window within a given tolerance. See Fig. 2.
17
PD0
Output
Parallel Data Output - Bit 0 (LSB). CMOS (TTL compatible) descrambled parallel data output from the
serial to parallel convertor representing the least significant bit (LSB).
18
VDD
19 - 25
PD1 - PD7
26
VSS
27
PD8
Output
Parallel Data Output. CMOS (TTL compatible) descrambled parallel data output from the serial to
parallel convertor representing data bit 8.
28
PD9
Output
Parallel Data Output - Bit 9 (MSB). CMOS (TTL compatible) descrambled data output from the serial
to parallel convertor representing the most significant bit (MSB).
Power Supply. Most positive power supply connection.
Outputs
Parallel Data Outputs - Bit 1 to Bit 7. CMOS (TTL compatible) descrambled parallel data outputs from
the serial to parallel convertor representing data bit 1 through data bit 7.
Power Supply. Most negative power supply connection.
VDD
INPUT / OUTPUT CIRCUITS
VDD
VDD
VDD
SDI
VDD
SCI
REXT
SSC
BIAS
SCE
VDD
EXTERNAL
COMPONENTS
SDI
SCI
Fig. 3 Pin 14 SCE
Fig. 2 Pin 11 SSC
Fig. 4 Pins 5 - 8 SDI - SCI
VDD
VDD
VDD
REXT
SWC
6800
CEXT
OUTPUT
EXTERNAL
COMPONENTS
GND
Fig. 5 Pin 15 SWC
Fig. 6 Pins 3, 16, 17, 19 - 25, 27, 28
SWF, HSYNC, SSI, SSD, PCLK, PD0-9
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1/
2
tCLKL = tCLKH
1/
2
50%
tD
Fig. 7 Waveforms
TEST SET-UP & APPLICATION INFORMATION
In order to maintain very short interconnections when interfacing
with the GS9005A Receiver, the critical high speed inputs
such as Serial Data (pins 5 and 6) and Serial Clock (pins 7 and
8) are located along one side of the device package.
Figure 9 shows the test set-up for the GS9000B operating from
a VDD supply of +5 volts. The differential pseudo ECL inputs for
DATA and CLOCK (pins 5,6,7 and 8) must be biased between
+3 and +4.2 volts. In the circuit shown, these inputs with the
resistor values shown, can be directly driven from the outputs
of the GS9005A Reclocking Receiver.
If the automatic standard select function is not used, the
Standard Select bits (pins 9 and 10) do not need to be
connected, however the control input (pin 11) should be
grounded.
In other cases, such as true ECL level driver outputs, two
biasing resistors are needed on the DATA and CLOCK inputs
and the signals must be AC coupled.
It is critical that the decoupling capacitors connected to pins
12,13 and 18 be chip types and be located as close as
possible to the device pins.
TYPICAL PERFORMANCE CURVES
(VS = 5V, TA = 25° C unless otherwise shown)
500
300
POWER (mW)
200
100
10
1
10
100
500
FREQUENCY (MHz)
Fig. 8 Power Consumption
5
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NOT RECOMMENDED FOR NEW DESIGNS
tHOLD
GS9000B
PARALLEL
CLOCK
(PCLK)
SERIAL
DATA
(SDI)
tSU
t
PARALLEL
DATA
(PDn)
50%
SERIAL
CLOCK
(SCI)
t
** Locate the three 0.22µF decoupling
capacitors as close as possible to the
corresponding pins on the GS9000B.
Chip capacitors are recommended.
+5V
100nF
82Ω
3x0.22µF
HSYNC OUTPUT
GS9000B
(+3V)
**
12
4x100Ω
5
SDI IN
6
SDI IN
7
SCI IN
8
NOT RECOMMENDED FOR NEW DESIGNS
SCI IN
9
STANDARDS SELECT BIT 1
STANDARDS SELECT BIT 0
13
18
1
VDD VDD VDD HSYNC
17
PD0
10
*11
* This pin receives a CARRIER DETECT
signal from the GS9005A Receiver.
When the line is LOW, the internal
counter is stopped and the outputs
SS0 and SS1 retain their logic levels
SDI
DECODER
GS9000B
PDI
PD2
SDI
PD3
SCI
PARALLEL DATA BIT 1
20
PARALLEL DATA BIT 2
21
PARALLEL DATA BIT 3
22
PD4
SCI
PD5
SS1
PD6
SS0
SSC
26 15
PARALLEL DATA BIT 5
24
PARALLEL DATA BIT 6
PARALLEL DATA BIT 7
27
PD8
PARALLEL DATA BIT 8
PD9 28
PARALLEL DATA BIT 9
SCE
VSS VSS VSS SWC SWF
4
PARALLEL DATA BIT 4
23
25
PD7
PCLK
2
PARALLEL DATA BIT 0
19
16
PARALLEL CLOCK OUT
14
SYNC CORRECTION ENABLE
3
SYNC WARNING FLAG
22nF
500kΩ
SYNC WARNING FLAG CONTROL TIME CONSTANT
+5V
Fig. 9 GS9000B Test Set-Up
4ƒsc
DATA
STREAM
With correctly synchronized serial data and clock connected
to the GS9000B, the HSYNC output (pin 1) will toggle for each
HSYNC detected. The Parallel Data bits PD0 through PD9
along with the Parallel Clock can be observed on an
oscilloscope or fed to a logic analyzer. These outputs can also
be fed through a suitable TTL to ECL converter to directly drive
parallel inputs to receiving equipment such as monitors or
digital to analog converters.
T
R
S
ACTIVE VIDEO
& H BLANKING
T
R
S
T
R
S
ACTIVE VIDEO
& H BLANKING
HSYNC
OUT
4:2:2
E
A
V
DATA
STREAM
In operation, the HSYNC output from the GS9000B decoder
toggles on each occurrence of the timing reference signal
(TRS). The state of the HSYNC output is not significant, just the
time at which it toggles.
H
BLNK
S
A
V
E
A
V
ACTIVE
VIDEO
H
BLNK
S
A
V
HSYNC
OUT
The HSYNC output toggles to indicate the presence of the
TRS on the falling edge of PCLK, one data symbol prior to the
output of the first word in the TRS. In the following diagram,
data is indicated in 10 bit Hex.
PCLK
PDN
HSYNC
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XXX
3FF
000
000 XXX
•••
XXX
3FF
000
000
XXX
•••
SWF
SSI
VCC
0.1µ
10µ
+
DVCC
+5V
VCC
+5V
100
3.3k
100
0.1µ
+
DGND
22
100
8
V
SS1 21 CC
SS0 20
390
9
390
10
VCC3
CD
19
11
VSS
PD8
PD9
VSS
100
24
100
23
100
22
100
21
100
20
100
PD1 19
100
PD7
PD6
SDI
PD5
SCI
PD4
GS9000B
SCI
PD3
SS1
PD2
SS0
SST
DVCC
VCC
PARALLEL DATA BIT 8
25
12 13 14 15 16
VDD
7
PARALLEL DATA BIT 9
28 27 26
PDO
100
HSYNC
23
SDI
1
PCLK
6
SCO
RVCO3
EYEOUT
RVCO2
VSS
100
SWF
24
2
SCE
VCC4
SSI
VEE2
A/D
AGC
VEE1
VCC1
5
12 13 14 15 16 17 18
5.6p
(1)
100
3
17
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
DVCC
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
18
SYNC CORRECTION ENABLE
0.1µ
113
(2)
0.1µ
910
100
100
DGND
10n
DGND
1.2k
DVCC
VCC
1.2k
(3)
0.1µ
68k
50k
22n
VCC
120
STAR
ROUTED
DGND
GS9010A
6.8µ
+
1
(2)
6.8µ
2
+
3
4
3.3n 5
VCC
P/N
OUT
INCOMP
STDT
VCC
CD
HSYNC
LF
GND
6
ƒ/2
OSC
7
VCC
DLY
8
SWF
FVCAP
16
0.1µ
15
14
13
VCC
12
11
10
STANDARD TRUTH TABLE
100k
9
82n
(2)
0.68µ
VCC
0.1µ
SWF
180n
ƒ/2
P/N
STANDARD
0
0
4:2:2 - 270
0
1
4:2:2 - 360
1
0
4ƒsc - NTSC
1
1
4ƒsc - PAL
(1) Typical value for input return loss matching
(2) To reduce board space, the two anti-series 6.8µF capacitors (connected across pins 2 and 3 of the GS9010A)
may be replaced with a 1.0 µF non-polarized capacitor provided that:
(a) the 0.68 µF capacitor connected to the OSC pin (11) of the GS9010A is replaced with a 0.33 µF capacitor and
(b) the GS9005A /15A Loop Filter Capacitor is 10nF.
(3) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
Fig. 10 Application Circuit - Adjustment Free Multistandard Serial to Parallel Convertor
GS9000B, GS9005A and GS9010A INTERCONNECTIONS
Figure 10 shows an application of the GS9000B in an
adjustment free, multi-standard serial to parallel convertor.
This circuit uses the GS9010A Automatic Tuning Sub-system
IC and a GS9005A Serial Digital Receiver. The GS9005A may
be replaced with a GS9015A Reclocker IC if cable equalization
is not required.
The GS9010A ATS eliminates the need to manually set or
externally temperature compensate the Receiver or Reclocker
VCO. The GS9010A can also determine whether the
incoming data stream is 4ƒsc NTSC,4ƒsc PAL or component
4:2:2.
The GS9010A includes a ramp generator/oscillator which
repeatedly sweeps the Receiver/Reclocker VCO frequency
over a set range until the system is correctly locked. An
automatic fine tuning (AFT) loop maintains the VCO control
voltage at it's centre point through continuous, long term
adjustments of the VCO centre frequency.
During normal operation, the GS9000B Decoder provides
continuous HSYNC pulses which disable the ramp/oscillator
of the GS9010A. This maintains the correct Receiver/
Reclocker VCO frequency. When an interruption to the
incoming data stream is detected by the Receiver/Reclocker,
the Carrier Detect goes LOW and tri-states the AFT loop in
order to maintain the correct VCO frequency for a period of
about 2 seconds. This allows the Receiver/Reclocker to
rapidly relock when the signal is re-established.
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521 - 79 - 01
NOT RECOMMENDED FOR NEW DESIGNS
75
22n
GS9005A
9 SDI
10 ƒ/2
VEE3
25
SDO
8 SDI
11
390
SCO
VCC2
4
28 27 26
DDI
RVCO1
47p
7
1
SDO
RVCO0
75
47p
6
2
DDI
LOOP
0.1µ
5
3
GS9000B
VCC
390
4
SYNC WARNING FLAG
HSYNC OUTPUT
DGND
SWC
DGND
ECL
DATA
INPUT
INPUT
INPUT SELECTION
0.1µ
0.1µ
GND
100
DGND
VCC
VCC
VDD
10µ
VDD
10µ
+
NOT RECOMMENDED FOR NEW DESIGNS
GS9000B
SYNC WARNING FLAG OPERATION
Each time HSYNC is not correctly detected, the Sync Warning
Flag output (pin 3 ) will go HIGH. The RC network connected
to the Sync Warning Control input (pin 15) sets the number
of sync errors that will cause the SWF pin to go HIGH. The
component values of the RC network shown in Figure 10 set
the SWF error rate to approximately one HSYNC error in 10
lines. These component values are chosen for optimum
performance of the SWF pin, and should not be adjusted.
VDD
COMPARATOR
15
VDD
SYNC
6.8k
WARNING
+
SYNC
3 WARNING
FLAG
(SWF)
CONTROL
SYNC
ERROR
Typically, HSYNC errors will become visible on a monitor
before the SWF will provide an indication of HSYNC errors. As
a result, the SWF function can be used in applications where
the detection of significant signal degradation is desired.
Fig. 11 Sync Warning Flag Circuit
A high SWF will go low as soon as the input error rate
decreases below the set rate. This response time is determined
by C, as mentioned earlier. A small amount of hysterisis in the
comparator ensures noise immunity.
REVISION NOTES:
Added Not Recommended watermark to all pages.
CAUTION
DOCUMENT IDENTIFICATION:
ELECTROSTATIC
DATA SHEET
The product is in production. Gennum reserves the right to
make changes at any time to improve reliability, function or
design, in order to provide the best product possible.
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright January 1997 Gennum Corporation. All rights reserved. Printed in Canada.
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