GENLINX™ GS9015A Serial Digital Reclocker DATA SHEET FEATURES DEVICE DESCRIPTION • reclocking of SMPTE 259M signals • operational to 400 Mb/s • adjustment free reclocker when used with the GS9000B or GS9000S decoder and GS9010A Automatic Tuning Sub-system The GS9015A is a monolithic IC designed to receive SMPTE 259M serial digital video signals. This device performs the function of data and clock recovery. It interfaces directly with the GENLINX ™ GS9000B or GS9000S Decoder. • While there are no plans to discontinue the GS9015A, Gennum has developed a successor product with improved features and performance called the GS9035. The GS9035 is recommended for new designs. 28 pin PLCC packaging APPLICATIONS The VCO centre frequencies are controlled by external resistors which can be selected by applying a two bit binary code to the Standards Select input pins. Alternatively, the GS9015A can be used with the GS9010A to form an adjustment free reclocker system. • 4ƒSC, 4:2:2 and 360 Mb/s serial digital interfaces ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE GS9015ACPJ 28 Pin PLCC 0O C to 70O C GS9015ACTJ 28 Pin PLCC Tape 0O C to 70O C The GS9015A is packaged in a 28 pin PLCC operating from a single +5 or -5 volt supply. SPECIAL NOTE: RVCO1 and RVCO2 are functional over a reduced temperature range of TA=0°C to 50°C. RVCO0 and RVCO3 are functional over the full temperature range of TA=0°C to 70°C. This limitation does not affect operation with the GS9010A ATS. GS9015A 24 DIGITAL 5,6 IN 25 DATA LATCH 22 23 SERIAL DATA SERIAL DATA SERIAL CLOCK SERIAL CLOCK PHASE COMPARATOR 10 CARRIER 19 DETECT ÷2 CARRIER DETECT ƒ/2 CHARGE PUMP 20 LOOP FILTER 12 VCO STANDARD SELECT 21 SS0 SS1 PLL 13 14 15 17 FUNCTIONAL BLOCK DIAGRAM Revision Date: April 1998 Document No. 520 - 99 - 05 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 Web Site: www.gennum.com E-mail: [email protected] ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE/UNITS Supply Voltage CAUTION ELECTROSTATIC 5.5 V Input Voltage Range (any input) SENSITIVE DEVICES VCC+0.5 to VEE-0.5 V DC Input Current (any one input) DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION 5 mA Power Dissipation 750 mW 0°C ≤ TA ≤70°C Operating Temperature Range -65°C ≤ TS≤150°C Storage Temperature Range Lead Temperature (soldering, 10 seconds) 260°C GS9015A RECLOCKER DC ELECTRICAL CHARACTERISTICS V S = 5V, TA = 0°C to 70°C, R L = 100Ω to (VCC - 2V) unless otherwise shown. PARAMETER SYMBOL CONDITIONS MIN MAX UNITS 4.75 5.0 5.25 V NOTES Supply Voltage VS Power Consumption PD - 330 500 mW Supply Current (Total) IS - 87 120 mA Serial Data & - High V OH T A = 25°C -1.025 - -0.88 V with respect to V CC Clock Output - Low V OL T A = 25°C -1.9 - -1.6 V with respect to VCC Logic Inputs - High V IH MIN +2.0 - - V with respect to V EE (1, 10, 20, 21) - Low V IL MAX - - +0.8 V with respect to V EE 0.2 0.4 V 4.0 5.0 - V MIN TYP MAX UNITS Carrier Detect V CDL Output Voltage V CDH Operating Range TYP RL = 10 kΩ to VCC see Figure11 with respect to VEE Open Collector - Active High GS9015A RECLOCKER AC ELECTRICAL CHARACTERISTICS V S = 5V, TA = 0°C to 70°C, R L = 100Ω to (VCC - 2V) unless otherwise shown. PARAMETER SYMBOL CONDITION NOTES Serial Data Bit Rate BR SDO T A = 25°C 100 - 400 Mb/s Serial Clock Frequency ƒ SLK T A = 25°C 100 - 400 MHz see Figure 9 Output Signal Swing VO T A = 25°C 700 800 900 mV p-p see Figure10 Serial Data to Serial Clock Synchronization td See Waveforms - -500 - ps Lock Times t LOCK see note 1 - - 10 µs Jitter tJ T A= 25°C, 270 Mb/s - ± 100 - ps p-p see Figure12 Direct Digital Input V DDI 200 - 2000 mVp-p Differential Drive Levels (5, 6) NOTES: 1. Switching between two sources of the same data rate. 520 - 99 - 05 2 Data lags Clock tD tD SERIAL DATA OUT (SD0) SERIAL CLOCK OUT (SCK) 50% 50% Fig.1 Waveforms GS9015A Reclocking Receiver - Detailed Device Description The GS9015A Reclocking Receiver is a bipolar integrated circuit containing circuitry necessary to re-clock and regenerate the NRZI serial data stream. VCO Centre Frequency Selection The centre frequency of the VCO is set by one of four external current reference resistors (RVCO0-RVCO3) connected to pins 13,14,15 or 17. These are selected by two logic inputs SS0 and SS1 (pins 20, 21) through a 2:4 decoder according to the following truth table. Packaged in a 28 pin PLCC, the receiver operates from a single five volt supply at data rates to 400 Mb/s. Typical power consumption is 330 mW. Typical output jitter is ± 100 ps at 270 Mb/s. Serial Digital signals are applied to digital inputs DDI and DDI (pins 5,6). SS1 SS0 Resistor Selected 0 0 RVCO0 (13) Phase Locked Loop 0 1 RVCO1 (14) The phase comparator itself compares the position of transitions in the incoming signal with the phase of the local oscillator (VCO). The error-correcting output signals are fed to the charge pump in the form of short pulses. The charge pump converts these pulses into a “charge packet” which is accurately proportional to the system phase error. 1 0 RVCO2 (15) 1 1 RVCO3 (17) As an alternative, the GS9010A Automatic Tuning Sub-system and the GS9000B or GS9000S Decoder may be used in conjunction with the GS9015A to obtain adjustment free and automatic standard select operation (see Figure17). The charge packet is then integrated by the second-order loop filter to produce a control voltage for the VCO. During periods when there are no transitions in the signal, the loop filter voltage is required to hold precisely at its last value so that the VCO does not drift significantly between corrections. Commutating diodes in the charge pump keep the output leakage current extremely low, minimizing VCO frequency drift. With the VCO operating at twice the clock frequency, a clock phase which is centred on the eye of the locked signal is used to latch the incoming data, thus maximising immunity to jitter-induced errors. The alternate phase is used to latch the output re-clocked data SDO and SDO (pins 25, 24). The true and inverse clock signals themselves are available from the SCO and SCO pins 23 and 22. The VCO is implemented using a current-controlled multivibrator, designed to deliver good stability, low phase noise and wide operating frequency capability. The frequency range is design-limited to ± 10% about the oscillator centre frequency. 3 520 - 99 - 05 VEE1 VEE1 4 3 VEE1 VEE1 VEE1 VEE2 VCC3 2 28 27 26 DDI 5 25 SD0 DDI 6 24 SD0 VCC1 7 23 SC0 VEE1 8 22 SC0 VEE1 9 21 SS1 ƒ/2 EN 10 20 SS0 VEE3 11 19 CD GS9015A TOP VIEW 12 13 14 15 16 LOOP RVCO0 RVCO1 RVCO2 VEE3 FILT 17 18 RVCO3 VCC2 Fig. 2 GS9015A Pin Connections GS9015A PIN DESCRIPTIONS PIN NO. SYMBOL TYPE DESCRIPTION 1 VEE1 Power Supply. Most negative power supply connection. 2 VEE1 Power Supply. Most negative power supply connection. 3 VEE1 Power Supply. Most negative power supply connection. 4 VEE1 Power Supply. Most negative power supply connection. 5,6 DDI/DDI Input Direct Data Inputs (true and inverse). Pseudo-ECL, differential serial data inputs. They may be directly driven from true ECL drivers when VEE = -5V and VCC = 0 V. 7 VCC1 Power Supply. Most positive power supply connection. (Phase Detector, Carrier Detect). 8, 9 VEE1 Power Supply. Most negative power supply connection. 10 ƒ/2 EN 11 VEE3 Power Supply. Most negative power supply connection. (VCO, MUX, Standard Select) 12 LOOP FILT Loop Filter. Node for connecting the loop filter components. 13 RVCO0 Input Input ƒ/2 Enable-TTL compatible input used to enable the divide by 2 function. VCO Resistor 0. Analog current input used to set the centre frequency of the VCO when the two Standard Select bits (pins 20 and 21) are set LOW. A resistor is connected from this pin to VEE. 14 RVCO1 Input VCO Resistor 1. Analog current input used to set the centre frequency of the VCO when Standard Select bit 0 (pin 20) is set HIGH and bit 1 (pin 21) is set LOW. A resistor is connected from this pin to VEE. 15 RVCO2 Input VCO Resistor 2. Analog current input used to set the centre frequency of the VCO when Standard Select bit 0 (pin 20) is set LOW and bit 1 (pin 21) is set HIGH. A resistor is connected from this pin to VEE. 16 VEE3 17 RVCO3 Power Supply. Most negative power supply connection. Input VCO Resistor 3. Analog current input used to set the centre frequency of the VCO when the two Standard Select bits (pins 20 and 21) are set HIGH. A resistor is connected from this pin to VEE. 520 - 99 - 05 4 GS9015A PIN DESCRIPTIONS cont. PIN NO SYMBOL 18 VCC2 19 CD TYPE DESCRIPTION Power Supply. Most positive power supply connection. (VCO, MUX, Standard Select). Output Carrier Detect. Open collector output which goes HIGH when a signal is present at either the Serial Data inputs or the Direct Digital inputs. This output is used in conjunction with the GS9000B or GS9000S in the Automatic Standards Select Mode to disable the 2 bit standard select counter. This pin should see a low AC impedance (e.g. 1nF to AC Gnd) 20,21 SS0, SS1 Inputs Standard Select Inputs. TTL inputs to the 2:4 multiplexer used to select one of four VCO centre frequency setting resistors (RVCO0 - RVCO3). When both SS0 and SS1 are LOW, RVCO0 is selected. When SS0 is HIGH and SS1 is LOW, RVCO1 is selected. When SS0 is LOW and SS1 is HIGH, RVCO2 is selected and when both SS0 and SS1 are HIGH, RVCO3 is selected. These pins should see a low AC impedance (e.g. 1nF to AC Gnd) 22,23 SCO/SCO Outputs Serial Clock Outputs (inverse and true). Pseudo-ECL differential outputs of the extracted serial clock. These outputs require a 390 Ω pull-down resistors to V EE. 24,25 SDO/SDO Outputs Serial Data Outputs (inverse and true). Pseudo-ECL differential outputs of the regenerated serial data. These outputs require a 390 Ω pull-down resistors to V EE. 26 VCC3 Power Supply. Most positive power supply connection. (ECL Outputs). 27 VEE2 Power Supply. Most negative power supply connection. (Phase Detector, Carrier Detect) 28 VEE1 Power Supply. Most negative power supply connection. INPUT / OUTPUT CIRCUITS VCC + - 1.2V 2k 2k 1k 1k DDI Pin 5 DDI Pin 6 380µA + 1.6V - Fig. 3 Pins 1, 5 and 6 5 520 - 99 - 05 INPUT / OUTPUT CIRCUITS cont. IVCO (1.9 - 2.4V) 400 Pin 13 RVCO 0 400 Pin 14 RVCO 1 400 Pin 15 RVCO 2 400 Pin 17 RVCO 3 Fig. 4 Pins 13, 14, 15 and 17 VCC VCC3 200 200 10k 10k SDO or SCO Pin 25, 24 SDO or SCO Pin 23, 22 VCC VCC 3k 800 Fig. 5 Pins 25, 24, 23 and 22 520 - 99 - 05 6 LOOP FILTER (1.8 - 2.7V) INPUT / OUTPUT CIRCUITS cont. VCC VCC VCC VCC 10k 1.5k CD Pin 19 2k LOOP FILTER Pin 12 1k Fig. 7 Pin 19 Fig. 6 Pin 12 VCC VCC VCC 18µA 40µA 40µA VCC VCC SS1 Pin 21 ƒ/2 EN Pin 10 55µA 480µA + - 1.6V SSO Pin 20 Fig. 8 Pins 20, 21 and 10 7 520 - 99 - 05 TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25°C unless otherwise shown) 900 500 450 SERIAL OUTPUTS (mV) (p-p) 850 FREQUENCY (MHz) 400 350 300 250 ƒ/2 OFF 200 ƒ/2 ON 150 VS = 5.25V 800 VS = 5.00V 750 700 VS = 4.75V 650 100 50 600 1 2 3 4 5 6 7 8 9 10 0 10 20 30 40 50 FREQUENCY SETTING RESISTANCE (kΩ) TEMPERATURE (°C) Fig. 9 Clock Frequency Fig. 10 Serial Outputs 60 70 400 105 350 100 300 95 90 JITTER p-p (ps) CURRENT (mA) V S = 5.25V V S = 5.00V 85 V S = 4.75V 80 250 ƒ/2 OFF 200 150 75 100 70 50 ƒ/2 ON 65 0 10 20 30 40 50 60 0 70 100 150 200 250 300 TEMPERATURE (°C) DATA RATE (Mb/s) Fig. 11 Supply Current Fig. 12 Output Jitter 520 - 99 - 05 8 350 400 +5V 0.1µ 390 +5V 0.1µ ECL DATA INPUTS VEE2 VEE1 1 28 27 26 VEE1 VEE1 2 SDO SDO SCO GS9015A SCO 25 100 24 100 DATA 23 100 CLOCK 100 CLOCK 22 +5V SS1 21 SS0 20 VCC2 RVCO3 VEE3 RVCO2 RVCO1 RVCO0 LOOP 9 VEE1 10 ƒ/2 11 VEE3 390 VCC3 5 DDI 6 DDI 7 VCC1 8 VEE1 3 VEE1 VEE1 4 CD DATA 390 390 CARRIER DETECT OUTPUT 19 10k 12 13 14 15 16 17 18 +5V 0.1µ 5.6p 910 +5V 10n ÷2 ÷1 See Figure 15 STAR ROUTED LOOP VOLTAGE TEST POINT All resistors in ohms, all capacitors in microfarads unless otherwise stated. Fig. 13 GS9015A Typical Test Circuit Using +5V Supply TEST SETUP The Carrier Detect is an open-collector active high output requiring a pull-up resistor of approximately 10 kΩ. Figure 13 shows a typical circuit for the GS9015A using a +5 volt supply. Figure 14 shows the GS9015A connections when using a -5 volt supply. The SS0, SS1, and CD pins should see a low AC impedance. This is particularly important when driving the SS0, SS1 pins with external logic. The use of 1nF decoupling capacitors at these pins ensures this. The 0.1µF decoupling capacitors must be placed as close as possible to the corresponding VCC pins. The layout of the loop filter and RVCO components requires careful attention. This has been detailed in an application note entitled "Optimizing Circuit and Layout Design of the GS9005A/15A", Document No. 521 - 32 - 00. The loop voltage can be conveniently measured across the 10 nF capacitor in the loop filter. Tuning procedures are described in the Temperature Compensation Section (page 11). The fixed value frequency setting resistors should be placed close to the corresponding pins on the GS9015A. 9 520 - 99 - 05 0.1µ -5V 390 ECL DATA INPUTS 6 VEE2 SDO SDO DDI SCO 7 GS9015A SCO SS1 9 VEE1 -5V 25 100 24 100 DATA 23 100 CLOCK 22 100 CLOCK 21 390 20 390 19 VCC2 RVCO3 V EE3 RVCO2 RVCO1 LOOP -5V RVCO0 SS0 10 ƒ/2 11 VEE3 390 VCC3 VEE1 1 28 27 26 VEE1 VEE1 2 DDI VCC1 8 VEE1 0.1µ 3 VEE1 5 VEE1 4 DATA CARRIER DETECT OUTPUT CD 10k 12 13 14 15 16 17 18 0.1µ 5.6p 10n 910 -5V ÷2 ÷1 See Figure 15 STAR ROUTED -5V -5V LOOP VOLTAGE -5V All resistors in ohms, all capacitors in microfarads unless otherwise stated. Fig. 14 GS9015A Typical Test Circuit Using -5V Supply VCO Frequency Setting Resistors There are two modes of VCO operation available in the GS9015A depending on the state of the ÷ 2 block. The ÷ 2 block is enabled according to : ÷ 2 ENABLE = ƒ/2 • SS1. When the ƒ/2 ENABLE (pin 10) is LOW, any of the four VCO frequency setting resistors, RVCO0 through RVCO3, (pins 13, 14, 15 and 17) may be used for any data r a t e f r o m 100 Mb/s t o 4 0 0 M b / s . F o r e x a m p l e , f o r 143 Mb/s data rate, the value of the total RVCO resistance is approximately 6k8 and f o r 2 7 0 M b / s o p e r a t i o n , t h e v a l u e i s approximately 3k5. The 5k potentiometers will then tune the desired data rate near their mid-points. Jitter performance at the lower data rates (143, 177 Mb/s) is improved by operating the VCO at twice the normal frequency. This is accomplished by enabling the divide by two block in the PLL section of the GS9015A. 520 - 99 - 05 10 When ƒ/2 (Pin 10) is HIGH, two of the RVCO pins are assigned to data rates below 200 Mb/s and two are assigned to data rates over 200 Mb/s. The selection is dependent upon the level of STANDARD SELECT BIT, SS1 (pin 21). When SS1 is LOW, RVCO0 and RVCO1 (pins 13 and 14) are used for the higher data rates. When SS1 is HIGH, the VCO frequency is now twice the bit rate and its frequency is set by RVCO2 and RVCO3 (pins 15 and 17). For 143 Mb/s and 270 Mb/s operation, (the VCO is at 286 MHz and 270 MHz respectively) the total resistance required is approximately the same for both data rates. This also applies for 177 Mb/s and 360 Mb/s operation (the VCO is tuned to 354 MHz and 360 MHz respectively). This means that one potentiometer may be used for each frequency pair with only a small variation of the fixed resistor value. This halves the number of adjustments required. Temperature Compensation Figure 15 shows the connections for the frequency setting resistors for the various data rates. The compensation shown for 360 Mb/s and 177 Mb/s with Divide by 2 ON, is useful to a maximum ambient temperature of 50°C. If the Divide by 2 function is not enabled by the ƒ/2 ENABLE input, no compensation is needed for the 143 Mb/s and 177 Mb/s data rates. The resistor connections are shown in Figure 16. In both cases , the 0.1µF capacitor that bypasses the potentiometer should be star routed to VEE3. 1k 5k 0.1µF VEE Divide by 2 is OFF 143Mb/s and 177 Mb/s using any R VCO pins Fig. 16 5.6k 4.3k 1.3k 1N914 5k 0.1µF Non - Temperature Compensated Resistor Values 1.3k 1N914 5k for 143 Mb/s and 177 Mb/s 0.1µF Loop Bandwidth VEE The loop bandwidth is dependant upon the internal PLL gain constants along with the loop filter components connected to pin 12. In addition, the impedance seen by the RVCO pin also influences the loop characteristics such that as the impedance drops, the loop gain increases. VEE Divide by 2 is OFF Divide by 2 is ON 270 Mb/s using RVCO0 or R VCO1 143 Mb/s using RVCO2 or R VCO3 Applications Circuit 1k 1k 1k 0.1µF 1k 0.1µF 1N914 1N914 VEE Divide by 2 is OFF 360 Mb/s using RVCO0 or R VCO1 Figure 17 shows an application of the GS9015A in an adjustment free, multi-standard serial to parallel convertor. This circuit uses the GS9010A Automatic Tuning Subsystem IC and a GS9000B or GS9000S Decoder IC. The GS9010A ATS eliminates the need to manually set or externally temperature compensate the Receiver or Reclocker VCO. The GS9010A can also determine whether the incoming data stream is 4ƒsc NTSC,4ƒsc PAL or component 4:2:2. VEE Divide by 2 is ON 177 Mb/s using RVCO2 or R VCO3 Fig. 15 Frequency Setting Resistor Values The GS9010A includes a ramp generator/oscillator which repeatedly sweeps the Reclocker VCO frequency over a set range until the system is correctly locked. An automatic fine tuning (AFT) loop maintains the Reclocker VCO control voltage at it's centre point through continuous, long term adjustments of the VCO centre frequency. & Temperature Compensation Temperature Compensation Procedure In order to correctly set the VCO frequency so that the PLL will always re-acquire lock over the full temperature range, the following procedure should be used. The circuit should be powered on for at least one minute prior to starting this procedure. During normal operation, the GS9000B or GS9000S Decoder provides continuous HSYNC pulses which disable the ramp/oscillator of the GS9010A. This maintains the correct Reclocker VCO frequency. When an interruption to the incoming data stream is detected by the Reclocker, the Carrier Detect goes LOW and opens the AFT loop in order to maintain the correct VCO frequency for a period of at least 2 seconds. This allows the Reclocker to rapidly relock when the signal is re-established. Monitor the loop filter voltage at the junction of the loop filter resistor and 10 nF loop filter capacitor (LOOP FILTER TEST POINT). Using the appropriate network shown above, the VCO frequency is set by first tuning the potentiometer so that the PLL loses lock at the low end (lowest loop filter voltage). The loop filter voltage is then slowly increased by adjusting the the potentiometer to determine the error free low limit of the capture range. Error free operation is determined by using a suitable CRC or EDH measurement method to obtain a stable signal with no errors. Record the loop filter voltage at this point as VCL. Now adjust the potentiometer so that the loop filter voltage is 250 mV above VCL. 11 520 - 99 - 05 Application Note - PCB Layout Special attention must be paid to component layout when designing high performance serial digital receivers. For background information on high speed circuit and layout design concepts, refer to Document No. 521-32-00, “Optimizing Circuit and Layout Design of the GS90005A/15A”. A recommended PCB layout can be found in the Gennum Application Note “EB9010B Deserializer Evaluation Board” The use of a star grounding technique is required for the loop filter components of the GS9005A/15A. Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005A and the GS9000B or GS9000S. These differential traces must not pass over any ground plane discontinuities. A slot antenna is formed when a microstrip trace runs across a break in the ground plane. The series resistors at the parallel data output of the GS9000B or GS9000S are used to slow down the fast rise/fall time of the GS9000B or GS9000S outputs. These resistors should be placed as close as possible to the GS9000B or GS9000S output pins to minimize radiation from these pins. DVCC VCC +5V + + 10µ 10µ 100 3.3k 100 100 DGND DGND GND VCC SWF +5V 0.1µ SYNC WARNING FLAG DGND DGND SCO 23 SCO 22 100 7 GS9015A 100 8 390 9 390 10 VCC2 RVCO3 VEE3 LOOP 9 VEE1 10 ƒ/2 RVCO2 SS1 21 SS0 20 11 CD 19 12 13 14 15 16 17 18 5.6p VCC VSS PD8 PD9 VSS SWF 100 22 100 21 100 20 100 PD1 19 100 PD4 PD3 SS1 PD2 SS0 SST 12 13 14 15 16 DVCC VCC 23 PD5 GS9000B or GS9000S SCI 100 PD6 (3) SCI 24 PD7 SDI PARALLEL DATA BIT 8 100 VDD 6 PARALLEL DATA BIT 9 25 PDO 100 HSYNC OUTPUT 28 27 26 PCLK 24 SDI 1 SWC VCC1 VSS 5 2 SCE VEE2 100 SDO DDI VEE3 25 SDO 8 VEE1 11 390 VCC3 VEE1 VEE1 VEE1 VEE1 28 27 26 3 VDD 7 1 DDI RVCO1 0.1µ 6 2 VDD SERIAL DIGITAL INPUT 3 RVCO0 VCC 5 VEE1 4 4 HSYNC 390 17 PARALLEL DATA BIT 7 PARALLEL DATA BIT 6 PARALLEL DATA BIT 5 PARALLEL DATA BIT 4 PARALLEL DATA BIT 3 PARALLEL DATA BIT 2 PARALLEL DATA BIT 1 PARALLEL DATA BIT 0 DVCC 18 PARALLEL CLOCK OUT SYNC CORRECTION ENABLE 0.1µ 910 0.1µ 0.1µ 100 100 DGND 10n (1) DGND 1.2k VCC DVCC 1.2k (2) 0.1µ 68k 50k 22n VCC 120 DGND STAR ROUTED GS9010A (1) 6.8µ 6.8µ + 1 2 + 3 4 3.3n 5 P/N STDT OUT VCC INCOMP LF 6 ƒ/2 7 V CC 8 SWF VCC 16 0.1µ 15 14 CD HSYNC 13 GND 12 VCC OSC 11 DLY 10 FVCAP 9 STANDARD TRUTH TABLE 100k 82n 0.68µ (1) VCC 0.1µ All resistors in ohms, all capacitors in microfarads, all inductors in henries unless otherwise stated. 180n SWF (1) To reduce board space, the two anti-series 6.8 µF capacitors (connected across pins 2 and 3 of the GS9010A) may be replaced with a 1.0 µF non-polarized capacitor provided that: (a) the 0.68 µF capacitor connected to the OSC pin (11) of the GS9010A is replaced with a 0.33 µF capacitor and (b) the GS9005A /15A Loop Filter Capacitor is 10 nF. (2) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A. (3) The GS9000B will operate to a maximum frequency of 370 Mbps. The GS9000S will operate to a maximum of 300 Mbps. Fig. 17 Typical Application Circuit 520 - 99 - 05 12 ƒ/2 P/N STANDARD 0 0 4:2:2 - 270 0 1 4:2:2 - 360 1 0 4ƒsc - NTSC 1 1 4ƒsc - PAL DOCUMENT IDENTIFICATION: DATA SHEET REVISION NOTES: The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. New information added to Device Description GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax +1 (905) 632-2814 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168-0081, Japan Tel. +81 (3) 3334-7700 Fax: +81 (3) 3247-8839 GENNUM UK LIMITED Centaur House, Ancells Business Park, Ancells Road, Fleet, Hampshire, UK GU13 8UJ Tel. +44 (1252) 761 039 Fax +44 (1252) 761 114 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright October 1993 Gennum Corporation. All rights reserved. 13 Printed in Canada. 520 - 99 - 05