AGILENT HFBR

Agilent HFBR-5710L/LP
Small Form Factor Pluggable
Optical Transceiver for Gigabit
Ethernet (1.25 GBd)
Data Sheet
Applications
• Switch to switch interface
• Switched backplane applications
• File server interface
• iSCSI applications
Description
The HFBR-5710L optical
transceiver is compliant with the
specifications set forth in both the
IEEE802.3 (1000BASE-SX), and
the Small Form-Factor Pluggable
(SFP) Multi-Source Agreement
(MSA). Its primary application is
servicing Gigabit Ethernet links
between optical networking
equipment. It offers previously
unavailable system cost, upgrade,
and reliability benefits by virtue of
being hot-pluggable. Further, it
incorporates the latest 3.3 VDC
compatible transceiver technology
including an 850 nm VCSEL
transmitter as well as a convenient
LC-Duplex optical interface.
Features
• IEEE 802.3 Gigabit Ethernet (1.25
GBd) 1000BASE-SX compliant
• Small Form Factor Pluggable (SFP)
Multi-Source Agreement (MSA)
compliant
• Manufactured in an ISO 9001
compliant facility
• Hot-pluggable
• Optional extended de-latch for
high density applications as shown
in Figure 10
– HFBR-5710LP extended de-latch
– HFBR-5710L standard de-latch
• +3.3 V DC power supply
• Industry leading EMI performance
for high port density
• 850 nm Vertical Cavity Surface
Emitting Laser (VCSEL)
• Eye safety certified:
– US 21 CFR(J)
– EN 60825-1 (+All)
• LC-Duplex fiber connector
compatible
• Fiber compatibility:
– 2 to 550 meters with 50/125 µm
fiber
– 2 to 275 meters with 62.5/125 µm
fiber
Related Products
• HFBR-5701L: Dual specified 1.25
GBd Ethernet (1000BASE-SX) and
1.0625 GBd Fibre Channel (100-M5SN-I, 100-M6-SN-I) SFP
• HFBR-5720L: 2.125 GBd Fibre
Channel (200-M5-SN-I, 200-M6-SN-I)
Multi-Mode SFP
• HFBR-5730L: 1.0625 GBd Fibre
Channel (100-M5-SN-I, 100-M6-SN-I)
Multi-Mode SFP
• HDMP-1687: Quad Channel SerDes
IC 1.25 GBd Ethernet
• HDMP-1646A: Single Channel
SerDes IC for 1.25 GBd Ethernet and
1.0625 GBd Fibre Channel
OPTICAL INTERFACE
INCOMING OPTICAL SIGNAL
RECEIVER
ELECTRICAL INTERFACE
RD+ (RECEIVE DATA)
AMPLIFICATION
& QUANTIZATION
PHOTODETECTOR
RD– (RECEIVE DATA)
LOSS OF SIGNAL
TRANSMITTER
OUTGOING OPTICAL SIGNAL
TX_DISABLE
LASER
DRIVER &
SAFETY
CIRCUITRY
VCSEL
TD+ (TRANSMIT DATA)
TD– (TRANSMIT DATA)
TX_FAULT
MOD-DEF2
EEPROM
MOD-DEF1
MOD-DEF0
Figure 1. HFBR-5710L block diagram.
Overview
The HFBR-5710L offers maximum flexibility to designers,
manufacturers, and operators of
Gigabit Ethernet networking
equipment. A pluggable architecture allows the module to be
installed into MSA standard SFP
ports at any time – even with the
host equipment operating and
online. This facilitates the rapid
configuration of equipment to
precisely the user’s needs –
reducing inventory costs and
network downtime. Compared
with traditional transceivers, the
size of the Small Form Factor
package enables higher port
densities.
Module Diagrams
Figure 1 illustrates the major
functional components of the
HFBR-5710L. The external
configuration of the module is
depicted in Figure 7. Figure 8
depicts the panel and host board
footprints.
Installation
The HFBR-5710L can be installed
in or removed from any MSAcompliant Pluggable Small Form
2
Factor port regardless of whether
the host equipment is operating
or not. The module is simply
inserted, electrical-interface first,
under finger-pressure. Controlled
hot-plugging is ensured by
3-stage pin sequencing at the
electrical interface. This printed
circuit board card-edge connector
is depicted in Figure 2.
As the HFBR-5710L is inserted,
first contact is made by the
housing ground shield, discharging any potentially
component-damaging static
electricity. Ground pins engage
next and are followed by Tx and
Rx power supplies. Finally, signal
lines are connected. Pin functions
and sequencing are listed in
Table 2.
3 2 1
20
VEET
19
3 2 1
ENGAGEMENT
SEQUENCE
1
VEET
TD–
2
TX FAULT
18
TD+
3
TX DISABLE
17
VEET
4
MOD-DEF(2)
16
VCCT
5
MOD-DEF(1)
15
VCCR
6
MOD-DEF(0)
14
VEER
7
RATE SELECT
13
RD+
8
LOS
12
RD–
9
VEER
11
VEER
10
VEER
TOP OF BOARD
Figure 2. Pin description of the SFP electrical interface.
BOTTOM OF BOARD
(AS VIEWED THROUGH TOP OF BOARD)
Before extracting the module, the
black plastic tab beneath the
optical port must be depressed,
releasing the latch mechanism.
The transceiver can then be
pulled out of the port manually by
gripping the side of the LC ports.
For easier fingertip delatching in
high port density applications, an
optional extended tab is offered
as shown in Figure 10.
Serial Identification (EEPROM)
The HFBR-5710L features an
EEPROM for Serial ID. It
contains the product data stored
for retrieval by host equipment.
This data is accessed via the 2wire serial EEPROM protocol of
the ATMEL AT24C01A or similar
in compliance with the industry
standard SFP Multi-Source
Agreement. Contents of the
HFBR-5710L serial ID memory
are displayed in Table 9.
Transmitter Section
The transmitter section includes
the Transmitter Optical Subassembly (TOSA) and laser driver
circuitry. The TOSA, containing
an 850 nm VCSEL (Vertical
Cavity Surface Emitting Laser)
light source, is located at the
optical interface and mates with
the LC optical connector. The
TOSA is driven by a custom IC,
which converts differential logic
signals into an analog laser diode
drive current. This Tx driver
circuit regulates the optical
power at a constant level
provided the data pattern is DC
balanced (8B10B code for
example).
Tx Disable
The HFBR-5710L accepts a
transmit disable control signal
input which shuts down the
transmitter. A high signal
implements this function while a
low signal allows normal laser
3
operation. In the event of a fault
(e.g., eye safety circuit activated),
cycling this control signal resets
the module as depicted in Figure 6.
Eye Safety Circuit
The HFBR-5710L provides Class
1 eye safety by design and has
been tested for compliance with
the requirements listed in
Table 1. The eye safety circuit
continuously monitors optical
output power levels and will
disable the transmitter and assert
a TX_FAULT signal upon
detecting an unsafe condition.
Such unsafe conditions can be
created by inputs from the host
board (Vcc fluxuation,
unbalanced code) or faults within
the module.
Receiver Section
The receiver section includes the
Receiver Optical Subassembly
(ROSA) and amplification/
quantization circuitry. The ROSA,
containing a PIN photodiode and
custom trans-impedance
preamplifier, is located at the
optical interface and mates with
the LC optical connector. The
ROSA is mated to a custom IC
that provides post-amplification
and quantization. Also included is
a Loss Of Signal (LOS) detection
circuit.
Loss of Signal
The Loss Of Signal (LOS) output
indicates an unusable optical
input power level. A high LOS
output signal indicates a loss of
signal while a low LOS output
signal indicates normal operation.
The Loss Of Signal thresholds are
set to indicate a definite optical
fault has occurred (e.g.,
disconnected or broken fiber
connection to receiver, failed
transmitter, etc.).
Functional I/O
The HFBR-5710L accepts
industry standard differential
signals such as LVPECL and CML
within the scope of the SFP MSA.
To simplify board requirements,
transmitter bias resistors and
coupling capacitors are
incorporated into the transceiver
module. The module is “accoupled” and internally
terminated.
Figure 4 illustrates a recommended interface circuit to link
the HFBR-5710L to the
supporting Physical Layer
integrated circuits.
Timing diagrams for the MSA
compliant control signals
implemented in this module are
depicted in Figure 6.
1 µH
VCCT
0.1 µF
1 µH
3.3 V
VCCR
0.1 µF
SFP MODULE
10 µF
HOST BOARD
Figure 3. MSA required power supply filter.
0.1 µF
10 µF
Required Host Board Components
The MSA power supply noise
rejection filter is required on the
host PCB to meet data sheet
performance. The MSA filter
incorporates an inductor which
should be rated 400 mADC and
1 Ω series resistance or better. It
should not be replaced with a
ferrite. The required filter is
illustrated in Figure 3.
The MSA also specifies that 4.7 K
to 10 KΩ pull-up resistors for
TX_FAULT, LOS, and
MOD_DEF0,1,2 are required on
the host PCB.
Application Support
Evaluation Kit
To assist in the transceiver
evaluation process, Agilent offers
a 1.25 Gbd Gigabit Ethernet
evaluation board which facilitates
testing of the HFBR-5710L. It can
be obtained through the Agilent
Field Organization by referencing
Agilent part number HFBR-0571.
Reference Designs
A Reference Design including the
HFBR-5710L and the HDMP1687 GigaBit Quad SerDes is
available. It may be obtained
through the Agilent Field Sales
organization.
Regulatory Compliance
See Table 1 for transceiver
Regulatory Compliance. Certification level is dependent on the
overall configuration of the host
equipment. The transceiver
performance is offered as a figure
of merit to assist the designer.
4
Electrostatic Discharge (ESD)
There are two design cases in
which immunity to ESD damage
is important.
The first case is during handling
of the transceiver prior to
insertion into the transceiver
port. To protect the transceiver,
it’s important to use normal ESD
handling precautions. These
precautions include using
grounded wrist straps, work
benches, and floor mats in ESD
controlled areas. The ESD
sensitivity of the HFBR-5710L is
compatible with typical industry
production environments.
The second case to consider is
static discharges to the exterior
of the host equipment chassis
after installation. To the extent
that the optical interface is
exposed to the outside of the host
equipment chassis, it may be
subject to system-level ESD
requirements.
Immunity
The ESD performance of the
HFBR-5710L exceeds typical
industry standards.
Equipment hosting HFBR-5710L
modules will be subjected to
radio-frequency electromagnetic
fields in some environments. The
transceiver has good immunity to
such fields due to its shielded
design.
Electromagnetic Interference (EMI)
Equipment incorporating Gigabit
Ethernet transceivers is typically
required to meet the requirements of the FCC in the United
States, CENELEC EN55022
(CISPR 22) in Europe, and VCCI
in Japan.
The metal housing and shielded
design of the HFBR-5710L
minimize the EMI challenge
facing the host equipment
designer.
Flammability
The HFBR-5710L transceiver is
made of metal and high strength,
heat resistant, chemically
resistant, and UL 94V-0 flame
retardant plastic.
Caution
There are no user serviceable
parts nor any maintenance
required for the HFBR-5710L. All
adjustments are made at the
factory before shipment to our
customers. Tampering with,
modifying, misusing or improperly handling the HFBR-5710L
will void the product warranty. It
may also result in improper
operation of the HFBR-5710L
circuitry, and possible overstress
of the laser source. Device
degradation or Product failure
may result. Connection of the
HFBR-5710L to a non-Gigabit
Ethernet-compliant optical
source, operating above the
recommended absolute maximum
conditions or operating the
HFBR-5710L in a manner
inconsistent with its design and
function may result in hazardous
radiation exposure and may be
considered an act of modifying or
manufacturing a laser product.
The person(s) performing such
an act is required by law to recertify and re-identify the laser
product under the provisions of
U.S. 21 CFR (Subchapter J).
1 µH
VCCT,R
10 µF
0.1 µF
HOUSING
GROUND
1 µH
0.1
µF
*RES
TX_DISABLE
GP04
TX_FAULT
TX_FAULT
VREFR
MAC
ASIC
RBC
RX_RATE
50 Ω
SO1+
TX[0:9]
TBC
EWRAP
AGILENT
HFBR-5710L
VCCT
*RES
TD+
C
C
50 Ω
SO1–
TD–
SYNC
LOOP
VEET
AGILENT
HDMP-1687
10
µF
RX[0:9]
SYN1
RC1(0:1)
SI1+
RCM0
SI1–
RX_LOS
LASER DRIVER
& EYE SAFETY
CIRCUITRY
R
RFCT
0.1
µF
VCCR
50 Ω
R
RD+
C
C
50 Ω
RD–
AMPLIFICATION
&
QUANTIZATION
REF_RATE
VCCT,R
*RES
*RES
*RES
*RES
RX_LOS
GPIO(X)
GPIO(X)
GP14
MOD_DEF2
MOD_DEF1
EEPROM
MOD_DEF0
REFCLK
VEER
125 MHz
NOTE: * 4.7 k < RES < 10 kΩ
Figure 4. Typical application configuration.
Table 1. Regulatory Compliance
Feature
Test Method
Performance
Electrostatic Discharge (ESD)
to the Electrical Pins
JEDEC/EIA
JESD22-A114-A
Class 2 (> +2000 Volts)
Electrostatic Discharge (ESD)
to the Duplex LC Receptacle
Variation of IEC 6100-4-2
Typically withstands at least 25 kV without
damage when the duplex LC connector
receptacle is contacted by a Human Body
Model probe
Electromagnetic Interference
(EMI)
FCC Class B
CENELEC EN55022 Class B
(CISPR 22A) VCCI Class 1
Applications with high SFP port counts are
expected to be compliant; however, margins are
dependent on customer board and chassis design.
Immunity
Variation of IEC 61000-4-3
Typically shows a negligible effect from a
10 V/m field swept from 80 to 1000 MHz applied
to the transceiver without a chassis enclosure.
Eye Safety[1]
US FDA CDRH AEL Class 1
EN(IEC)60825-1,2, EN60950
Class 1
CDRH certification #9720151-13
TUV file #E9971083.07
Component Recognition
Underwriters Laboratories and
Canadian Standards Association Joint Component Recognition
for Information Technology
Equipment Including Electrical
Business Equipment
UL File #E173874
Note:
1. Changes to IEC 60825-1,2 are currently anticipated to allow higher eye-safe Optical Output Power levels. Agilent may choose to take advantage of these
in future revisions to this part.
5
Table 2. Pin Description
Pin Name
Function/Description
Engagement Order
(insertion)
1
VeeT
Transmitter Ground
1
2
TX Fault
Transmitter Fault Indication
3
1
3
TX Disable
Transmitter Disable - Module disables on high or open
3
2
4
MOD-DEF2
Module Definition 2 - Two wire serial ID interface
3
3
5
MOD-DEF1
Module Definition 1 - Two wire serial ID interface
3
3
6
MOD-DEF0
Module Definition 0 - Grounded in module
3
3
7
Rate Select Not Connected
3
8
LOS
Loss of Signal
3
9
VeeR
Receiver Ground
1
10
VeeR
Receiver Ground
1
11
VeeR
Receiver Ground
1
12
RD-
Inverse Received Data Out
3
5
13
RD+
Received Data Out
3
5
14
VeeR
Receiver Ground
1
15
VccR
Receiver Power - 3.3 V ± 5%
2
6
16
VccT
Transmitter Power - 3.3 V ± 5%
2
6
17
VeeT
Transmitter Ground
1
18
TD+
Transmitter Data In
3
7
19
TD-
Inverse Transmitter Data In
3
7
20
VeeT
Transmitter Ground
1
Notes
4
Notes:
1. TX Fault is an open collector/drain output which should be pulled up externally with a 4.7K – 10 KΩ resistor on the host board to a supply < VccT+0.3 V
or VccR+0.3 V. When high, this output indicates a laser fault of some kind. Low indicates normal operation. In the low state, the output will be pulled to
< 0.8 V.
2. TX disable input is used to shut down the laser output per the state table below. It is pulled up within the module with a 4.7-10 K resistor.
Low (0 – 0.8 V):
Transmitter on
Between (0.8 V and 2.0 V): Undefined
High (2.0 – 3.465 V):
Transmitter Disabled
Open:
Transmitter Disabled
3. Mod-Def 0,1,2. These are the module definition pins. They should be pulled up with a 4.7-10 KΩ resistor on the host board to a supply less than
VccT +0.3 V or VccR+0.3 V.
Mod-Def 0 is grounded by the module to indicate that the module is present
Mod-Def 1 is clock line of two wire serial interface for optional serial ID
Mod-Def 2 is data line of two wire serial interface for optional serial ID
4. LOS (Loss of Signal) is an open collector/drain output which should be pulled up externally with a 4.7 K – 10 KΩ resistor on the host board to a supply
< VccT,R+0.3 V. When high, this output indicates the received optical power is below the worst case receiver sensitivity (as defined by the standard in
use). Low indicates normal operatio0n. In the low state, the output will be pulled to < 0.8 V.
5. RD-/+: These are the differential receiver outputs. They are AC coupled 100 Ω differential lines which should be terminated with 100 Ω differential at the
user SERDES. The AC coupling is done inside the module and is thus not required on the host board. The voltage swing on these lines must be between
370 and 2000 mV differential (185 – 1000 mV single ended) according to the MSA. Typically it will be 1500mv differential.
6. VccR and VccT are the receiver and transmitter power supplies. They are defined as 3.135 – 3.465 V at the SFP connector pin. The in-rush current will
typically be no more than 30 mA above steady state supply current after 500 nanoseconds.
7. TD-/+: These are the differential transmitter inputs. They are AC coupled differential lines with 100 Ω differential termination inside the module. The AC
coupling is done inside the module and is thus not required on the host board. The inputs will accept differential swings of 500 – 2400 mV (250 – 1200 mV
single ended). However, the applicable recommended differential voltage swing is found in Table 5.
6
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Unit
Notes
Ambient Storage Temperature
(Non-Operating)
Ts
–40
+100
°C
1
Case Temperature
TC
–40
+85
°C
1
Relative Humidity
RH
5
95
%
1
Supply Voltage
VCCT,R
–0.5
3.6
V
1
Voltage at any Input Pin
VIH
–0.5
VCC
V
1
Sense Output Current – LOS, TX Fault
ID
150
mA
1
Sense Output Current – MOD_DEF2
ID
5
mA
1
Notes:
1. Absolute Maximum Ratings are those values beyond which damage to the device may occur if these limits are exceeded. See Reliability Data Sheet for
specific reliability performance.
2. Between Absolute Maximum Ratings and the Recommended Operating Conditions functional performance is not intended, device reliability is not
implied, and damage to the device may occur.
Table 4. Recommended Operating Conditions
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
Case Temperature
TC
0
25
70
°C
1, 2
Supply Voltage
VCC
3.135
3.3
3.465
V
1
Gb/s
1
Date Rate
1.25
Notes:
1. Recommended Operating Conditions are those within which functional performance within data sheet characteristics is intended.
2. Refer to the Reliability Data Sheet for specific reliability performance predictions.
Table 5. Transceiver Electrical Characteristics (TC = 0°C to 70°C, VCCT,R = 3.3 V ± 5%)
Parameter
Symbol
Module Supply Current
Minimum
Typical
Maximum
Unit
ICC
160
220
mA
Power Dissipation
PDISS
530
765
mW
Power Supply Noise
Rejection (peak-peak)
PSNR
100
Data Input:
Transmitter Differential
Input Voltage (TD +/–)
VI
500
Data Output:
Receiver Differential
Output Voltage (RD +/–)
VO
370
Receive Data Rise & Fall
Times
Sense Outputs:
Transmit Fault
[TX_FAULT,
Loss of Signal (LOS),
MOD_DEF2]
Control Inputs:
Transmitter Disable
[TX_DISABLE,
MOD_DEF1,2]
Trf
1500
mVPP
1
1660
mVPP
2
2000
mVPP
3
220
ps
VOH
2.0
VCC
V
VOL
0
0.8
V
VIH
2.0
VCC
V
VIL
0
0.8
V
Notes:
1. Measured at the input of the required MSA Filter on host board.
2. Internally AC coupled and terminated to 100 Ω differential load.
3. Internally AC coupled, but requires a 100 ohm differential termination at or internal to Serializer/Deserializer.
7
Notes
Table 6. Transmitter Optical Characteristics (TC = 0°C to 70°C, VCCT,R = 3.3 V ± 5%)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
Output Optical Power (Average)
Pout
–9.5
–6.5
0
dBm
1, 2, 3
Optical Extinction Ratio
ER
9
14.5
dB
1
Center Wavelength
λC
830
850
860
nm
1
Spectral Width – rms
σ
0.85
nm
1
Optical Rise/Fall Time
Trise/fall
260
ps
1
Relative Intensity Noise, maximum
RIN
–117
dB/Hz
1
Total Jitter
TJ
227
ps
1
0.284
UI
1
–35
dBm
1
150
(TP1 to TP2 Contribution)
Pout TX_DISABLE Asserted
POFF
Notes:
1. IEEE 802.3.
2. Max. Pout is the lesser of 0 dBm or Maximum allowable per Eye Safety Standard.
3. 50/125 µm fiber with NA = 0.2, 62.5/125 µm fiber with NA = 0.275.
NORMALIZED TIME (UNIT INTERVAL)
0.22 0.375
0.625 0.78
1.0
130
1.30
100
1.00
80
0.80
50
0.50
20
0.20
0
0
NORMALIZED AMPLITUDE
NORMALIZED AMPLITUDE (%)
0
–0.20
–20
0
22
37.5
62.5
78
100
NORMALIZED TIME (% OF UNIT INTERVAL)
Figure 5a. Gigabit Ethernet transmitter eye mask diagram.
8
Figure 5b. Typical HFBR-5710L eye mask diagram.
Table 7. Receiver Optical Characteristics (TC = 0°C to 70°C, VCCT,R = 3.3 V ± 5%)
Parameter
Symbol
Minimum
Optical Input Power
PR
–17
Receiver Sensitivity
(Optical Input Power)
PRMIN
Typical
Maximum
Unit
Notes
0
dBm
1
–17
dBm
1
–12.5
dBm
1, 2
–13.5
dBm
1, 3
266
ps
1
(TP3 to TP4 Contribution)
0.332
UI
1
Return Loss
–12
dB
1
–17
dBm
1
dBm
1
dB
1
–21
Stressed Receiver Sensitivity
Total Jitter
TJ
LOS De-Asserted
PD
LOS Asserted
PA
LOS Hysterisis
PD - PA
–31
3
Notes:
1. IEEE 802.3.
2. 62.5/125 µm fiber.
3. 50/125 µm fiber.
Table 8. Transceiver Timing Characteristics (TC = 0°C to 70°C, VCCT,R = 3.3 V ± 5%)
Parameter
Symbol
Tx Disable Assert Time
Minimum
Typical
Maximum
Unit
Notes
t_off
10
µs
1
Tx Disable Negate Time
t_on
1
ms
2
Time to initialize, including
reset of Tx_Fault
t_init
300
ms
3
Tx Fault Assert Time
t_fault
100
µs
4
Tx Disable to Reset
t_reset
µs
5
LOS Assert Time
t_loss_on
100
µs
6
LOS Deassert Time
t_loss_off
100
µs
7
Serial ID Clock Rate
f_serial_clock
100
kHz
10
Notes:
1. Time from rising edge of Tx Disable to when the optical output falls below 10% of nominal.
2. Time from falling edge of Tx Disable to when the modulated optical output rises above 90% of nominal.
3. From power on or negation of Tx Fault using Tx Disable.
4. Time from fault to Tx fault on.
5. Time Tx Disable must be held high to reset Tx_fault.
6. Time from LOS state to Rx LOS assert.
7. Time from non-LOS state to RX LOS deassert.
9
VCC > 3.15 V
VCC > 3.15 V
TX_FAULT
TX_FAULT
TX_DISABLE
TX_DISABLE
TRANSMITTED SIGNAL
TRANSMITTED SIGNAL
t_init
t_init
t-init: TX DISABLE NEGATED
t-init: TX DISABLE ASSERTED
VCC > 3.15 V
TX_FAULT
TX_FAULT
TX_DISABLE
TX_DISABLE
TRANSMITTED SIGNAL
TRANSMITTED SIGNAL
t_off
t_init
t_on
INSERTION
t-init: TX DISABLE NEGATED, MODULE HOT PLUGGED
t-off & t-on: TX DISABLE ASSERTED THEN NEGATED
OCCURANCE OF FAULT
OCCURANCE OF FAULT
TX_FAULT
TX_FAULT
TX_DISABLE
TX_DISABLE
TRANSMITTED SIGNAL
TRANSMITTED SIGNAL
t_fault
* SFP SHALL CLEAR TX_FAULT IN
t_init IF THE FAILURE IS TRANSIENT
t-fault: TX FAULT ASSERTED, TX SIGNAL NOT RECOVERED
t_reset
t_init*
t-reset: TX DISABLE ASSERTED THEN NEGATED, TX SIGNAL RECOVERED
OCCURANCE OF FAULT
OPTICAL SIGNAL
TX_FAULT
OCCURANCE OF LOSS
TX_DISABLE
LOS
TRANSMITTED SIGNAL
t_fault2
t_loss_on
t_reset
* SFP SHALL CLEAR Tx_FAULT IN
t_init IF THE FAILURE IS TRANSIENT
t-fault2: TX DISABLE ASSERTED THEN NEGATED,
TX SIGNAL NOT RECOVERED
t_init*
t-loss-on & t-loss-off
NOTE: t_fault2 timing is typically 1.7 to 2 ms.
Figure 6. Transceiver timing diagrams (Module installed except where noted).
10
t_loss_off
Table 9. EEPROM Serial ID Memory Contents
Address
Hex
0
ASCII
Address
Hex
03
32
1
04
2
ASCII
Address
Hex
20
64
33
20
07
34
3
00
4
Address
Hex
00
96
Note 4
65
1A
97
Note 4
20
66
00
98
Note 4
35
20
67
00
99
Note 4
00
36
00
68
Note 1
100
Note 4
5
00
37
00
69
Note 1
101
Note 4
6
01
38
30
70
Note 1
102
Note 4
7
20
39
D3
71
Note 1
103
Note 4
8
40
40
48
H
72
Note 1
104
Note 4
9
0C
41
46
F
73
Note 1
105
Note 4
10
00
42
42
B
74
Note 1
106
Note 4
11
01
43
52
R
75
Note 1
107
Note 4
12
0C
44
2D
-
76
Note 1
108
Note 4
13
00
45
35
5
77
Note 1
109
Note 4
14
00
46
37
7
78
Note 1
110
Note 4
15
00
47
31
1
79
Note 1
111
Note 4
16
37
48
30
0
80
Note 1
112
Note 4
17
1B
49
4C
L
81
Note 1
113
Note 4
18
00
50
20
82
Note 1
114
Note 4
19
00
51
20
83
Note 1
115
Note 4
20
41
A
52
20
84
Note 2
116
Note 4
21
47
G
53
20
85
Note 2
117
Note 4
22
49
I
54
20
86
Note 2
118
Note 4
23
4C
L
55
20
87
Note 2
119
Note 4
24
45
E
56
20
88
Note 2
120
Note 4
25
4E
N
57
20
89
Note 2
121
Note 4
26
54
T
58
20
90
Note 2
122
Note 4
27
20
59
20
91
Note 2
123
Note 4
28
20
60
00
92
00
124
Note 4
29
20
61
00
93
00
125
Note 4
30
20
62
00
94
00
126
Note 4
31
20
63
A9
95
Note 3
127
Note 4
Notes:
1. These addresses are reserved for serial number information and will vary from module to module.
2. These addresses are reserved for date code information and may vary from lot to lot.
3. Byte address 95 is a check sum which may vary from module to module.
4. These fields are reserved for future use by Agilent Technologies.
11
ASCII
ASCII
AGILENT HFBR-5710L
850 nm LASER PROD
21CFR(J) CLASS 1
COUNTRY OF ORIGIN YYWW
TUV
XXXXXX
UL
TX
13.40 ± 0.1
(0.53 ± 0.004)
RX
13.75 ± 0.1
(0.54 ± 0.004)
56.40 ± 0.2
(2.22 ± 0.01)
SEE DETAIL 1
TCASE REFERENCE POINT
AREA
FOR
PROCESS
PLUG
14.8 MAX. UNCOMPRESSED
(0.58)
13.0 ± 0.1
(0.51 ± 0.004)
14.20 ± 0.1
(0.56 ± 0.004)
DETAIL 1
SCALE 2x
0.7 MAX. UNCOMPRESSED
(0.03)
8.50 ± 0.1
(0.33 ± 0.004)
DIMENSIONS ARE IN MILLIMETERS (INCHES)
Figure 7. Module drawing.
12
FRONT EDGE OF SFP
TRANSCEIVER CAGE
6.25 ± 0.05
(0.25 ± 0.002)
11.80 ± 0.2
(0.46 ± 0.008)
TX
RX
X
Y
34.5
3x 10
7.2
10x 1.05 ± 0.01
∅ 0.1 S X A S
B
1
16.25
MIN. PITCH
7.1
∅ 0.85 ± 0.05
∅ 0.1 S X Y
A
1
2.5
2.5
PCB
EDGE
3.68
5.68
20
PIN 1
8.58
11.08
16.25 14.25
REF.
2x 1.7
8.48
9.6
4.8
11
10
11.93
SEE DETAIL 1
11x 2.0
11x 2.0
9x 0.95 ± 0.05
∅ 0.1 L X A S
5
26.8
3
2
3x 10
41.3
42.3
5
3.2
0.9
20x 0.5 ± 0.03
0.06 S A S B S
NOTES:
9.6
1.PADS AND VIAS ARE CHASSIS GROUND.
20
PIN 1
10.53
10.93
11.93
0.8
TYP.
2.THROUGH HOLES, PLATING OPTIONAL.
3.HATCHED AREA DENOTES COMPONENT AND
TRACE KEEPOUT (EXCEPT CHASSIS GROUND).
11
10
4.AREA DENOTES COMPONENT KEEPOUT
(TRACES ALLOWED).
4
2 ± 0.05 TYP.
0.06 L A S B S
2x 1.55 ± 0.05
∅ 0.1 L A S B S
DETAIL 1
Figure 8. SFP host board mechanical layout.
13
DIMENSIONS IN MILLIMETERS
1.7 ± 0.9
(0.07 ± 0.04)
3.5 ± 0.3
(0.14 ± 0.01)
PCB
41.73 ± 0.5
(1.64 ± 0.02)
BEZEL
15 MAX.
(0.59)
AREA
FOR
PROCESS
PLUG
CAGE ASSEMBLY
15.25 ± 0.1
(0.60 ± 0.004)
11 REF.
(0.43)
10.4 ± 0.1
(0.41 ± 0.004)
9.8
MAX.
(0.39)
1.5 REF.
(0.06)
BELOW PCB
10 REF
(0.39)
TO PCB
0.4 ± 0.1
(0.02 ± 0.004)
BELOW PCB
16.25 ± 0.1 MIN. PITCH
(0.64 ± 0.004)
MSA-SPECIFIED BEZEL
DIMENSIONS ARE IN MILLIMETERS (INCHES).
Figure 9. Assembly drawing.
Figure 10. The extended de-latch for belly to belly application.
14
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2001 Agilent Technologies, Inc.
June 26, 2001
Obsoletes 5988-2462EN
5988-3323EN