Pb Free Plating Product ISSUED DATE :2005/07/01 REVISED DATE :2005/09/29B N-CH BVDSS 30V N-CH RDS(ON) 50m N-CH ID 5A P-CH BVDSS -30V N-CH RDS(ON) 70m N-CH ID -4A GSS4532 N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET Description The GSS4532 provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SOP-8 package is universally preferred for all commercial-industrial surface mount applications and suited for low voltage applications such as DC/DC converters. Features *Simple Drive Requirement *Lower On-resistance *Fast Switching Package Dimensions REF. A B C D E F Millimeter Min. Max. 5.80 4.80 3.80 0 0.40 0.19 Absolute Maximum Ratings Parameter Symbol Drain-Source Voltage VDS Gate-Source Voltage VGS 6.20 5.00 4.00 8 0.90 0.25 Ratings N-channel P-channel 30 -30 20 20 REF. M H L J K G Millimeter Min. Max. 0.10 0.25 0.35 0.49 1.35 1.75 0.375 REF. 45 1.27 TYP. Unit V V Continuous Drain Current 3 ID @TA=25 5 -4 A Continuous Drain Current 3 ID @TA=70 4 -3.2 A 20 -20 A Pulsed Drain Current 1,4 IDM PD @TA=25 Total Power Dissipation Linear Derating Factor 2.0 0.016 Operating Junction and Storage Temperature Range Tj, Tstg -55 ~ +150 Symbol Value Rthj-a 62.5 W W/ Thermal Data Parameter Thermal Resistance Junction-ambient GSS4532 Max. Unit /W Page: 1/9 ISSUED DATE :2005/07/01 REVISED DATE :2005/09/29B N-Channel Electrical Characteristics(Tj = 25 Parameter Unless otherwise specified) Symbol Min. Typ. Max. Unit Drain-Source Breakdown Voltage BVDSS 30 - - V Breakdown Voltage Temperature Coefficient BVDSS / Tj - 0.037 - Gate Threshold Voltage VGS(th) 1.0 - 3.0 V VDS=VGS, ID=250uA gfs - 8 - S VDS=10V, ID=5A IGSS - - 100 nA VGS= - - 1 uA VDS=30V, VGS=0 - - 25 uA VDS=24V, VGS=0 - - 50 - - 70 Forward Transconductance Gate-Source Leakage Current Drain-Source Leakage Current(Tj=25 ) Drain-Source Leakage Current(Tj=55 ) Static Drain-Source On-Resistance IDSS RDS(ON) V/ m Test Conditions VGS=0, ID=250uA Reference to 25 , ID=1mA 20V VGS=10V, ID=5A VGS=4.5V, ID=4.2A Total Gate Charge2 Qg - 10.2 - Gate-Source Charge Qgs - 1.2 - Gate-Drain (“Miller”) Change Qgd - 3.4 - Td(on) - 6 - Tr - 9 - Td(off) - 15 - Tf - 5.5 - Input Capacitance Ciss - 240 - Output Capacitance Coss - 145 - Reverse Transfer Capacitance Crss - 55 - Symbol Min. Typ. Max. Unit VSD - - 1.2 V IS=1.7A, VGS=0V, Tj=25 IS - - 1.7 A VD=VG=0V, VS=1.2V ISM - - 20 A Turn-on Delay Time2 Rise Time Turn-off Delay Time Fall Time nC ID=5A VDS=10V VGS=10V ns VDS=10V ID=1A VGS=10V RG=6 RD=10 pF VGS=0V VDS=25V f=1.0MHz Source-Drain Diode Parameter 2 Forward On Voltage Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) 1 Test Conditions Notes: 1. Pulse width limited by Max. junction temperature. 2. Pulse width 300us, duty cycle 2%. 3. Surface mounted on FR4 board, t 10sec. 4. Pulse width 10us, duty cycle 1%. GSS4532 Page: 2/9 ISSUED DATE :2005/07/01 REVISED DATE :2005/09/29B P-Channel Electrical Characteristics(Tj = 25 Parameter Unless otherwise specified) Symbol Min. Typ. Max. Unit Drain-Source Breakdown Voltage BVDSS -30 - - V Breakdown Voltage Temperature Coefficient BVDSS / Tj - -0.028 - Gate Threshold Voltage VGS(th) -1.0 - -3.0 V VDS=VGS, ID=-250uA gfs - 5 - S VDS=-10V, ID=-4A IGSS - - 100 nA VGS= - - -1 uA VDS=-30V, VGS=0 - - -25 uA VDS=-24V, VGS=0 - - 70 - - 90 Forward Transconductance Gate-Source Leakage Current Drain-Source Leakage Current(Tj=25 ) Drain-Source Leakage Current(Tj=55 ) Static Drain-Source On-Resistance IDSS RDS(ON) V/ m Test Conditions VGS=0, ID=-250uA Reference to 25 , ID=-1mA 20V VGS=-10V, ID=-4A VGS=-4.5V, ID=-3A Total Gate Charge2 Qg - 18.3 - Gate-Source Charge Qgs - 3.6 - Gate-Drain (“Miller”) Change Qgd - 1.5 - Td(on) - 8 - Tr - 9 - Td(off) - 21 - Tf - 10 - Input Capacitance Ciss - 760 - Output Capacitance Coss - 345 - Reverse Transfer Capacitance Crss - 90 - Symbol Min. Typ. Max. Unit VSD - - -1.2 V IS=-1.7A, VGS=0V, Tj=25 IS - - -1.7 A VD=VG=0V, VS=-1.2V ISM - - -20 A Turn-on Delay Time2 Rise Time Turn-off Delay Time Fall Time nC ID=-4A VDS=-10V VGS=-10V ns VDS=-10V ID=-1A VGS=-10V RG=6 RD=10 pF VGS=0V VDS=-25V f=1.0MHz Source-Drain Diode Parameter 2 Forward On Voltage Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) 1 Test Conditions Notes: 1. Pulse width limited by Max. junction temperature. 2. Pulse width 300us, duty cycle 2%. 3. Surface mounted on FR4 board, t 10sec. 4. Pulse width 10us, duty cycle 1%. GSS4532 Page: 3/9 ISSUED DATE :2005/07/01 REVISED DATE :2005/09/29B Characteristics Curve N-Channel Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature Fig 5. Maximum Drain Current v.s. Case Temperature Fig 6. Type Power Dissipation GSS4532 Page: 4/9 ISSUED DATE :2005/07/01 REVISED DATE :2005/09/29B N-Channel Fig 7. Maximum Safe Operating Area Fig 9. Gate Charge Characteristics Fig 11. Forward Characteristics of Reverse Diode GSS4532 Fig 8. Effective Transient Thermal Impedance Fig 10. Typical Capacitance Characteristics Fig 12. Gate Threshold Voltage v.s. Junction Temperature Page: 5/9 ISSUED DATE :2005/07/01 REVISED DATE :2005/09/29B N-Channel GSS4532 Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform Page: 6/9 ISSUED DATE :2005/07/01 REVISED DATE :2005/09/29B P-Channel Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature Fig 5. Maximum Drain Current v.s. Case Temperature Fig 6. Type Power Dissipation GSS4532 Page: 7/9 ISSUED DATE :2005/07/01 REVISED DATE :2005/09/29B P-Channel Fig 7. Maximum Safe Operating Area Fig 9. Gate Charge Characteristics Fig 11. Forward Characteristics of Reverse Diode GSS4532 Fig 8. Effective Transient Thermal Impedance Fig 10. Typical Capacitance Characteristics Fig 12. Gate Threshold Voltage v.s. Junction Temperature Page: 8/9 ISSUED DATE :2005/07/01 REVISED DATE :2005/09/29B P-Channel Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform Important Notice: All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of GTM. GTM reserves the right to make changes to its products without notice. GTM semiconductor products are not warranted to be suitable for use in life-support Applications, or systems. GTM assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. Head Office And Factory: Taiwan: No. 17-1 Tatung Rd. Fu Kou Hsin-Chu Industrial Park, Hsin-Chu, Taiwan, R. O. C. TEL : 886-3-597-7061 FAX : 886-3-597-9220, 597-0785 China: (201203) No.255, Jang-Jiang Tsai-Lueng RD. , Pu-Dung-Hsin District, Shang-Hai City, China TEL : 86-21-5895-7671 ~ 4 FAX : 86-21-38950165 GSS4532 Page: 9/9