IMAGE SENSOR CCD area image sensor S9972/S9973 series Front-illuminated FFT-CCD, high IR sensitivity S9972/S9973 series are families of FFT-CCD image sensors specifically designed for low-light-level detection in scientific applications. By using the binning operation, S9972/S9973 series can be used as a linear image sensor having a long aperture in the direction of the device length. This makes S9972/S9973 series ideally suited for use in spectrophotometry. The binning operation offers significant improvement in S/N and signal processing speed compared with conventional methods by which signals are digitally added by an external circuit. S9972/S9973 series also feature low noise and low dark signal (MPP mode operation). This enables low-light-level detection and long integration time, thus achieving a wide dynamic range. S9972/S9973 series have an effective pixel size of 24 × 24 µm and are available in image areas of 24.576 (H) × 2.976 (V) mm2 (1024 × 124 pixels) and 24.576 (H) × 6.048 (V) mm 2 (1024 × 252 pixels). S9972/S9973 series are pin compatible with S9970/S9971 series. (Operating conditions and characteristics are a little bit different from S9970/S9971 series.) Features Applications l 1024 (H) × 124 (V) and 1024 (H) × 252 (V) pixel format l Pixel size: 24 × 24 µm l Line/pixel binning l 100 % fill factor l Wide dynamic range l Low dark signal l Low readout noise l MPP operation l High IR sensitivity l Fluorescence spectrometer, ICP l Raman spectrometer l Industrial inspection requiring l Semiconductor inspection l DNA sequencer l Low-light-level detection ■ Selection guide Type No. S9972-1007 S9972-1008 S9973-1007 S9973-1008 Cooling Non-cooled One-stage TE-cooled Number of total pixels Number of active pixels 1044 × 128 1044 × 256 1044 × 128 1044 × 256 1024 × 124 1024 × 252 1024 × 124 1024 × 252 Active area [mm (H) × mm (V)] 24.576 × 2.976 24.576 × 6.048 24.576 × 2.976 24.576 × 6.048 ■ General ratings Parameter Pixel size Vertical clock phase Horizontal clock phase Output circuit Package Specification 24 (H) × 24 (V) µm 2 phase 2 phase One-stage MOSFET source follower 24 pin ceramic DIP (refer to dimensional outlines) S9972 series: quartz glass Window *1 S9973 series: sapphire glass *1: Temporary window type and UV coat type are available upon request. (Temporary window is fixed by tape to protect the CCD chip and wire bonding.) Temporary window type: expressed by “N” ex. S9972-1007N UV coat type: expressed by “UV” ex. S9972-1007UV PRELIMINARY DATA Nov. 2005 1 CCD area image sensor S9972/S9973 series ■ Absolute maximum ratings (Ta=25 °C) Parameter Operating temperature Storage temperature OD voltage RD voltage ISV voltage ISH voltage IGV voltage IGH voltage SG voltage OG voltage RG voltage TG voltage Vertical clock voltage Horizontal clock voltage Symbol Topr Tstg VOD VRD VISV VISH VIG1V, VIG2V VIG1H, VIG2H VSG VOG VRG VTG VP1V, VP2V VP1H, VP2H Min. -50 -50 -0.5 -0.5 -0.5 -0.5 -15 -15 -15 -15 -15 -15 -15 -15 Typ. - Max. +30 +70 +25 +18 +18 +18 +15 +15 +15 +15 +15 +15 +15 +15 Unit °C °C V V V V V V V V V V V V Symbol VOD VRD VOG VSS VISV VISH VIG1V, VIG2V VIG1H, VIG2H VP1VH, VP2VH VP1VL, VP2VL VP1HH, VP2HH VP1HL, VP2HL VSGH VSGL VRGH VRGL VTGH VTGL Min. 18 12 -0.5 -8 -8 0 -9 0 -9 0 -9 0 -9 0 -9 Typ. 20 13 0 0 VRD VRD 0 0 4 -8 4 -8 4 -8 4 -8 4 -8 Max. 22 14 2 6 -7 6 -7 6 -7 6 -7 6 -7 Unit V V V V V V V V ■ Operating conditions (MPP mode, Ta=25 °C) Parameter Output transistor drain voltage Reset drain voltage Output gate voltage Substrate voltage Test point (vertical input source) Test point (horizontal input source) Test point (vertical input gate) Test point (horizontal input gate) Vertical shift register clock voltage Horizontal shift register clock voltage Summing gate voltage Reset gate voltage Transfer gate voltage High Low High Low High Low High Low High Low V V V V V ■ Electrical characteristics (Ta=25 °C) Parameter Symbol Remark Min. Signal output frequency fc S9972/S9973-1007 Vertical shift register CP1V, CP2V capacitance S9972/S9973-1008 Horizontal shift register capacitance CP1H, CP2H Summing gate capacitance CSG Reset gate capacitance CRG Transfer gate capacitance CTG Transfer efficiency CTE *2 0.99995 DC output level Vout *3 12 Output impedance Zo *3 Power dissipation P *3, *4 *2: Charge transfer efficiency per pixel, measured at half of the full well capacity. *3: The values depend on the load resistance. (VOD=20 V, Load resistance=10 kΩ) *4: Power dissipation of the on-chip amplifier. 2 Typ. 0.1 1600 3200 180 7 7 100 0.99999 15 3 15 Max. 1 Unit MHz pF 18 - pF pF pF pF V kΩ mW CCD area image sensor S9972/S9973 series ■ Electrical and optical characteristics (Ta=25 °C, unless otherwise noted) Parameter Symbol Remark Min. Typ. Max. Unit Saturation output voltage Vsat Fw × Sv V Vertical 120 240 Full well Fw kecapacity Horizontal 240 480 CCD node sensitivity Sv *5 2.8 µV/e+25 °C 2000 30000 Dark current DS *6 e-/pixel/s (MPP mode) 0 °C 100 1500 Readout noise Nr *7 4 18 e-rms Line binning 13333 120000 Dynamic range *8 Area scanning 6667 60000 Spectral response range 400 to 1100 nm λ Photo response non-uniformity PRNU *9 ±10 % Point defects *10 0 Blemish Cluster defects *11 0 Column defects *12 0 *5: VOD=20 V , Load resistance=10 kΩ *6: Dark current nearly doubles for every 5 to 7 °C increase in temperature. *7: -40 °C, operating frequency is 80 kHz. *8: DR = Fw / Nr *9: Measured at half of the full well capacity. PRNU = noise / signal × 100 [%], noise: fixed pattern noise (peak to peak) *10: White spots > 3 % of full well at 0 °C after Ts=1 s Black spots Pixels whose sensitivity is lower than one-half of the average pixel output (Measured with uniform light producing one-half of the saturation charge) *11: 2 to 9 contiguous defective pixels *12: 10 or more contiguous defective pixels ■ Spectral response (without window) (Typ. Ta=25 ˚C) 50 S9970/S9971 SERIES (Typ. Ta=25 ˚C) 100 S9972/S9973 SERIES 90 80 40 TRANSMITTANCE (%) QUANTUM EFFICIENCY (%) ■ Spectral transmittance characteristics 30 20 QUARTZ WINDOW 70 SAPPHIRE WINDOW 60 50 40 30 20 10 10 0 200 300 400 500 600 700 800 900 1000 1100 1200 0 100 200 300 400 500 600 700 800 900 1000 WAVELENGTH (nm) WAVELENGTH (nm) KMPDB0257EC KMPDB0101EA 3 CCD area image sensor S9972/S9973 series ■ Device structure, line output format IG1V IG2V ISV 24 23 22 SS 20 TG 16 P1V 15 P2V 14 ...... V 1 RD 2 OS 3 ...... H D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 RG D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 1 V=124, 252 H=1024 ...... 13 ISH 12 IG1H 4 OD 6 SG 5 OG 9 10 11 IG2H 2 ISOLATION P2H P1H 1024 4 OPTICAL SIGNAL OUT 4 BLANK BLACK 2 ISOLATION 4 BLANK 4 OPTICAL BLACK KMPDC0237EA Pixel format Blank 4 Left ← Horizontal Direction → Right Isolation Effective Isolation 2 1024 2 Optical Black 4 Optical Black 4 Top ← Vertical Direction → Bottom Isolation Effective Isolation 2 124 or 252 2 ■ Timing chart Line binning INTEGRATION PERIOD (Shutter must be open) VERTICAL BINNING PERIOD (Shutter must be closed) 3..126 3..254 Tpwv 1 P1V 127 255 READOUT PERIOD (Shutter must be closed) 128← 124 + 4 (ISOLATION): S9972/S9973-1007 256← 252 + 4 (ISOLATION): S9972/S9973-1008 2 Tovr P2V, TG Tpwh, Tpws P1H 1 2 4..1042 1043 1044: S9972/S9973-1007/-1008 3 P2H, SG Tpwr RG OS D1 D2 D19 D3..D10, S1..S1024, D11..D18 D20 KMPDC0238EA 4 Blank 4 S9972/S9973 series CCD area image sensor Area scanning 1: low dark current mode INTEGRATION PERIOD (Shutter must be open) READOUT PERIOD (Shutter must be closed) 4..127 128←124 + 4 (ISOLATION): S9972/S9973-1007 4..255 256←252 + 4 (ISOLATION): S9972/S9973-1008 Tpwv 1 2 3 P1V P2V, TG P1H P2H, SG RG OS Tovr P2V, TG ENLARGED VIEW Tpwh, Tpws P1H P2H, SG Tpwr RG OS D1 D2 D3 D4 D18 D5..D10, S1..S1024, D11..D17 D19 D20 KMPDC0239EA Area scanning 2: large full well mode INTEGRATION PERIOD (Shutter must be open) READOUT PERIOD (Shutter must be closed) 4..127 128←124 + 4 (ISOLATION): S9972/S9973-1007 4..255 256←252 + 4 (ISOLATION): S9972/S9973-1008 Tpwv 1 2 3 P1V P2V, TG P1H P2H, SG RG OS Tovr P2V, TG ENLARGED VIEW Tpwh, Tpws P1H P2H, SG Tpwr RG OS D1 D2 D3 D4 D18 D5..D10, S1..S1024, D11..D17 D19 D20 KMPDC0240EA Parameter P1V, P2V, TG Pulse width S9972/S9973-1007 S9972/S9973-1008 Symbol Remark Tpwv *13 Rise and fall time Tprv, Tpfv Pulse width Tpwh P1H, P2H Rise and fall time Tprh, Tpfh Duty ratio Pulse width Tpws SG Rise and fall time Tprs, Tpfs Duty ratio Pulse width Tpwr RG Rise and fall time Tprr, Tpfr TG - P1H Overlap time Tovr *13: The clock pulses should be overlapped at 50 % of clock pulse amplitude. *14: P2H and SG should have the same electrical specifications. *13 *14 - Min. 6.0 12 200 500 10 500 10 100 5 3 Typ. 18 36 5000 50 5000 50 500 6 Max. - Unit µs ns ns ns % ns ns % ns ns µs 5 CCD area image sensor S9972/S9973 series ■ Dimensional outlines (unit: mm) S9972-1007 PHOTOSENSITIVE SURFACE 1.1 ± 0.3 10.05 ± 0.25 2.976 ACTIVE AREA 24.576 40.64 ± 0.41 1st PIN INDICATION PAD 3.0 PHOTOSENSITIVE SURFACE 0.46 2.54 27.94 KMPDA0204EA S9972-1008 PHOTOSENSITIVE SURFACE 6.048 1.1 ± 0.3 14.99 ± 0.25 ACTIVE AREA 24.576 40.64 ± 0.41 1st PIN INDICATION PAD 3.0 PHOTOSENSITIVE SURFACE 0.51 2.54 27.94 KMPDA0205EA S9973-1007 ACTIVE AREA 24.576 12.0 14.99 ± 0.25 7.1 4.0 2.976 3.2 ± 0.4 5.0 40.64 ± 0.41 58.84 1st PIN INDICATION PAD 7.65 ± 0.5 PHOTOSENSITIVE SURFACE TE-COOLER 0.46 2.54 27.94 6 KMPDA0206EA CCD area image sensor S9972/S9973 series S9973-1008 WINDOW 28.6 22.4 22.9 7.3 19.0 6.7 4.0 8.2 6.048 ACTIVE AREA 24.576 2.54 44.0 52.0 60.0 1.0 TE-COOLER 7.7 PHOTOSENSITIVE SURFACE 5.3 1st PIN INDICATION PAD (24×) 0.5 KMPDA0198EA ■ Pin connections S9972 series S9973 series Remark Symbol Description Symbol Description 1 RG Reset gate RG Reset gate 2 RD Reset drain RD Reset drain 3 OS Output transistor source OS Output transistor source 4 OD Output transistor drain OD Output transistor drain 5 OG Output gate OG Output gate 6 SG Summing gate SG Summing gate Same timing as P2H 7 NC Th1 Thermistor 8 NC Th2 Thermistor 9 P2H CCD horizontal register clock-2 P2H CCD horizontal register clock-2 10 P1H CCD horizontal register clock-1 P1H CCD horizontal register clock-1 11 IG2H Test point (horizontal input gate-2) IG2H Test point (horizontal input gate-2) Shorted to GND 12 IG1H Test point (horizontal input gate-1) IG1H Test point (horizontal input gate-1) Shorted to GND 13 ISH Test point (horizontal input source) ISH Test point (horizontal input source) Shorted to RD 14 P2V CCD vertical register clock-2 P2V CCD vertical register clock-2 15 P1V CCD vertical register clock-1 P1V CCD vertical register clock-1 16 TG *15 Transfer gate TG *15 Transfer gate Same timing as P2V 17 NC NC 18 NC PTE-cooler19 NC P+ TE-cooler+ 20 SS Substrate (GND) SS Substrate (GND) 21 NC NC 22 ISV Test point (vertical input source) ISV Test point (vertical input source) Shorted to RD 23 IG2V Test point (vertical input gate-2) IG2V Test point (vertical input gate-2) Shorted to GND 24 IG1V Test point (vertical input gate-1) IG1V Test point (vertical input gate-1) Shorted to GND *15: TG is an isolation gate between vertical register and horizontal register. In standard operation, the same pulse as P2V should be applied to TG. Pin No. 7 CCD area image sensor S9972/S9973 series ■ Specifications of built-in TE-cooler (Typ.) Parameter Symbol Condition S9973-1007 S9973-1008 Unit Internal resistance Rint Ta=25 °C 6.0 1.2 Ω Maximum current *16 Imax Tc *17=Th *18=25 °C 1.5 3.0 A Maximum voltage Vmax Tc *17=Th *18=25 °C 8.8 3.6 V Maximum heat Qmax 6.7 5.1 W absorption *19 Maximum temperature 70 °C of hot side *16: Maximum current Imax: If the current is greater than Imax, the heat absorption begins to decrease due to the Joule heat. It should be noted that this value is not a damage threshold. To protect the thermoelectric cooler and maintain stable operation, the supply current should be less than 60 % of this maximum current. *17: Temperature of cool side of thermoelectric cooler *18: Temperature of hot side of thermoelectric cooler *19: Maximum heat absorption Qmax This is a heat absorption when the maximum current is supplied to the TE-cooler. ■ TE-cooler characteristics S9973-1008 (Typ. Ta=25 ˚C) 10 VOLTAGE vs. CURRENT CCD TEMPERATURE vs. CURRENT 0 4 -10 2 -20 0 0 0.5 1.0 1.5 -30 2.0 20 5 10 4 0 3 -10 2 -20 1 -30 0 0 1 2 3 4 -40 CURRENT (A) CURRENT (A) KMPDB0177EB 8 VOLTAGE (V) 6 30 VOLTAGE vs. CURRENT CCD TEMPERATURE vs. CURRENT 6 10 CCD TEMPERATURE (˚C) VOLTAGE (V) 8 (Typ. Ta=25 ˚C) 7 20 CCD TEMPERATURE (˚C) S9973-1007 KMPDB0179EB CCD area image sensor S9972/S9973 series ■ Specifications of built-in temperature sensor A chip thermistor is built in the same package with a CCD chip, and the CCD chip temperature can be monitored with it. A relation between the thermistor resistance and absolute temperature is expressed by the following equation. RESISTANCE The characteristics of the thermistor used are as follows. R (298K) = 10 kΩ B (298K / 323K) = 3450 K (Typ. Ta=25 ˚C) 1 MΩ R1 = R2 × expB (1 / T1 - 1 / T2) where R1 is the resistance at absolute temperature T1 (K) R2 is the resistance at absolute temperature T2 (K) B is so-called the B constant (K) 100 kΩ 10 kΩ 220 240 260 280 300 TEMPERATURE (K) KMPDB0111EA ■ Precaution for use (Electrostatic countermeasures) ● Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist strap, in order to prevent electrostatic damage due to electrical charges from friction. ● Avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge. ● Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to discharge. ● Ground the tools used to handle these sensors, such as tweezers and soldering irons. It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the amount of damage that occurs. ■ Element cooling/heating temperature incline rate When cooling the CCD by an externally attached cooler, set the cooler operation so that the temperature gradient (rate of temperature change) for cooling or allowing the CCD to warm back is less than 5 K/minute. Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2006 Hamamatsu Photonics K.K. HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, www.hamamatsu.com U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 Cat. No. KMPD1092E03 Jun. 2006 DN 9