HANBIT HMD4M64D16E

HANBiT
HMD4M64D16E
32Mbyte(4Mx64) EDO Mode 4K Ref. 5V, DIMM 168 pin
Part No. HMD4M64D16E
GENERAL DESCRIPTION
The HMD4M64D16E is a 4Mx64bits Dynamic RAM high density memory module. The HMD4M64D16E consists of
sixteen CMOS 4Mx4bits DRAMs in SOJ/TSOPІІ 400mil packages mounted on a 168-pin glass-epoxy substrate. A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The HMD4M64D16E is a Dual In-line
Memory Module and is intended for mounting into 168 pin edge connector sockets
FEATURES
PERFORMANCE RANGE
w Part Identification
SPEED
tRAC
tCAC
tRC
tHPC
-5
50ns
15ns
84ns
20ns
-6
60ns
17ns
104ns
25ns
HMD4M64D16E --- 4KCycles/64ms Ref, Gold Plate Lead
w High-density 32MByte design
w New JEDEC standard proposal without buffer
w CAS-before-RAS Refresh capability
w RAS-only and Hidden refresh capability
w Single +5± 0.5V power supply
w Timing
w EDO mode operation.
50ns access
w LVTTL compatible inputs and outputs
-5
60ns access
w FR4-PCB design
w Packages
w Access times : 50, 60ns
168-pin DIMM
-6
D
PIN NAMES
Pin Name
A0-A11
Function
Address
Pin Name
Function
Pin Name
Function
Input
(4k
/RAS0, /RAS2
Row Address Strobe
Vss
Ground
Input
(8k
/CAS0 - /CAS7
Column
NC
No Connection
ref)
A0-A12
Address
ref)
Address
Strobe
/WE0,/WE2
Read/Write Enable
SCL
Serial Clock
Vcc
Power (+5V)
/OE0,/OE2
Output Enable
DU
Don't use
SDA
Serial Address /Data
I/O
SA0 – SA2
Address in EEPROM
URL:www.hbe.co.kr
REV.1.0 (August.2002)
CB0 - CB7
Check Bit
-1-
DQ0-DQ63
Data In/Out
HANBit Electronics Co.,Ltd.
HANBiT
HMD4M64D16E
PIN ASSIGNMENT
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
1
Vss
29
/CAS1
57
DQ18
85
Vss
113
/CAS5
141
DQ50
2
DQ0
30
/RAS0
58
DQ19
86
DQ32
114
/RAS1
142
DQ51
3
DQ1
31
/OE0
59
Vcc
87
DQ33
115
NC
143
Vcc
4
DQ2
32
Vss
60
DQ20
88
DQ34
116
Vss
144
DQ52
5
DQ3
33
A0
61
NC
89
DQ35
117
A1
145
NC
6
Vcc
34
A2
62
NC
90
Vcc
118
A3
146
NC
7
DQ4
35
A4
63
NC
91
DQ36
119
A5
147
NC
8
DQ5
36
A6
64
Vss
92
DQ37
120
A7
148
Vss
9
DQ6
37
A8
65
DQ21
93
DQ38
121
A9
149
DQ53
10
DQ7
38
A10
66
DQ22
94
DQ39
122
A11
150
DQ54
11
DQ8
39
NC
67
DQ23
95
DQ40
123
NC
151
DQ55
12
Vss
40
Vcc
68
Vss
96
Vss
124
Vcc
152
Vss
13
DQ9
41
Vcc
69
DQ24
97
DQ41
125
NC
153
DQ56
14
DQ10
42
NC
70
DQ25
98
DQ42
126
NC
154
DQ57
15
DQ11
43
Vss
71
DQ26
99
DQ43
127
Vss
155
DQ58
16
DQ12
44
/OE2
72
DQ27
100
DQ44
128
NC
156
DQ59
17
DQ13
45
/RAS2
73
Vcc
101
DQ45
129
/RAS3
157
Vcc
18
Vcc
46
/CAS2
74
DQ28
102
Vcc
130
/CAS6
158
DQ60
19
DQ14
47
/CAS3
75
DQ29
103
DQ46
131
/CAS7
159
DQ61
20
DQ15
48
/WE2
76
DQ30
104
DQ47
132
NC
160
DQ62
21
NC
49
Vcc
77
DQ31
105
NC
133
Vcc
161
DQ63
22
NC
50
NC
78
Vss
106
NC
134
NC
162
Vss
23
Vss
51
NC
79
NC
107
Vss
135
NC
163
NC
24
NC
52
NC
80
NC
108
NC
136
NC
164
NC
25
NC
53
NC
81
NC
109
NC
137
NC
165
SA0
26
Vcc
54
Vss
82
SDA
110
Vcc
138
Vss
166
SA1
27
/WE0
55
DQ16
83
SCL
111
NC
139
DQ48
167
SA2
28
/CAS0
56
DQ17
84
Vcc
112
/CAS4
140
DQ49
168
Vcc
URL:www.hbe.co.kr
REV.1.0 (August.2002)
-2-
HANBit Electronics Co.,Ltd.
HANBiT
HMD4M64D16E
FUNCTIONAL BLOCK DIAGRAM
DQ 0-63
/CAS0
/RAS0
/OE0
/CAS
/RAS
/OE
/W
/CAS
/RAS
/OE
/W
/CAS1
/CAS
/RAS
/OE
/W
/CAS
/RAS
/OE
/W
/CAS
/RAS
/OE
/W
/CAS3
U1
/CAS
/RAS
/OE
/W
/CAS
/RAS
/OE
/W
/CAS4
/RAS2
/OE2
A0 -A11
DQ4-7
/CAS
/RAS
/OE
/W
/CAS
/RAS
U2
/OE
/W
A0 -A11
/CAS
/RAS
/OE
/W
/CAS2
DQ0-3
DQ8-11
/CAS5
A0 -A11
DQ12-15
/CAS
/RAS
/OE
/W
U4
A0 -A11
DQ16-19
/CAS6
U6
A0 -A11
DQ20-23
A0 -A11
DQ24-27
/CAS
/RAS
/OE
/W
/CAS
/RAS
/OE
/W
U7
/CAS7
U8
A0 -A11
DQ28-31
/CAS
/RAS
/OE
/W
/CAS
/RAS
/OE
/W
U9
A0 -A11
U11
A0 -A11
DQ36-39
U12
A0 -A11
/CAS
/RAS
/OE
/W
U3
DQ32-35
DQ40-43
U13
A0 -A11
DQ44-47
U14
A0 -A11
DQ48-51
U16
A0 -A11
DQ52-55
U17
A0 -A11
DQ56-59
U18
A0 -A11
DQ60-63
U19
A0 -A11
/WE
/WE0
A0-A11
Vcc
0.1uF or 0.22uF
Capacitor
To all DRAMs
Vss
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REV.1.0 (August.2002)
-3-
HANBit Electronics Co.,Ltd.
HANBiT
HMD4M64D16E
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN ,OUT
-0.5V to 4.6V
Voltage on Vcc Supply Relative to Vss
Vcc
-0.5V to 4.6V
Power Dissipation
PD
18W
TSTG
-55oC to 150oC
Voltage on Any Pin Relative to Vss
Storage Temperature
Short Circuit Output Current
IOS
50mA
w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to VSS, TA=0 to 70 o C )
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
Supply Voltage
Vcc
4.5
5..
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
VIH
2.4
-
Vcc+1
V
Input Low Voltage
VIL
-1.0
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
HMD4M72D18EG
(4K REF)
SYMBOL
SPEED
MIN
MAX
-5
-
UNITS
1980
mA
1800
mA
ICC1
-6
ICC2
Don't care
-
18
MA
-5
-
1980
mA
1800
mA
1620
mA
1440
mA
ICC3
-6
-5
-
ICC4
-6
ICC5
Don't care
-
9
MA
-5
-
1980
mA
-6
1800
mA
Icc7
L
4500
µA
Iccs
L
3600
µA
ICC6
ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.)
ICC2 : Standby Current ( /RAS=/CAS=VIH )
ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min )
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REV.1.0 (August.2002)
-4-
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HMD4M64D16E
ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min )
ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V )
ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min )
IIL : Input Leakage Current (Any input 0V ≤ VIN ≤ 4.5V, all other pins not under test = 0V)
IOL : Output Leakage Current (Data out is disabled, 0V ≤ VOUT ≤ 3.3V
VOH : Output High Voltage Level (IOH= -2mA )
VOL : Output Low Voltage Level (IOL = 2mA )
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the
output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once
while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
CAPACITANCE
o
( TA=25 C, Vcc = 5V, f = 1Mz )
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance (A0-A11)
CIN1
-
20
pF
Input Capacitance (/W0,/W1,/OE0,/OE2)
C IN2
-
20
pF
Input Capacitance (/RAS0,/RAS2)
CIN3
-
73
pF
Input Capacitance (/CAS0-/CAS7)
CIN4
-
20
pF
Input/Output Capacitance (DQ0-63)
CDQ1
-
17
pF
AC CHARACTERISTICS
o
( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, See notes 1,2.)
-5
STANDARD OPERATION
UNIT
MIN
Random read or write cycle time
-6
SYMBOL
MAX
MIN
MAX
tRC
84
104
ns
Read-modify-write cycle time
tRWC
116
140
ns
Access time from /RAS
tRAC
50
60
ns
Access time from /CAS
tCAC
13
15
ns
Access time from column address
tAA
25
30
ns
/CAS to output in Low-Z
tCLZ
3
3
ns
/OE to output in Low-Z
tOLZ
3
3
ns
Output buffer turn-off delay from /CAS
tOFF
3
13
3
13
ns
Transition time (rise and fall)
tT
2
50
2
50
ns
/RAS precharge time
tRP
30
/RAS pulse width
tRAS
50
/RAS hold time
tRSH
13
15
ns
/CAS hold time
tCSH
38
45
ns
/CAS pulse width
tCAS
8
10K
10
/RAS to /CAS delay time
tRCD
20
37
20
URL:www.hbe.co.kr
REV.1.0 (August.2002)
-5-
40
10K
60
ns
10K
10K
45
ns
ns
ns
HANBit Electronics Co.,Ltd.
HANBiT
HMD4M64D16E
/RAS to column address delay time
tRAD
15
/CAS to /RAS precharge time
tCRP
5
5
ns
Row address set-up time
tASR
0
0
ns
Row address hold time
tRAH
10
10
ns
Column address set-up time
tASC
0
0
ns
Column address hold time
tCAH
8
10
ns
Column address hold referenced to /RAS
tRRH
0
0
ns
Column Address to /RAS lead time
tRAL
25
30
ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
tWCH
10
10
ns
Write command pulse width
tWP
10
10
ns
Write command to /RAS lead time
tRWL
13
15
ns
Write command to /CAS lead time
tCWL
8
10
ns
Data-in set-up time
tDS
0
0
ns
Data-in hold time
tDH
8
10
ns
Refresh period
tREF
Write command set-up time
tWCS
0
0
ns
/CAS to /W delay time
tCWD
30
34
ns
/RAS to /W delay time
tRWD
67
79
ns
Column address to /W delay time
tAWD
42
49
ns
/CAS precharge to /W delay time
tCPWD
47
54
ns
tCSR
5
5
ns
/CAS hold time(/CAS-before-/RAS refresh)
tCHR
10
10
ns
/RAS to /CAS precharge time
tRPC
5
5
ns
Access time from /CAS precharge
tCPA
Hyper page mode cycle time
tHPC
20
25
ns
tHPRWC
47
56
ns
tCP
8
10
ns
/RAS pulse width (Hyper page cycle)
tRASP
50
/RAS hold time from /CAS precharge
tRHCP
30
/OE access time
tOEA
/OE to date delay
tOED
13
Output buffer tune off delay time from /OE
tOEZ
3
/CAS setup time (/CAS-before /RAS
25
15
32
30
32
ns
ms
refresh)
Hyper page mode read-modify write cycle
28
35
ns
time
/CAS precharge time(Hyper page cycle)
URL:www.hbe.co.kr
REV.1.0 (August.2002)
200K
60
35
13
-6-
200K
ns
15
15
13
3
ns
ns
ns
15
ns
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HANBiT
HMD4M64D16E
/OE command hold time
tOEH
13
13
ns
Output data hold time
tDOH
10
10
ns
Output buffer turn off delay from /RAS
tREZ
3
13
3
15
ns
Output buffer turn off delay from /W
tWEZ
3
13
3
15
ns
/W to data delay
tWED
15
15
ns
/OE to /CAS hold time
tOCH
5
5
ns
/CAS hold time to /OE
tCHO
5
5
ns
/OE precharge time
tOEP
5
5
ns
/W pulse width (Hyper page cycle)
tWPE
5
5
ns
NOTES
1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.Input voltage levels are VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times
are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 1TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that tRCD ≥ tRCD(max)
6.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH
or VOL.
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If t WCS ≥ tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle the data output will contain the data
read from the selected address. If neither of the above conditions are satisfied, The condition of the data out is
indeternimated.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference
point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
10. If /RAS goes to high before /CAS high going, the open circuit condition of the output is achieved by /CAS high
going. If /Cas goes to high before /RAS high going, the open circuit condition of the output is achieved by /RAS high
going.
11.tASC ≥ 6ns
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REV.1.0 (August.2002)
-7-
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HMD4M64D16E
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE
/RAS
/CAS
A
/W
/OE
DQ
TIMING WAVEFORM OF WRITE CYCLE (EARLY WRITE)
/RAS
/CAS
A
/W
/OE
DQ
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REV.1.0 (August.2002)
-8-
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HMD4M64D16E
TIMING WAVEFORM OF WRITE CYCLE (/OE CONTROLLED WRITE)
NOTE : Dout = OPEN
/RAS
/CAS
A
/W
/OE
DQ
READ MODIFY WRITE CYCLE
/RAS
/CAS
A
/W
/OE
DQ
URL:www.hbe.co.kr
REV.1.0 (August.2002)
-9-
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HMD4M64D16E
HYPER PAGE READ CYCLE
/RAS
/CAS
A
/W
/OE
DQ
HYPER PAGE WRITE CYCLE (EARLY WRITE)
/RAS
/CAS
A
/W
/OE
DQ
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REV.1.0 (August.2002)
- 10 -
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HMD4M64D16E
HYPER PAGE READ MODIFY WRITE CYCLE
/RAS
/CAS
A
/W
/OE
DQ
HYPER PAGE READ AND WRITE MIXED CYCLE
/RAS
/CAS
A
/W
/OE
DQ
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REV.1.0 (August.2002)
- 11 -
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HMD4M64D16E
/RAS ONLY REFRESH CYCLE
NOTE: /W,/OE,Din = Don't care
Dout = OPEN
/RAS
/CAS
A
/CAS BEFORE /RAS REFRESH CYCLE
NOTE: /OE, A = Don't care
/RAS
/CAS
A
DQ
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REV.1.0 (August.2002)
- 12 -
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HMD4M64D16E
HIDDEN REFRESH CYCLE ( READ)
/RAS
/CAS
A
/W
/OE
DQ
HIDDEN REFRESH CYCLE ( WRITE )
NOTE: Dout = OPEN
/RAS
/CAS
A
/W
/OE
DQ
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REV.1.0 (August.2002)
- 13 -
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HMD4M64D16E
/CAS BEFORE /RAS REFRESH COUNTER TEST CYCLE
/RAS
/CAS
A
READ CYCLE
/W
/OE
DQ
WRITE CYCLE
/W
/OE
DQ
READ-MODIFY-WRITE
/W
/OE
DQ
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REV.1.0 (August.2002)
- 14 -
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HMD4M64D16E
/CAS BEFORE /RAS SELF REFRESH CYCLE
NOTE : /OE, A = Don’t care
/RAS
/CAS
DQ
/W
TEST MODE IN CYCLE
NOTE: /OE, A = Don't care
/RAS
/CAS
/W
DQ
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REV.1.0 (August.2002)
- 15 -
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HMD4M64D16E
PACKAGING INFORMATION
UNIT:mm
±0.2mm
(FRONT VIEW)
3.69
MAX
2.54 mm
0.25 mm MAX
MIN
1.27
Gold : 1.00mm
1.27±0.1 mm
ORDERING INFORMATION
Part Number
Density
Org.
Package
HMD4M72D18EG-5
32MByte
x 72
168 Pin-DIMM
HMD4M72D18EG-6
32MByte
x 72
168 Pin-DIMM
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REV.1.0 (August.2002)
- 16 -
Component
Vcc
MODE
SPEED
18EA
5V
EDO
50ns
18EA
5V
EDO
60ns
Number
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