HD404669 Series Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit ADE-202-083B Rev. 3.0 Sept. 1999 Description The HD404669 Series microcomputers incorporate a DTMF generation circuit, two comparators, and a serial interface on chip. They also provide input and output pins with large current handling capacities. Thus they are 4-bit single-chip microcomputers that are optimal for use in multifunction telephones, cordless telephones, and other communications equipment. HD404669 Series microcomputers have a 32.768 kHz sub-oscillator for realtime clock use, providing a time counting facility, and a variety of power supply modes to reduce current drain. The HD407A4669 is a ZTAT™ microcomputer with on-chip PROM that drastically shortens development time and ensures a smooth transition from debugging to mass production. (The PROM programming specifications are the same as for the 27256 type.) ZTAT™: Zero Turn-Around Time ZTAT is a trademark of Hitachi, Ltd. Features • 1,152-digit × 4-bit RAM • I/O pins: 47 High-current I/O pins (source: 10 mA max.): 4 High-current I/O pins (sink: 15 mA max.): 5 • Timer counters: 3 • Input capture: one 8-bit channel • Timer outputs: 2 (with PWM output capability) • Event input: 1 (edge-programmable) • Clock synchronous 8-bit serial interface: 1 • DTMF generation circuit • Comparator: 2 channels • System clock oscillator Ceramic oscillator, crystal oscillator, or external clock operation possible HD404669 Series • Subsystem clock oscillator 32.768 kHz crystal oscillator for realtime clock use • Interrupts External: 5 (including 3 edge-programmable) Internal: 4 • Subroutine stack: max. 16 levels including interrupts • Low-power modes: 4 • System clock division software switching (1/4, 1/8, 1/16, 1/32) • Instruction execution time Min. 1 µs (fOSC = 4 MHz, 1/4 clock division) Min. 0.5 µs (fOSC = 8 MHz, 1/4 clock division) • Operating voltage 1.8 V to 5.5 V 2.2 V to 5.5 V (ZTAT™) Ordering Information Type Product Name Mask ROM (standard version) Mask ROM (high-speed version) ZTAT™ (high-speed version) Note: Model Name ROM (Words) HD404668 HD404668H 8,192 HD4046612 HD4046612H 12,288 HD404669 HD404669H 16,384 HCD404669 HCD404669 16,384 HD40A4668 HD40A4668H 8,192 HD40A46612 HD40A46612H 12,288 HD40A4669 HD40A4669H 16,384 HD407A4669 HD407A4669H 16,384 RAM (Digits) 1,152 Package 64-pin plastic QFP (FP-64A) Chip *1 *2 64-pin plastic QFP (FP-64A) 1. ZTAT™ chip shipment is not supported. 2. The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details. Cautions about Operation The mask ROM and ZTAT™ versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this data sheet. However, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, internal 2 HD404669 Series wiring patterns, etc. Users are therefore requested to confirm the operation of individual products by conducting evaluation tests under conditions equivalent to those in the actual application system. List of Functions Standard version HD404668 HD4046612 HD404669 HD40A4668 HD40A46612 HD40A4669 ROM (Words) 8,192 12,288 16,384 RAM (Digits) 1,152 I/O 52 (max) Highspeed version Product name Large-current I/O pins Timer / Counter 16,384 HD407A4669 16,384PROM 3 Input capture 8 bit × 1 Timer output 2 (PWM output possible) Event input 1 (edge selection possible) 1 (8-bit clock syncronous) DTMF generation circuit Available Comparator 2 External 5 (edge selection possible for 3) Internal 4 Low-Power Dissipation Mode Main Oscillator ——— 4 ( Source 10mA max), 5 (Sink 15 mA max) Serial interface Interrupt HCD404669 4 Stop mode Available Watch /mode Available Standby mode Available Subactive mode Available Ceramic oscillation 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz*, 8 MHz* Crystal oscillation 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 Mhz, 7.16 MHz*, 8 MHz* Sub oscillator Crystal oscillation 32.768 kHz Minimum instruction execution time Standard version 1 µs (fOSC = 4 MHz, 1/4 frequency division) High-speed version 0.5 µs (fOSC = 8 MHz, 1/4 frequency division) Operating voltage (V) 1.8 to 5.5 1.8 to 5.5 2.2 to 5.5 Package 64-pin plastic QFP (FP-64A) Chip 64-pin plastic QFP (FP-64A) –20 to +75 +75°C –20 to +75 Guaranteed operation temperature (˚C) Note: * Applies to high-speed versions (HD40A4668, HD40A46612, HD40A4669, HD407A4669). 3 HD404669 Series RD0/COMP0 VTref TONER TONEC VCC SEL RA1 RA0 R93 R92 R91 R90 R83 R82 R81 63 62 61 60 58 57 56 55 54 53 52 51 50 49 59 RD1/COMP1 64 Pin Arrangement RE0/VCref 1 48 R80 TEST 2 47 R73 OSC1 3 46 R72 OSC2 4 45 R71 RESET 5 44 R70 X1 6 43 R63 X2 7 42 R62 GND 8 41 R61 D0 9 40 R60 D1 D2 D3 10 39 R43 /SO1 11 38 R42 /SI1 12 37 R41 /SCK1 D4 13 36 D5 14 35 R40 /EVND R31 /TOC D9 15 34 R32 /TOD D10 16 33 R33 23 24 25 26 27 28 29 30 31 32 R03 /INT4 R10 R11 R12 R13 R20 R21 R22 R23 R30 22 R02 /INT3 21 R01 /INT2 20 18 D12 /STOPC D13 /INT0 R00 /INT1 19 17 D11 FP-64A Top view 4 HD404669 Series Pad Arrangement HCD404669 64 62 63 60 61 58 59 56 57 54 55 52 53 50 51 49 TYPE CODE 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 19 18 21 20 23 22 25 24 27 26 29 28 31 30 32 TYPE CODE: HD404669 5 HD404669 Series Bonding Pad Coordinates HCD404669 Y Chip Size (X × Y): 4.34 × 4.01 (mm) Coordinates: Pad Center Home Point position: Chip Center Pad size (X × Y): 90 × 90 (µm) Chip thickness: 400 (µm) TYPE CODE X Chip center (X=0, Y=0) Pad Pad No. Name Coordinates Coordinates Y RE0 –1983 1444 17 D11 –1607 –1819 33 R33 1983 –1444 49 R81 1587 1819 2 TESTN –1983 1252 18 D12 –1394 –1819 34 R32 1983 –1252 50 R82 1374 1819 3 OSC1 –1983 1062 19 D13 –1181 –1819 35 R31 1983 –1060 51 R83 1161 1819 4 OSC2 –1983 871 20 R00 –968 –1819 36 R40 1983 –867 52 R90 948 1819 5 RESET –1983 657 21 R01 –755 –1819 37 R41 1983 –675 53 R91 735 1819 6 X1 –1983 466 22 R02 –541 –1819 38 R42 1983 –483 54 R92 522 1819 7 X2 –1983 275 23 R03 –329 –1819 39 R43 1983 –291 55 R93 309 1819 8 GND –1983 84 24 R10 –117 –1819 40 R60 1983 –99 56 RA0 93 1819 9 D0 –1983 –108 25 R11 96 –1819 41 R61 1983 93 57 RA1 –177 1819 10 D1 –1983 –299 26 R12 309 –1819 42 R62 1983 285 58 SEL –329 1819 11 D2 –1983 –490 27 R13 522 –1819 43 R63 1983 478 59 V CC –542 1819 12 D3 –1983 –680 28 R20 735 –1819 44 R70 1983 670 60 TONEC –755 1819 13 D4 –1983 –871 29 R21 948 –1819 45 R71 1983 862 61 TONER –968 1819 14 D5 –1983 –1062 30 R22 1161 –1819 46 R72 1983 1054 62 VTREF –1181 1819 15 D9 –1983 –1253 31 R23 1374 –1819 47 R73 1983 1246 63 RD0 –1394 1819 16 D10 –1983 –1444 32 R30 1587 –1819 48 R80 1983 1444 64 RD1 –1607 1819 6 X Coordinates 1 Y Y Pad Pad No. Name Coordinates Pad Pad No. Name X Pad Pad No. Name X X Y HD404669 Series Pin Description Pin Number Item Symbol FP-64A, chip I/O Function Power supply VCC 59 – Applies power voltage GND 8 – Connected to ground Test TEST 2 I Used for factory testing only: Connect this pin to V CC Reset RESET 5 I Resets the MCU Oscillator OSC1 3 I Input/output pins for the internal oscillator circuit: Connect them to a ceramic oscillator ,crystal oscillator or connect OSC 1 to an external oscillator circuit OSC2 4 O X1 6 I X2 7 O D0–D5, D9–D11 9-17 I/O Port Used for a 32.768-kHz crystal for clock purposes. If not to be used, fix the X1 pin to V CC and leave the X2 pin open. Input/output pins addressed by individual bits; D0 to D3 are source high-current input/output pins. A maximum 10 mA current can be supplied to each pin. D4, D5, and D9 to D11 are sink high-current input/output pins. A maximum 15 mA current can be supplied to each pin. D12 , D13 18, 19 I Input pins addressable by individual bits R00–R4 3, R60–RA 1 20–57 I/O Input/output pins addressable in 4-bit units RD 0, RD1, RE0 63, 64, 1 I Input pins addressable in 4-bit units Interrupt INT0, INT1, INT2–INT4 19-23 I Input pins for external interrupts Stop clear STOPC 18 I Input pin for transition from stop mode to active mode Serial SCK1 37 I/O Serial interface clock input/output pin interface SI 1 38 I Serial interface receive data input pin SO 1 39 O Serial interface transmit data output pin TOC, TOD 35, 34 O Timer output pins EVND 36 I Event input pin TONER 61 O Output pin for DTMF row signals TONEC 60 O Output pin for DTMF column signals VTref 62 – Reference voltage pin for DTMF signals. Voltage conditions are: VCC ≥ VTref ≥ GND Timer DTMF 7 HD404669 Series Pin Number Item Symbol FP-64A, chip I/O Function Voltage comparator COMP0, COMP1 63, 64 I Comparator analog input pins. VCref 1 – Analog input pin threshold voltage reference level power supply pin. SEL 58 I Pin that selects the system clock division ratio immediately after a reset and when returning from stop mode to active mode. Connect to Vcc voltage to select division-by-4, or to GND potential to select division-by-32. Frequency division ratio selection 8 HD404669 Series RESET TEST STOPC OSC1 OSC2 X1 X2 VCC GND SEL Block Diagram ROM INT0 INT1 INT2 INT3 INT4 RAM D port HMCS400 CPU 8-bit timer A (free-running timer) TOC 8-bit timer C EVND TOD 8-bit timer D SCK1 SI1 SO1 Synchronous 8-bit serial interface VTref TONER TONEC DTMF generation circuit VCref COMP0 COMP1 Comparator : Data bus RE RD RA port port port R9 port R8 port R7 port R6 port R4 port R3 port R2 port R1 port R0 port External interrupt control circuit D0 D1 D2 D3 D4 D5 D9 D10 D11 D12 D13 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 R32 R33 R40 R41 R42 R43 R60 R61 R62 R63 R70 R71 R72 R73 R80 R81 R82 R83 R90 R91 R92 R93 RA0 RA1 RD0 RD1 RE0 : Signal line 9 HD404669 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. ROM address ROM address $0000 $0000 $000F Vector addresses (16 words) $0010 $0001 $0002 $0003 Zero page subroutine area (64 words) JMPL instruction (Jump to INT0 interrupt handling routine) JMPL instruction (Jump to INT1 interrupt handling routine) $0004 $003F $0005 $0040 $0006 Pattern area (4,096 words) JMPL instruction (Jump to reset, stop mode clearance routine) JMPL instruction (Jump to timer A interrupt handling routine) $0007 JMPL instruction (Jump to INT2 interrupt handling routine) $0008 $0FFF $0009 $1000 $000A HD404668/HD40A4668 program area (8,192 word) $000B $000C $1FFF $000D $2000 HD4046612/HD40A46612 program area (12,288 words) $000E $000F JMPL instruction (Jump to timer C, INT3 interrupt handling routine) JMPL instruction (Jump to timer D, INT4 interrupt handling routine) JMPL instruction (Jump to serial 1 routine) $2FFF $3000 HD404669/HD40A4669/ HCD404669/HD407A4669 program area (16,384 words) $3FFF Figure 1 ROM Memory Map Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000–$1FFF: HD404668, HD40A4668; $0000–$2FFF: HD4046612, HD40A46612; $0000–$3FFF: HD404669, HD40A4669, HD407A4669, HCD404669): Used for program coding. 10 HD404669 Series RAM Memory Map The MCU contains a RAM area consisting of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special function register area, and register flag area are mapped onto the same RAM memory space. The RAM memory map is shown in figure 2 and described below. RAM-Mapped Register Area ($000–$03F): • Interrupt Control Bits Area ($000–$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. • Special Function Register Area ($004–$01F, $024–$03F) This area is used as mode registers and data registers for external interrupts, serial interface, timers, DTMF, comparator, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers. • Register Flag Area ($020–$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. 11 HD404669 Series RAM address RAM address $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F $000 RAM-mapped register area $040 Memory registers (16 digits) $050 Not used $090 Data (464 digits x 2) V = 0 (bank = 0) V = 1 (bank = 1) *1 $260 Data (144 digits) $2F0 Not used $3C0 Stack area (64 digits) $3FF R : Read only W : Write only R/W : Read/Write Note : *1. There are two data areas, V = 0 (bank 0) and V = 1 (bank 1) $090 Data (464 digits) V=0 (bank = 0) Data (464 digits) V=1 (bank = 1) $25F Interrupt control bit area Port mode register A Serial mode register 1A Serial data register 1L Serial data register 1U Timer mode register A W W R/W R/W W (MIS) (TMC1) (TRCL/TWCL) (TRCU/TWCU) (TMD1) (TRDL/TWDL) (TRDU/TWDU) W W R/W R/W W R/W R/W (TMC2) (TMD2) R/W R/W (CDR) (CER) (TGM) (TGC) R W W W (PMRB) (PMRC) (ESR1) (ESR2) (SM1B) (SSR1) (SSR2) W W W W W W W (DCD0) (DCD1) (DCD2) W W W (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) W W W W W (DCR6) (DCR7) (DCR8) (DCR9) (DCRA) W W W W W Not used Miscellaneous register Timer mode register C1 Timer C Timer mode register D1 Timer D Not used Timer mode register C2 Timer mode register D2 Not used Compare data register Compare enable register Tone generator mode register Tone generator control register Not used Register flag area Port mode register B Port mode register C Detection edge select register 1 Detection edge select register 2 Serial mode register 1B System clock select register 1 System clock select register 2 Not used Data control register D0 to D3 Data control register D4 to D5 Data control register D9 to D11 Not used Data control register R0 Data control register R1 Data control register R2 Data control register R3 Data control register R4 Not used Data control register R6 Data control register R7 Data control register R8 Data control register R9 Data control register RA Not used (V) V register *2. Two registers are mapped onto the same address ($00E, $00F, $011, $012) $00E $00F Timer read register CL Timer read register CU (TRCL) (TRCU) R R Timer write register CL Timer write register CU (TWCL) (TWCU) W W $011 $012 Timer read register DL Timer read register DU (TRDL) (TRDU) R R Timer write register DL Timer write register DU (TWDL) (TWDU) W W Figure 2 RAM Memory Map 12 (PMRA) (SM1A) (SR1L) (SR1U) (TMA) R/W *2 *2 HD404669 Series RAM address Bit 3 Bit 2 Bit 1 IM0 (INT0 interrupt mask) IF0 (INT0 interrupt request flag) RSP (Reset stack pointer) IE (Interrupt enable flag) IMTA $001 (Timer A interrupt mask) IFTA (Timer A interrupt request flag) IM1 (INT1 interrupt mask) IF1 (INT1 interrupt request flag) IMTC $002 (Timer C interrupt mask) IFTC (Timer C interrupt request flag) Not used Not used IFS1 (Serial 1 interrupt request flag) IMTD (Timer D interrupt mask) IFTD (Timer D interrupt request flag) $000 $003 IMS1 (Serial 1 interrupt mask) Bit 0 Interrupt control bits area RAM address Bit 3 Bit 2 Bit 1 Bit 0 $020 DTON (DTON flag) Not used WDON (Watchdog on flag) LSON (Low speed on flag) $021 RAME (RAM enable flag) Not used ICEF (Input capture error flag) ICSF (Input capture status flag) $022 IM3 (INT3 interrupt mask) IF3 (INT3 interrupt request flag) IM2 (INT2 interrupt mask) IF2 (INT2 interrupt request flag) $023 Not used Not used IM4 (INT4 interrupt mask) IF4 (INT4 interrupt request flag) Register flag area IF IM IE SP : Interrupt Request Flag : Interrupt Mask : Interrupt Enable Flag : Stack Pointer Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas 13 HD404669 Series Bits in the interrupt control bits area and register flag area can be set and reset by the SEM or SEMD instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not affected by any other instructions. The following restrictions apply to individual bits. IE IM LSON IF ICSF ICEF RAME RSP WDON DTON Not used SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed Not executed Allowed Not executed in active mode Used in subactive mode Not executed Allowed Not executed Inhibited Inhibited Allowed Allowed Not executed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions 14 HD404669 Series Bit 3 PMRA SM1A SR1L SR1U TMA MIS TMC1 TRCL/TWCL TRCU/TWCU TMD1 TRDL/TWDL TRDU/TWDU TMC2 TMD2 CDR CER TGM TGC PMRB PMRC ESR1 ESR2 SM1B SSR1 SSR2 DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR6 DCR7 DCR8 DCR9 DCRA V Bit 2 Bit 1 Bit 0 $000 $001 Interrupt control bits area $002 $003 R43/SO1 R42/SI1 $004 $005 R41/SCK1 Serial transfer clock speed selection 1 $006 Serial data register 1 (lower) $007 Serial data register 1 (upper) Clock source setting (timer A) Timer A/time base $008 $009 $00A $00B $00C MOS pull-up/pull-down control R43/SO1 PMOS control Interrupt frame period selection Clock source setting (timer C) $00D Reload on/off $00E Timer C register (lower) $00F Timer C register (upper) $010 Reload on/off Clock source setting (timer D) $011 Timer D register (lower) $012 Timer D register (upper) $013 $014 Timer C output mode setting $015 Input capture selection Timer D output mode setting $016 $017 COMP1 comparison result COMP0 comparison result $018 Comparator operation selection Comparator selection $019 TONEC output frequency TONER output frequency $01A TONEC output TONER output DTMF enable $01B $01C $01D $01E $01F $020 $021 Register flag area $022 $023 R02/INT3 $024 R01/INT2 R00/INT1 R03/INT4 D13/INT0 $025 D12/STOPC R40/EVND INT3 detection edge selection INT2 detection edge selection $026 EVND detection edge selection INT4 detection edge selection $027 SO1 idle High/Low setting Serial clock selection $028 DTMF speed setting $029 *2 *1 $02A DTMF speed setting OSC frequency division ratio switching $02B Port D0DCR Port D3DCR Port D2DCR Port D1DCR $02C Port D5DCR Port D4DCR $02D Port D11DCR Port D10DCR Port D9DCR $02E $02F Port R03DCR Port R02DCR Port R01DCR Port R00DCR $030 Port R13DCR Port R12DCR Port R11DCR Port R10DCR $031 Port R23DCR Port R22DCR Port R21DCR Port R20DCR $032 Port R33DCR Port R32DCR Port R31DCR Port R30DCR $033 Port R43DCR Port R42DCR Port R41DCR Port R40DCR $034 $035 Port R63DCR Port R62DCR Port R61DCR Port R60DCR $036 Port R73DCR Port R72DCR Port R71DCR Port R70DCR $037 Port R83DCR Port R82DCR Port R81DCR Port R80DCR $038 Port R93DCR Port R92DCR Port R91DCR Port R90DCR $039 Port RA1DCR Port RA0DCR $03A $03B $03C $03D $03E Bank setting $03F : Not used *1: 32kHz oscillation stop setting *2: 32kHz frequency division ratio switching Figure 5 Special Function Register Area 15 HD404669 Series Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. RAM address $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04A $04B $04C $04D $04E $04F MR MR MR MR MR MR MR MR MR MR MR MR MR MR MR MR (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (a) Memory registers $3C0 $3FF Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 Bit 3 Bit 2 Bit 1 Bit 0 $3FC ST PC13 PC12 PC11 $3FD PC10 PC9 PC8 PC7 $3FE CA PC6 PC5 PC4 $3FF PC3 PC2 PC1 PC0 (b) Stack area PC13 to PC0 : Program counter ST : Status flag CA : Carry flag Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position 16 HD404669 Series Data Area ($090–$2EF): 464 digits from $090 to $25F have two banks, which can be selected by setting the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure 7). The area from $026 to $2EF is accessed without setting the bank register. Bank register (V: $03F) Bit 3 2 1 0 Initial value — — — 0 — — — R/W Read/Write Bit name Not used Not used Not used V0 V0 Bank area selection 0 Bank 0 is selected 1 Bank 1 is selected Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected. Figure 7 Bank Register (V) Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage. 17 HD404669 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described below. 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W W register Initial value: Undefined, R/W 0 (B) 1 0 (W) 3 X register Initial value: Undefined, R/W 0 (X) 3 Y register 0 (Y) Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W SPY register Initial value: Undefined, R/W Carry Initial value: Undefined, R/W Status Initial value: 1, R/W not possible 0 (SPX) 3 0 (SPY) 0 (CA) 0 Program counter Initial value: $0000, R/W not possible (ST) 13 0 (PC) 9 Stack pointer Initial value: $3FF, R/W not possible 1 5 1 1 1 0 (SP) Figure 8 Registers and Flags Accumulator (A) and B Register (B): A and B are 4-bit registers, and are used to hold the results of ALU (arithmetic and logical unit) operations and to transfer data between memory, I/O ports, and other registers. 18 HD404669 Series W Register (W), X Register (X), and Y Register (Y): W is a 2-bit register and X and Y are 4-bit registers. These registers are used in RAM register indirect addressing. The Y register is also used in D port addressing. SPX Register (SPX) and SPY Register (SPY): The SPX and SPY registers are 4-bit registers used to supplement the X and Y registers. Carry Flag (CA): CA is a 1-bit flag that stores ALU overflow generated by an arithmetic operation. CA is set to 1 when an overflow is generated, and is cleared to 0 after operations in which no overflow occurred. CA is also affected by the carry set/carry clear instructions (SEC and REC), and by the rotate with carry instructions (ROTL and ROTR). During interrupt handling, CA is saved on the stack, and is restored from the stack by the RTNI instruction. (but is not affected by the RTN instruction) Status Flag (ST): ST is a 1-bit flag that stores the results of arithmetic instructions, compare instructions, and bit test instructions, and is used as the branch condition for the BR, BRL, CAL, and CALL conditional branch instructions. The contents of the ST flag are held until the next arithmetic, compare, bit test, or conditional branch instruction is executed. After the execution of a conditional branch instruction, the value of ST is set to 1 without regard to the condition. During interrupt handling, ST is saved on the stack, and is restored from the stack by the RTNI instruction. (but is not affected by the RTN instruction) Program Counter (PC): The PC is a 14-bit counter that indicates the ROM address of the next instruction the CPU will execute. Stack Pointer (SP): The SP is a 10-bit register that indicates the RAM address of the next stack frame in the stack area. The SP is initialized to $3FF by a reset. The SP is decremented by 4 by a subroutine call or by interrupt handling, and is incremented by 4 when the saved data has been restored by a return instruction. The upper 4 bits of the SP are fixed at 1111; the maximum number of stack levels is thus 16. In addition to the reset method described above, the SP can also be initialized to $3FF by clearing the reset stack pointer (RSP) in the interrupt control bits area with a RAM bit manipulation instruction, i.e., REM or REMD. 19 HD404669 Series Reset The MCU can be reset by setting the RESET pin high or by setting the STOPC pin low*. When power is first applied, or when clearing subactive mode, watch mode, or stop mode, the RESET input must be held for at least tRC to assure that the oscillation stabilization time (tRC) condition is fulfilled. Similarly, the STOPC pin input must held for at least tRC when clearing stop mode with a STOPC pin input to assure that the oscillator stabilizes. In all other cases, the MCU is reset by a RESET input that is held for at least two instruction execution cycles. Table 1 lists the section of the MCU that are initialized by a reset and the initial values. Note: * The STOPC pin reset is only effective in stop mode. 20 HD404669 Series Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Contents Program counter (PC) $0000 Indicates program execution point from start Status flag (ST) 1 Enables conditional branching (SP) $3FF Stack level 0 (IE) 0 Inhibits all interrupts address of ROM area Stack pointer Interrupt flags/mask I/O Timer/ counters, serial interface Interrupt enable flag Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCD0) 0000 Turns output buffer off (to high impedance) Data control register (DCD1) --00 Data control register (DCD2) 000- Data control register (DCR0–DCR4, DCR6–DCR9) 0000 Data control register (DCRA) --00 Port mode register A (PMRA) --00 Refer to description of port mode register A Port mode register B (PMRB) 0000 Refer to description of R port Port mode register C bits 3, 1, 0 (PMRC3, PMRC1, PMRC0) 00- Refer to description of port mode register C Detection Edge select registers 1 and 2 (ESR1, 2) 0000 Refer to description of interrupts Timer mode register A (TMA) 0000 Refer to description of timer mode register A section Timer mode register C1 (TMC1) 0000 Refer to description of timer mode register C1 Timer mode register C2 (TMC2) -000 Refer to description of timer mode register C2 Timer mode register D1 (TMD1) 0000 Refer to description of timer mode register D1 Timer mode register D2 (TMD2) 0000 Refer to description of timer mode register D2 Serial mode register 1A (SM1A) 0000 Refer to description of serial mode register 1A Serial mode register 1B (SM1B) --X0 Refer to description of serial mode register 1B Prescaler S (PSS) $000 Refer to description of prescalers Prescaler W (PSW) $00 Refer to description of prescalers Timer counter A (TCA) $00 Refer to description of timer A Timer counter C (TCC) $00 Refer to description of timer C Timer counter D (TCD) $00 Refer to description of timer D 21 HD404669 Series Abbr. Initial Value Contents Timer write register C (TWCU, L) $X0 Refer to description of timer write register C Timer write register D (TWDU, L) $X0 Refer to description of timer write register D Serial data register 1 (SR1U, L) $XX Refer to description of serial data register 1 Octal counter (OC1) 000 Refer to description of serial interface Tone generator mode register (TGM) 0000 Refer to description of tone generator mode register Tone generator control register (TGC) 000 - Refer to description of tone generator control register Compare data register (CDR) --XX Refer to description of compare data register Compare enable register (CER) 0-00 Refer to description of compare enable register Low speed on flag (LSON) 0 Refer to description of operating modes Watchdog timer on flag (WDON) 0 Refer to description of timer C Direct transfer on flag (DTON) 0 Refer to description of operating modes Input capture status flag (ICSF) 0 Refer to description of timer D Input capture error flag (ICEF) 0 Refer to description of timer D Miscellaneous register (MIS) 0000 Refer to description of operating modes and pull-up and pull-down MOS transistor control. System clock select register 1 bits 2 to 0 (SSR12 –SSR10) 000 Refer to description of internal oscillator circuit and system clock select register 1 and 2 System clock select register 2 (SSR2) 0000 Refer to description of internal oscillator circuit and system clock select register 1 and 2 Bank register (V) - - -0 Refer to description of RAM memory map Item Timer/ counters, serial interface DTMF Comparator Bit registers Others Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. – indicates that the bit does not exist. Item Abbr. Carry flag (CA) Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) RAM Status After Cancel-lation of Stop Mode by STOPC Input Status After all Other Types of Reset Pre-stop-mode values are not guaranteed; values must be initialized by program Pre-MCU-reset values are not guaranteed; values must be initialized by program Pre-stop-mode values are retained RAM enable flag (RAME) 1 0 Port mode register C bit 2 (PMRC2) Pre-stop-mode values are retained 0 System clock select register 1 bit 3 (SSR13) 22 HD404669 Series Interrupts The MCU has 9 interrupt sources: five external signals (INT0 , INT1, INT 2–INT 4), three timer/ counters (timers A, C, and D), serial interface (Serial 1). An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. As vector addresses are shared by interrupt sources timer C and INT3, and timer D and INT4, so the type of request that has occurred must be checked at the beginning of interrupt processing. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 9 interrupt sources are listed in table 3. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET, STOPC* — $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 INT2 4 $0008 Timer C, INT3 5 $000A Timer D, INT4 6 $000C Serial 1 7 $000E Note: * The STOPC interrupt request is valid only in stop mode. 23 HD404669 Series $000, 0 Interrupt request IE $000, 2 INT0 interrupt IF0 $000, 3 Vector address IM0 $001, 0 INT1 interrupt Priority controller IF1 $001, 1 IM1 $022, 0 $001, 2 Timer A interrupt IF2 IFTA IM2 IMTA $022, 2 $002, 2 Timer C interrupt IFTC IF3 IMTC IM3 $023, 0 $003, 0 IFTD IF4 $023, 1 $003, 1 IMTD IM4 $003, 2 Serial 1 interrupt IFS1 $003, 3 IMS1 Figure 9 Interrupt Control Circuit 24 INT3 interrupt $022, 3 $002, 3 Timer D interrupt INT2 interrupt $022, 1 $001, 3 INT4 interrupt HD404669 Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Cuntrol Bit INT0 INT1 Timer A INT2 Timer C or INT3 Timer D or INT4 Serial 1 IE 1 1 1 1 1 1 1 IF0 . IM0 IF1 . IM1 1 0 0 0 0 0 0 * 1 0 0 0 0 0 IFTA . IMTA IF2 . IM2 * * 1 0 0 0 0 * * * 1 0 0 0 IFTC . IMTC + IF3 . IM3 IFTD . IMTD + IF4 . IM4 * * * * 1 0 0 * * * * * 1 0 IFS1 . IMS1 * * * * * * 1 Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a 2-cycle instruction. Execution of instruction at start address of interrupt routine Figure 10 Interrupt Sequence 25 HD404669 Series Power on RESET = "1"? No Yes Yes Interrupt request? No No IE = 1? Yes MCU reset Execute instruction PC (PC)+1 PC $0002 Accept interrupt IE Stack Stack Stack Yes 0 (PC) (CA) (ST) INT0 interrupt? No Yes PC $0004 INT1 interrupt? No Yes PC Timer A interrupt? $0006 No Yes PC $0008 INT2 interrupt? No Yes PC $000A Timer C or INT3 interrupt? No Yes PC $000C Timer D or INT4 interrupt? No PC $000E (Serial 1 interrupt) Figure 11 Interrupt Processing Flowchart 26 HD404669 Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupt Request Flags (IF0–IF4: $000, $001, $022, $023): IF0 and IF1 are set at the falling edge of signals input to INT0 and INT1, and IF2–IF4 are set at the rising or falling edge of signals input to INT 2–INT 4, as listed in table 5. The INT2–INT4 interrupt edges are selected by the detection edge select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13. Detection edge selection register 1 (ESR1: $026) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W ESR13 ESR12 ESR11 ESR10 Bit name INT3 detection edge ESR13 ESR12 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Falling/Rising-edge detection 1 INT2 detection edge ESR11 ESR10 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Falling/Rising-edge detection 1 Figure 12 Detection Edge Selection Register 1 (ESR1) 27 HD404669 Series Detection edge selection register 2 (ESR2: $027) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W ESR23 ESR22 ESR21 ESR20 Bit name EVND detection edge ESR23 ESR22 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Falling/Rising-edge detection 1 INT4 detection edge ESR21 ESR20 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Falling/Rising-edge detection 1 Figure 13 Detection Edge Selection Register 2 (ESR2) Table 5 External Interrupt Request Flags (IF0–IF4: $000, $001, $022, $023) IF0–IF4 Interrupt Request 0 No 1 Yes External Interrupt Masks (IM0–IM4: $000, $001, $022, $023): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 External Interrupt Masks (IM0–IM4: $000, $001, $022, $023) IM0–IM4 Interrupt Request 0 Enabled 1 Disabled (masked) 28 HD404669 Series Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A, C, D Interrupt Request Flags (IFTA: $001, Bit 2, IFTC: $002, Bit 2, IFTD: $003, Bit 0) Timer A, C, D Interrupt Request Flags (IFTA, IFTC, IFTD) Interrupt Request 0 No 1 Yes Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8 Timer A, C, D Interrupt Masks (IMTA: $001, Bit 3, IMTC: $002, Bit 3, IMTD: $003, Bit 1) Timer A, C, D Interrupt Masks (IMTA, IMTC, IMTD) Interrupt Request 0 Enabled 1 Disabled (masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 7. Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 8. Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling of signals input to EVND when the input capture function is used, as listed in table 7. Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 8. Serial 1 Interrupt Request Flag (IFS1: $003, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 9. Table 9 Serial 1 Interrupt Request Flag (IFS1: $003, Bit 2) IFS1 Interrupt Request 0 No 1 Yes 29 HD404669 Series Serial 1 Interrupt Mask (IMS1: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial 1 interrupt request flag, as listed in table 10. Table 10 Serial 1 Interrupt Mask (IMS1: $003, Bit 3) IMS1 Interrupt Request 0 Enabled 1 Disabled (masked) 30 HD404669 Series Operating Modes The MCU has five operating modes as shown in table 11. The operations in each mode are listed in table 12. Transitions between operating modes are shown in figure 14. Table 11 Operating Modes and Clock Status Mode Name Active Standby Stop Watch Subactive*2 RESET cancellation, interrupt request, STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) SBY instruction STOP instruction when TMA3 = 0 STOP instruction when TMA3 = 1 INT0 or timer A interrupt request from watch mode when LSON = 1 System oscillator Operation Operation Stopped Stopped Stopped Subsystem oscillator Operation Operation *1 Operation Operation RESET input, STOP/SBY instruction RESET input, RESET input, interrupt STOPC input request RESET input, INT0 or timer A interrupt request RESET input, STOP/SBY instruction Activation method Status Cancellation method STOP/SBY instruction in subactive mode (except when direct transition is specified) Notes: 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $029). 2. Subactive mode is an optional function; specify it on the function option list. 31 HD404669 Series Table 12 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Subactive Mode*2 CPU Reset Retained Retained Operation RAM Retained Retained Retained Operation Timer A Reset Operation Operation Operation Timer C Reset Stopped Operation Operation Timer D Reset Stopped Operation Operation Serial interface 1 Reset Stopped *1 Operation Operation DTMF Reset Reset Operation Reset Comparator Reset Stopped Stopped Operation I/O Reset Retained Retained Operation (highimpedance) Notes: 1. When a clock is input in external clock mode, transmit/receive operations are performed, but interrupt operations are halted. 2. Subactive mode is a function option, and should be specified in the function option list. 32 HD404669 Series Reset by RESET input or by watchdog timer Stop mode (TMA3 = 0, SSR13 = 0) RAME = 0 RESET1 RAME = 1 RESET2 STOPC STOPC STOP Oscillate Oscillate Stop fcyc fcyc Stop Oscillate Stop Stop Stop Active mode Standby mode fOSC: fX: ø CPU : ø CLK : ø PER : fOSC: fX: ø CPU : ø CLK : ø PER : SBY Interrupt fOSC: fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate fcyc fcyc fcyc (TMA3 = 0, SSR13 = 1) STOP fOSC: fX: ø CPU : ø CLK : ø PER : Stop Stop Stop Stop Stop (TMA3 = 0) Watch mode (TMA3 = 1) fOSC: fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate Stop fW fcyc SBY Interrupt fOSC: fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate fcyc fW fcyc (TMA3 = 1, LSON = 0) STOP INT0, timer A fOSC: fX: ø CPU : ø CLK : ø PER : Stop Oscillate Stop fW Stop *2 fOSC: fX: *1 Main oscillation frequency Subactive Suboscillation frequency STOP mode (TMA3 = 1, LSON = 1) for time-base Stop f : fOSC: Stop OSC *3 fcyc: fOSC/4, fOSC/8, fOSC/16 or Oscillate Oscillate f fX: : X fOSC/32 (selected by software) INT0, ø CPU : fSUB ø CPU : Stop fSUB: fX/8 or fX/4 timer A ø CLK : fW ø CLK : fW (software selectable) ø ø : f SUB PER PER : Stop fW: fX/8 ø CPU : System clock ø CLK : Clock for time-base Notes: 1. STOP/SBY (DTON = 1, LSON = 0) ø PER : Peripheral functions clock 2. STOP/SBY (DTON = 0, LSON = 0) LSON: Low speed on flag 3. STOP/SBY (DTON = Don’t care, LSON = 1) DTON: Direct transfer on flag Figure 14 MCU Status Transitions 33 HD404669 Series Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC1 and OSC2. Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. (Interrupts, timers, the serial interface, and other peripheral functions continue to operate. The exception is the comparator, which is halted.) The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. Figure 15 shows a flowchart of MCU operation. Stop mode Standby mode No RESET=1? No Watch mode RESET=1? Yes No IF0 · IM0=1? No Yes STOPC=0? Yes IF1 · IM1=1? Yes * Yes No No IFTA · IMTA=1? No RAME=1 RAME=0 Yes IF2·IM2 = 1? Yes * IFTC·IMTC + IF3·IM3=1? Yes * No IFTD·IMTD + IF4·IM4=1? No No Yes * IFS1·IMS1=1 Yes * System clock oscillator started Next instruction execution MCU reset No IF =1, IM=0, IE =1? Yes Next instruction execution Interrupts enabled Note: * Only when clearing from standby mode. Figure 15 MCU Operation Flowchart 34 System clock oscillator started , HD404669 Series Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC 1 and OSC2 oscillator stops. For the X1 and X2 oscillator to operate or stop can be selected by setting bit 3 of the system clock select register 1 (SSR1: $029; operating: SSR13 = 0, stop: SSR3 = 1) (figure 24). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 40). Stop mode is cleared by a RESET or STOPC* input. The RESET or STOPC input must be held for at least the oscillation stabilization time (t RC) as shown in figure 16. (refer to the "AC Characteristics" section.) In either of these cases, the MCU will start program execution from the program start address (location 0). However, the value of the RAM enable flag (RAME: $021,3) will be different in these cases. In particular, RAME will be set to 0 for a RESET input and will be set to 1 for a STOPC input. Also note that while a RESET input is effective in all MCU modes, STOPC is only effective in stop mode, and is ignored in all other modes. If a program needs to determine if stop mode was cleared by a STOPC input (for example, if the program intends to use the contents of RAM that were stored before stop mode was entered after returning to active mode) the program should test the RAM enable flag with a TEST instruction at the start of the program. Note: * If stop mode is to be cleared by a S TOP C input, applications should set bit 2 of port mode register C (PMRC) to 1 (PMRC2 = 1) before switching to stop mode. Stop mode Oscillator Internal clock RESET STOPC tres STOP instruction execution (at least equal to oscillation stabilization time tRC) Figure 16 Timing of Stop Mode Cancellation Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator, but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the OSC 1 and OSC2 oscillator stops, but the X1 and X2 oscillator operates. The MCU is switched to watch mode by executing a STOP instruction while TMA3 = 1 in active mode, or by executing a STOP/SBY instruction while LSON is set to 1 or DTON is cleared to 0 in subactive mode. Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC ) for an INT 0 interrupt, as shown in figures 17 and 18. 35 HD404669 Series Operation during mode transition is the same as that at standby mode cancellation (figure 15). Oscillation stabilization time Active mode Watch mode Active mode Interrupt strobe INT0 Interrupt request generation (During the transition from watch mode to active mode only) T T tRC TX T: Interrupt frame period t RC : Oscillation stabilization time Note: If the time from the fall of the INT0 signal until the interrrupt is accepted and active mode is entered is designated Tx, then Tx will be in the following range: T + tRC < Tx < 2T + tRC Figure 17 Interrupt Frame 36 HD404669 Series Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions other than the DTMF generation circuit operate, but since the operating clocks are slow, power consumption is the lowest after watch mode. The CPU instruction execution speed can be selected as 244 µs or 122 µs by setting bit 2 (SSR12) of the system clock select register (SSR1: $029). Note that the SSR12 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Subactive mode is an optional function that the user must specify on the function option list. Interrupt Frame: In watch and subactive modes, φCLK is applied to timer A and the INT0Icircuit. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame periods (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18). In watch and subactive modes, the timer-A/ INT0 interrupt is generated synchronously with the interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 MIS1 MIS0 0 0 Bit name MIS3 MIS2 Buffer control. See figure 37 in the pull-up and pull-down MOS transistor control section T*1 tRC * 1 0.24414 ms 0.12207 ms 0.24414 Oscillation circuit conditions External clock input ms* 2 Ceramic oscillator 0 1 15.625 ms 7.8125 ms 1 0 62.5 ms 31.25 ms Crystal oscillator 1 1 Not used Not used — Notes: 1. Values of T and tRC when a 32.768-kHz crystal oscillator is used to pins x1 and x2. 2. The value is applied only when direct transfer operation is used. Figure 18 Miscellaneous Register (MIS) 37 HD404669 Series Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: • Set LSON to 0 and DTON to 1 in subactive mode. • Execute the STOP or SBY instruction. • The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (figure 19). Notes: 1. The DTON flag can be set only in subactive mode. It is always reset in active mode. 2. The transition time (TD) from subactive mode to active mode: tRC < TD < T + tRC STOP/SBY instruction execution Subactive mode MCU internal processing time Oscillation stabilization time Active mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing t RC T TD Interrupt frame period T: t RC : Oscillation stabilization time TD : Direct transition time Figure 19 Direct Transition Timing MCU Operation Sequence: The MCU operates in the sequence shown in figure 20. It is reset by an asynchronous RESET input, regardless of its status. With the IE flag cleared and an interrupt request flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt request flags are cleared or all interrupts are masked. 38 HD404669 Series STOP/SBY instruction IF = 1 and IM = 0? No Yes Standby/watch mode No Interrupt service routine IE = 0 * No Yes Stop mode IF = 1 and IM = 0? No STOPC = 0? Yes Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC ← (PC)+1 PC ← (PC)+1 Reset MCU Instruction execution MCU operation cycle Note: * Refer to figure 15, Flowchart for Exiting Low Power Modes, for IF and IM operation. Figure 20 MCU Operating (Low-Power Mode Operation) Notes: When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Also, if the low level period after the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Edge detection is shown in figure 21. The level of the INT0 signal is sampled by a sampling clock. When this sampled value changes to low from high, a falling edge is detected. 39 HD404669 Series In figure 22(a), the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge is not detected in this case either. When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT 0 longer than interrupt frame. INT0 Sampling High Low Low Figure 21 Edge Detection INT0 INT0 Interrupt frame Interrupt frame A: Low B: Low (a) High level period Figure 22 Sampling Example 40 A: High B: High (b) Low level period HD404669 Series Internal Oscillator Circuit A block diagram of the clock generation circuit is shown in figure 23. As shown in table 13, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. Set bits 0 and 1 (SSR10, SSR11) of system clock select register 1 (SSR1: $029) and bits 2 and 3 (SSR22, SSR23) of system clock select register 2 (SSR2: $02A) according to the frequency of the oscillator connected to OSC 1 and OSC2 (figures 24 and 25). The system clock division ratio can be set with bits 0 and 1 (SSR20, SSR21) of system clock select register 2 (SSR2: $02A). The value set in these bits does not become valid until watch mode is entered. Therefore, the system clock must be halted temporarily when changing the division ratio. The system clock division ratio immediately after a reset or when stop mode is cleared can be selected by means of the SEL pin level, division-by-4 being selected when the SEL pin is at Vcc potential, and division-by-32 when at GND potential. Note: If the system clock select register 1 and 2 (SSR1, SSR2: $029, $02A) setting does not match the oscillator frequency, DTMF generation circuit and subsystems using the 32.768-kHz oscillation will malfunction. LSON OSC2 OSC1 System fOSC 1/4, 1/8, 1/16 or clock 1/32 oscillator division circuit fX X1 X2 Subsystem clock oscillator fcyc tcyc Timing generation circuit CPU with ROM, RAM, registers, flags, and I/O øCPU System clock selection circuit øPER Internal Peripheral module interrupts fSUB 1/8 or 1/4 Timing division tsubcyc generation circuit circuit TMA3 bit 1/8 division circuit fW tWcyc Timing generation circuit Time-base clock øCLK selection circuit Time base interrupt Figure 23 Clock Generation Circuit 41 HD404669 Series System clock select register 1 (SSR1: $029) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name SSR13 W W W W SSR13 SSR12 SSR11 SSR10 System clock SSR23 SSR22 SSR11 SSR10 selection 32-kHz oscillation stop 0 Oscillation operates in stop mode 1 Oscillation stops in stop mode 0 0 0 1 SSR12 32-kHz oscillation division ratio selection 0 fSUB = fX/8 1 fSUB = fX/4 1 0 400 kHz 1 800 kHz 0 2 MHz 1 4 MHz 1 × × 3.58 MHz 0 1 1 8 MHz 1 × × 7.16 MHz Note: SSR13 is cleared only by a RESET input. SSR13 will not be cleared by a STOPC input during stop mode, and will retain its value. SSR13 will also not be cleared upon entering stop mode. Figure 24 System Clock Select Register 1 (SSR1) System clock select register 2 (SSR2: $02A) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SSR23 SSR22 SSR21 SSR20 Bit name SSR23 0 1 System clock selection*2 System clock division ratio selection*1 SSR21 SSR20 Selected from 400 kHz, 800 kHz, 2 MHz, 4 MHz 0 0 Division by 4 1 Division by 8 1 3.58MHz 1 0 Division by 16 0 8MHz 1 Division by 32 1 7.16MHz SSR22 0 Notes : *1 The DTMF generation circuit frequencies are not affected by the system clock division ratio setting. *2 See system clock select register 1 (SSR1). Figure 25 System Clock Select Register 2 (SSR2) 42 HD404669 Series Table 13 Oscillator Circuit Examples Circuit Configuration External clock operation Circuit Constants — External oscillator OSC 1 Open OSC 2 Ceramic oscillator Ceramic oscillator: CSB400P22 (Murata) CSB400P (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 220 pF ± 5% (OSC1, OSC 2) C1 OSC1 Ceramic oscillator Ceramic oscillator: CSB800J122 (Murata), CSB800J (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 220 pF ± 5% Rf OSC2 C2 Ceramic oscillator: CSA2.00MG (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 30 pF ± 20% GND Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 30 pF ± 20% Ceramic oscillator: CSA3.58MG (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 30 pF ± 20% Ceramic oscillator: CSA8.00MT (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 30 pF ± 20% Crystal oscillator Rf = 1 MΩ ± 20% C1 = C2 = 10 to 22pF ± 20% C1 (OSC1, OSC 2) Crystal oscillator OSC1 Rf Crystal oscillator: Equivalent circuit at left C0 =7pF max Rs = 100Ω max f = 400kHz, 800kHz, 2MHz, 3.58MHz, 4MHz, 7.16MHz, 8MHz OSC2 C2 GND OSC1 L CS RS OSC2 C0 43 HD404669 Series Circuit Configuration Circuit Constants C1 Crystal oscillator Crystal oscillator: 32.768 kHz: MX38T (Nippon Denpa) C1 = C2 = 20 pF ± 20% RS=14 kΩ C0=1.5 pF X1 (X1, X2) Crystal oscillator X2 C2 GND L CS RS X1 X2 C0 Notes: 1. Circuit constants differ by the different types of crystal oscillators, ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. The wiring between the OSC1, OSC 2 (X1 and X2 pins), and the other elements should be as short as possible, and must not cross other wiring. Refer to figure 26. 3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to VCC and leave the X2 pin open. GND X2 X1 RESET OSC2 OSC1 TEST GND Figure 26 Typical Layouts of Crystal and Ceramic Oscillator 44 HD404669 Series Input/Output The MCU has 47 input/output pins (D0 to D5, D 9 to D11, R00 to R43 and R60 to RA 1) and 5 input pins (D12, D13, RD0, RD1 and RE0). The features are described below. • Four pins D0 to D3 are high source current (10 mA maximum) input/output pins. • Five pins D 4, D5, and D9 to D11 are high sink current (15 mA maximum) input/output pins. • Certain of these input and output pins have shared functions with timers, the serial interface, and other peripheral functions. The D 12, D13, R0, R30, R32, R4, RD 0, RD1 and RE0 pins are shared function pins. The use of these pins as peripheral function pins takes precedence over their use as the D and R port pins. Pins that are set to function as peripheral function pins are switched automatically between their various functions and between the input and output directions according to their specifications under the peripheral function setting. • Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. • Peripheral function output pins are all CMOS outputs. However, the SO1 pin and the R43 port pin can be set to function as NMOS open drain outputs by software. • Since the MCU goes to the reset state internally after a reset and in stop mode, the peripheral function settings for these pins are cleared. Furthermore, since the data control registers (DCD and DCR) are also reset, the input/output pins go to the high-impedance state. • The D0 to D3 pin circuits include pull-down MOS transistors, and all the other pin circuits include pullup MOS transistors. Note that the on/off states of the pull-up and pull-down MOS transistors can be set independently of the setting for use as peripheral function pins. I/O buffer configurations are shown in figures 27 and 28, and I/O pin circuit structures are listed in tables 14 and 15. HLT Pull-up control signal VCC VCC MIS3 Buffer control signal Pull-up MOS DCD,DCR Output data PDR Input data Input control signal Figure 27 I/O Buffer Configuration (with Pull-Up MOS) 45 HD404669 Series Input data Input control signal VCC Buffer control signal DCD Output data Pull-down MOS PDR Pull-down MOS control signal MIS3 HLT Figure 28 I/O Buffer Configuration (with Pull-Down MOS) Table 14 I/O Pin Control by Register Settings (with Pull-Up MOS) MIS3 (bit 3 of MIS) 0 DCD, DCR 0 PDR CMOS buffer 1 0 1 0 1 0 1 0 1 0 1 PMOS — — — On — — — On NMOS — — On — — — On — — — — — — On — On Pull-up MOS Note: 1 1. — indicates off status. 2. PDR is not assigned to a RAM address. It is accessed with special input/output instructions. Table 15 I/O Pin Control by Register Settings (with Pull-Down MOS) MIS3 (bit 3 of MIS) 0 DCD 0 PDR CMOS buffer Pull-down MOS Note: 46 1 1 0 1 0 1 0 1 0 1 0 1 PMOS — — — On — — — On NMOS — — On — — — On — — — — — On — On — 1. — indicates off status. 2. PDR is not assigned to a RAM address. It is accessed with special input/output instructions. HD404669 Series Table 16 Input/Output Pin Circuit Configurations I/O Pin Type Circuit Configuration Relevant Pins Input/output pins HLT VCC VCC Pull-up control signal Buffer control signal MIS3 DCD,DCR Output data PDR Input data Input control signal Input data Input control signal D4 , D5 , D9 – D11 R0 0–R0 3 R1 0–R1 3 R2 0–R2 3 R3 0–R3 3 R4 0–R4 2 R6 0–R6 3 R7 0–R7 3 R8 0–R8 3 R9 0–R9 3 RA 0, RA 1 D0–D 3 VCC Buffer control signal DCD Output data Pull-down control signal PDR MIS3 HLT VCC HLT VCC Pull-up control signal Buffer control signal Output data R4 3 MIS3 DCR MIS2 PDR Input data Input control signal Input pins Input data D12, D13 RD0, RD1, RE 0 Input control signal 47 HD404669 Series Table 16 Input/Output Pin Circuit Configurations (cont) I/O Pin Type Peripheral function Circuit Configuration Input/output pins VCC VCC Relevant Pins Pull-up control signal Output data Input data VCC SCK 1 MIS3 SCK1 SCK1 Output pins VCC HLT Pull-up control signal HLT SO1 MIS3 PMOS control signal MIS2 Output data VCC VCC Pull-up control signal Output data Input pins SO1 HLT MIS3 TOC,TOD HLT VCC MIS3 PDR Input data Input data TOC, TOD SI 1, INT1, INT2, INT3, INT4, EVND SI1,INT1,etc. INT0, STOPC, RESET INT0, STOPC RESET Note: In a reset and in stop mode, since the I/O control registers are reset, input/output pins go to the highimpedance state and peripheral function selections are cleared. 48 HD404669 Series D Port The D port consists of 9 input/output pins and 2 input-only pins that can be addressed individually on a perbit basis. The D0 to D3 pins are high source current input/output pins and the D4, D 5, and D9 to D11 pins are high sink current input/output pins. The D 12 and D 13 pins are input-only pins. The D0 to D 5 and D9 to D11 pins can be set or reset by the SED/RED and SEDD/REDD instructions. The output data is stored in the port data register for the pin. All the D port pins can be tested using the TD and TDD instructions. The D port data control registers (DCD0 to DCD2: $02C to $02E) are used to turn the D0 to D5 and D9 to D11 pin output buffers on and off. The DCD registers are mapped to addresses in the RAM area. (figure 29.) The D12 and D 13 pins have shared functions as internal peripheral function pins and the STOPC and INT0 pins. Port mode register C (PMRC: $025) bits 2 and 3 (PMRC2 and PMRC3) are used to switch the functions of these pins. (figure 32.) 49 HD404669 Series Data control register DCD0 to DCD2 Bit 3 (DCD0 to 2: $02C to $02E) (DCR0 to 4, DCR6 to A: $030 to $034, $036 to $03A) 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name DCD03, DCD02, DCD01– DCD00– DCD23 DCD22 DCD21 DCD10 DCR0 to DCR4 DCR6 to DCRA Bit 3 2 1 0 Initial value 0 0 0 0 W W W W Read/Write Bit name DCR03– DCR02– DCR01– DCR00– DCR43 DCR42 DCR41 DCR40 DCR63– DCR62– DCR61– DCR60– DCR93 DCR92 DCRA1 DCRA0 Note: Other bits are not used. All Bits CMOS Buffer Control 0 CMOS buffer Off (high-impedance) 1 CMOS buffer active Correspondence between ports and DCD/DCR bits Register Name Bit 3 Bit 2 Bit 1 Bit 0 DCD0 D3 D2 D1 D0 DCD1 — — D5 D4 DCD2 D11 D10 D9 — DCR0 R03 R02 R01 R00 DCR1 R13 R12 R11 R10 DCR2 R23 R22 R21 R20 DCR3 R33 R32 R31 R30 DCR4 R43 R42 R41 R40 DCR6 R63 R62 R61 R60 DCR7 R73 R72 R71 R70 DCR8 R83 R82 R81 R80 DCR9 R93 R92 R91 R90 DCRA — — RA1 RA0 Figure 29 Data Control Registers (DCD, DCR) 50 HD404669 Series R Port The R port consist of 38 input/output pins and 3 input pins that can be addressed in groups of 4 bits. Data can be input using the LAR and LBR instructions, and data can be output using the LRA and LRB instructions. Output data is stored in the port data register for the corresponding pin. The R port data control registers (DCR0 to DCR4 and DCR6 to DCRA: $030 to $034, and $036 to $03A) are used to turn the R port output buffers on and off. The DCR registers are mapped to addresses in the RAM area. (figure 29.) The R00 to R04 port pins have shared functions as the external interrupt input pins INT1 to INT4. Port mode register B (PMRB $024) is used to set these pins to their peripheral function usage. (figure 31.) The R40 port pin has a shared function as the EVND peripheral function pin. Port mode register C (PMRC: $025) bit 1 (PMRC1) is used to switch the function of this pin. (figure 32.) The R31 and R32 port pins have shared functions as the TOC and TOD peripheral function pins. Timer mode register C2 (TMC2: $014) bits 0 to 2 (TMC20 to TMC22) and timer mode register D2 (TMD2: $015) are used to set these pins to their peripheral function usage. (figures 33 and 34.) The R4 1 to R43 port pins have shared functions as the SCK 1, SI 1, and SO1 peripheral function pins. Serial mode register 1A (SM1A: $005) bit 3 (SM1A3) and port mode register A (PMRA: $004) bits 0 and 1 (PMRA0 and PMRA1) are used to set these pins to their peripheral function usage. (figures 30 and 35.) The R4 3/SO 1 pin can be set to function as an NMOS open drain output with the output buffer off. Miscellaneous register (MIS: $00C) bit 2 (MIS2) is used for this setting. (figure 37.) The RD0 and RD1 port pins have shared functions as the COMP 0 and COMP1 peripheral function pins. The compare enable register (CER: $018) is used to set these pins to their comparator pin functions. (figure 36.) Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value — — 0 0 Read/Write — — W W Bit name PMRA1 Not used Not used PMRA1 PMRA0 R42/SI1 mode selection PMRA0 R43/SO1 mode selection 0 R42 0 R43 1 SI1 1 SO1 Figure 30 Port Mode Register A (PMRA) 51 HD404669 Series Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value 0 0 0 0 W W W Read/Write Bit name PMRB3 W PMRB3 PMRB2 PMRB1 PMRB0 PMRB0 R03/INT4 mode selection R00/INT1 mode selection 0 R03 0 R00 1 INT4 1 INT1 PMRB2 R02/INT3 mode selection PMRB1 R01/INT2 mode selection 0 R02 0 R01 1 INT3 1 INT2 Figure 31 Port Mode Register B (PMRB) Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 0 — W — Read/Write Bit name PMRC3 W W PMRC3 PMRC2 D13/INT0 mode selection 0 D13 1 INT0 PMRC2 PMRC1 Not Used D12/STOPC mode selection PMRC1 R40/EVND mode selection 0 D12 0 R40 1 STOPC 1 EVND Figure 32 Port Mode Register C (PMRC) 52 HD404669 Series Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value — 0 0 0 Read/Write — R/W R/W R/W TMC21 TMC20 Bit name Not used TMC22 TMC22 TMC21 TMC20 0 0 0 R31 R31 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 — Not Used TOC PWM output 1 0 1 R31/TOC mode selection 1 1 0 1 Figure 33 Timer Mode Register C2 (TMC2) Timer mode register D2 (TMD2: $015) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name R/W R/W R/W R/W TMD23 TMD22 TMD21 TMD20 R32/TOD mode selection TMD23 TMD22 TMD21 TMD20 0 0 0 0 R32 R32 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 — Not used 1 TOD PWM output × R32 Input capture (R32 port) 1 1 0 1 1 1 × × 0 × : Don’t care Figure 34 Timer Mode Register D2 (TMD2) 53 HD404669 Series Serial mode register 1A (SM1A: $005) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W Bit name SM1A3 SM1A2 SM1A1 SM1A0 SM1A3 R41/SCK1 mode selection 0 R41 1 SCK1 SM1A2 SM1A1 SM1A0 SCK1 Clock source Prescaler division ratio 0 0 0 Output Prescaler ÷2048 1 Output Prescaler ÷512 0 Output Prescaler ÷128 1 Output Prescaler ÷32 0 Output Prescaler ÷8 1 Output Prescaler ÷2 0 Output System clock — 1 Input External clock — 1 1 0 1 Figure 35 Serial Mode Register 1A (SM1A) Compare enable register (CER: $018) Bit 3 2 1 0 Initial value 0 — 0 0 Read/Write W — W W Bit name CER1 0 1 CER3 CER0 Not Used CER1 CER0 Analog input pin selection 0 COMP0 1 COMP1 × Not Used × : Don't care CER3 Comparator operation selection 0 Normal operation (digital input mode): RD0/COMP0 and RD1/COMP1 pins function as R port pins 1 Comparator operation (analog input mode): RD0/COMP0 and RD1/COMP1 pins function as comparator pins Figure 36 Compare Enable Register (CER) 54 HD404669 Series Pull-up and Pull-down MOS Transistor Control The D4, D5, D9 to D11, and the R port pins have built-in pull-up MOS transistors that can be controlled by software, and the D0 to D3 pins have built-in pull-down MOS transistors that can be controlled by software. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin—enabling on/off control of that pin alone (tables 14, 15 and figure 37). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 MIS2 CMOS buffer on/off selection for pin R43/SO1 Bit name MIS3 Pull-up/Pull-down MOS transistor control 0 Off 0 Active 1 Active 1 Off MIS1 MIS0 tRC selection. Refer to figure 18 in the operation modes section. Figure 37 Miscellaneous Register (MIS) How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 kΩ. Pins provided with pull-down MOS should be pulled down to GND potential with the built-in pull-down MOS or connected to GND. 55 HD404669 Series Prescalers The MCU has the following two prescalers, S and W. The prescalers operating conditions are listed in table 17, and the prescalers output supply is shown in figure 38. The timers A, C, D input clocks except external events, the serial transmit clock except the external clock, are selected from the prescaler outputs, depending on corresponding mode registers. Table 17 Prescaler Operating Conditions Prescaler Input Clock Reset Conditions Stop Conditions Prescaler S System clock (in active and standby mode), Subsystem clock (in subactive mode) MCU reset MCU reset, stop mode, watch mode Prescaler W Clock derived by dividing subsystem clock 32.768 kHz oscillation by 8 MCU reset, software* MCU reset, stop mode Note: * If bits TMA3 to TMA1 in timer mode register A (TMA) are all set to 1, PSW is cleared to $00. Subsystem clock Prescaler W Timer A Timer C Timer D System clock Clock selector Prescaler S Serial interface 1 Figure 38 Prescaler Output Supply Prescaler Operation Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and stop modes and at MCU reset. Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by software. 56 HD404669 Series Timers The MCU has three timer/counters (A, C, D). • Timer A: Free-running timer • Timer C: Multifunction timer • Timer D: Multifunction timer Timer A is an 8-bit free-running timer. Timers C, D are 8-bit multifunction timers, whose functions are listed in table 18. The operating modes are selected by software. Table 18 Timer Functions Functions Timer A Timer C Timer D Clock Prescaler S Available Available Available source Prescaler W Available — — External event — — Available Timer Free-running Available Available Available functions Time-base Available — — Event counter — — Available Reload — Available Available Watchdog — Available — Input capture — — Available Timer Toggle — Available Available outputs 0 output — Available Available 1 output — Available Available PWM — Available Available Note: — implies not available. Timer A Timer A Functions: Timer A has the following functions. • Free-running timer • Clock time-base The block diagram of timer A is shown in figure 39. 57 HD404669 Series 1/4 1/2 2 fW fW twcyc Timer A interrupt request flag (IFTA) Prescaler W (PSW) ÷2 ÷8 ÷ 16 ÷ 32 32.768-kHz oscillator 1/2 twcyc Clock Timer counter A (TCA) Overflow ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 1024 ÷ 2048 Selector ø PER System clock Internal data bus Selector Selector Prescaler S (PSS) 3 Timer mode register A (TMA) Data bus Clock line Signal line Figure 39 Block Diagram of Timer A Timer A Operations Free-running timer operation: The timer A input clock is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by an MCU reset, and counts up each time the input clock is input. When the input clock is input after the timer A value reaches $FF, overflow output is generated, and the timer A value becomes $00. The generated overflow output sets the timer A interrupt request flag (IFTA: $001, 2). Timer A continues counting up after the count value returns to $00, so that an interrupt is generated regularly every 256 input clock cycles. Realtime clock time base operation: Timer A can be used as the realtime clock time base by setting bit 3 (TMA3) of timer mode register A to 1. As the prescaler W output is input to timer counter A (TCA), interrupts are generated with accurate timing using the 32.768 kHz crystal oscillator as the basic clock.When timer A is used as the realtime clock time base, prescaler W and timer counter A (TCA) can be reset to $00 by the program. Registers for Timer A Operation Timer A operating modes are set by the following registers. Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode and input clock source as shown in figure 40. 58 HD404669 Series Timer mode register A (TMA: $008) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W TMA3 TMA2 TMA1 TMA0 Source Input clock TMA3 TMA2 TMA1 TMA0 prescaler frequency 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 PSS 2048tcyc 1 PSS 1024tcyc 0 PSS 512tcyc 1 PSS 128tcyc 0 PSS 32tcyc 1 PSS 8tcyc 0 PSS 4tcyc 1 PSS 2tcyc 0 PSW 32tWcyc 1 PSW 16tWcyc 0 PSW 8tWcyc 1 PSW 2tWcyc 0 — 1/2tWcyc 1 — Not used × — Reset PSW and TCA Operating mode Timer A mode Time-base mode × : Don’t care Note: 1. tWcyc = 244.14 µs (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) × 256. 3. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Figure 40 Timer Mode Register A (TMA) 59 HD404669 Series Timer C Timer C Functions: Timer C has the following functions. • Free-running/reload timer • Watchdog timer • Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 41. 60 HD404669 Series System reset signal Watchdog on flag (WDON) Timer C interrupt request flag (IFTC) Watchdog timer control logic TOC Timer output control logic ø PER Timer read register CL (TRCL) Timer read register CU (TRCU) ÷2 ÷8 ÷ 128 ÷ 512 clock ÷ 1024 ÷ 2048 3 Timer mode register C1 (TMC1) Free-running/reload control ÷ 32 Timer counter C (TCCL) (TCCU) 4 4 Overflow Internal data bus 4 ÷4 Selector Prescaler S (PSS) System clock Timer write register C (TWCL) (TWCU) 3 Timer output control Data bus Timer mode register C2 (TMC2) Clock line Signal line Figure 41 Block Diagram of Timer C 61 HD404669 Series Timer C Operations Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C (TWCL: $00E, TWCU: $00F); if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2 ). The timer C interrupt request flag is reset by the program, an MCU reset or a transition to stop mode. For details, see figure 3, Configuration of Interrupt Control Bits and Register Flag Area, and table 1, Initial Values after MCU Reset. Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). With timer C, the R3 1/TOC pin is designated as the TOC pin, and toggle waveform output, low-level output, high-level output, or PWM waveform output can be selected, by timer mode register C2 (TMC2: $014). TOC pin output is initialized to the low level by an MCU reset. • Toggle output With toggle output, the output level is changed upon input of the next clock pulse after the timer C value reaches $FF. Use of this function in combination with the reload timer allows a clock signal with any period to be output, enabling it to be used as buzzer output. The output waveform is shown in figure 42. • Low-level output With low-level output, the output is changed to the low level when timer C overflows. This function should be used when the output is high. • High-level output With high-level output, the output is changed to the high level when timer C overflows. This function should be used when the output is low. • PWM output With PWM output, variable-duty pulses are output. The output waveform is as shown in figure 42, according to the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). 62 HD404669 Series Toggle output waveform (timers C and D) Free-running timer 256 clock cycles 256 clock cycles Reload timer (256 – N) clock cycles (256 – N) clock cycles PWM output waveform (timers C and D) T × (N + 1) TMC13 = 0 TMD13 = 0 (free-running timer) T T × 256 TMC13 = 1 TMD13 = 1 (reload timer) T × (256 – N) Notes: T: Counter input clock period The clock input source and division ratio are controlled by timer mode register C1 and timer mode register D1. N: Value in timer write register C or timer write register D (When N = 255 (= $FF), PWM output is always fixed low.) Figure 42 Timer Output Waveforms 63 HD404669 Series Registers for Timer C Operation By using the following registers, timer C operation modes are selected and the timer C count is read and written. • • • • Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/reload timer function, and the prescaler division ratio as shown in figure 43. It is reset to $0 by MCU reset or in stop mode. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C’s initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. Timer mode register C1 (TMC1: $00D) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W TMC13 TMC12 TMC11 TMC10 Bit name TMC13 Free-running/reload timer selection 0 Free-running timer 1 Reload timer TMC11 TMC10 0 0 0 2048tcyc 1 1024tcyc 0 512tcyc 1 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 2tcyc 1 1 0 1 Figure 43 Timer Mode Register C1 (TMC1) 64 Input clock period TMC12 HD404669 Series Timer mode register C2 (TMC2: $014): Timer mode register C2 (TMC2: $014) is a 3-bit read/write register, used to switch the function of the R31/TOC pin and select the timer C output mode as shown in figure 44. Timer mode register C2 (TMC2: $014) is reset to $0 by an MCU reset or in stop mode. Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value — 0 0 0 Read/Write — R/W R/W R/W TMC21 TMC20 Bit name Not used TMC22 TMC22 TMC21 TMC20 0 0 0 R31 R31 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 — Not used TOC PWM output 1 1 0 R31/TOC mode selection 1 1 0 1 Figure 44 Timer Mode Register C2 (TMC2) Timer write register C (TWCL: $00E, TWCU: $00F): Timer write register C (TWCL: $00E, TWCU: $00F) is a write-only register composed of a lower digit (TWCL: $00E) and an upper digit (TWCU: $00F). The lower digit (TWCL) of timer write register C is reset to $0 by an MCU reset or in stop mode, while the upper digit (TWCU) is undetermined. Timer C can be initialized by writing to timer write register C (TWCL, TWCU). To write the data, first write the lower digit (TWCL). The lower digit write does not change the timer C value. Next, write the upper digit (TWCU). Timer C is then initialized to the timer write register C (TWCL, TWCU) value. When writing to timer write register C (TWCL, TWCU) from the second time onward, if it is not necessary to change the lower digit (TWCL) reload value, timer C initialization is completed by the upper digit write alone. 65 HD404669 Series Timer write register C (lower digit) (TWCL: $00E) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWCL3 TWCL2 TWCL1 TWCL0 Bit name Figure 45 Timer Write Register C Lower Digit (TWCL) Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWCU3 TWCU2 TWCU1 TWCU0 Figure 46 Timer Write Register C Upper Digit (TWCU) Timer read register C (TRCL: $00E, TRCU: $00F): Timer read register C (TRCL: $00E, TRCU: $00F) is a read-only register composed of a lower digit (TRCL: $00E), and an upper digit (TRCU: $00F) from which the value of the upper digit of timer C is read directly. First, read the upper digit (TRCU) of timer read register C. The current value of the timer C upper digit is read and, at the same time, the value of the timer C lower digit is latched in the lower digit (TRCL) of timer read register C. The timer C value is obtained when the upper digit (TRCU) of timer read register C is read by reading the lower digit (TRCL) of timer read register C. Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCL3 TRCL2 TRCL1 TRCL0 Figure 47 Timer Read Register C Lower Digit (TRCL) 66 HD404669 Series Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCU3 TRCU2 TRCU1 TRCU0 Figure 48 Timer Read Register C Upper Digit (TRCU) Timer D Timer D Functions: Timer D has the following functions. • • • • Free-running/reload timer External event counter Timer output operation (toggle, low-level, high-level, and PWM outputs) Input capture timer The block diagram for each operation mode of timer D is shown in figures 49(1) and 49(2). 67 HD404669 Series Timer D interrupt request flag (IFTD) EVND Edge detection logic Timer read register DU (TRDU) øPER System clock ÷ 32 ÷ 128 clock ÷ 512 ÷ 2048 3 Free-running/reload control ÷8 Timer counter D (TCDL) (TCDU) 4 4 Internal data bus 4 ÷4 Selector Prescaler S (PSS) ÷2 Overflow Timer read register DL (TRDL) Timer write register D (TWDL) (TWDU) Timer mode register D1 (TMD1) 2 Edge detection select register 2 Edge detection control (ESR2) Timer mode register D2 (TMD2) Timer output control logic TOD Data bus Clock line Signal line Figure 49(1) Block Diagram of Timer D (Free-Running/Reload Timer/Event Counter Modes) 68 HD404669 Series Timer D interrupt request flag (IFTD) Input capture error flag (ICEF) Input capture status flag (ICSF) Error control logic EVND Edge detection logic ø PER Timer read register D 4 4 ÷4 ÷ 32 ÷ 128 clock Selector ÷8 Timer counter D (TCDL) ÷ 512 ÷ 2048 (TCDU) Input capture timer control 3 Timer mode register D1 (TMD1) Internal data bus ÷2 (TRDU) Overflow (TRDL) Prescaler S (PSS) System clock Read signal Timer mode register D2 (TMD2) 2 Edge detection select register 2 Edge detection control (ESR2) Data bus Clock line Signal line Figure 49(2) Block Diagram of Timer D (Input Capture Timer) 69 HD404669 Series Timer D Operations: • Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D (TWDL: $011, TWDU: $012); if the freerunning timer function is enabled, the timer is initialized to $00 and then incremented again. The timer D interrupt request flag (IFTD: $003, 0) is reset by the program, and by an MCU reset or a transition to stop mode. For details, see figure 3, Configuration of Interrupt Control Bits and Register Flag Areas, and table 1, Initial Values after MCU Reset. • External event counter operation: When external event input is designated for the input clock by timer mode register D1 (TMD1), timer D operates as an external event counter.In this case, pin R40/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation. • Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle Low-level output Hige-level output PWM output Pin R3 2/TOD is set to TOD. Toggle output: The operation is basically the same as that of timer-C’s toggle output. 0 output: The operation is basically the same as that of timer-C’s 0 output. 1 output: The operation is basically the same as that of timer-C’s 1 output. PWM output: The operation is basically the same as that of timer-C’s PWM output. 70 HD404669 Series • Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 0) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R3 2/TOD is set to R3 2 and timer D is reset to $00. Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 50. Timer mode register D1 (TMD1: $010) is reset to $0 by an MCU reset or in stop mode. • Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D’s initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. • When selecting the input capture timer operation, select the internal clock as the input clock source. When designating external event input for the input clock, set bit 1 (PMRC1) of port mode register C (PMRC) to 1. 71 HD404669 Series Timer mode register D1 (TMD1: $010) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name TMD13 W W W W TMD13 TMD12 TMD11 TMD10 Free-running/reload timer selection 0 Free-running timer 1 Reload timer TMD11 TMD10 0 0 0 2048tcyc 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 EVND (external event input) 1 1 0 1 Figure 50 Timer Mode Register D1 (TMD1) 72 Input clock period and input clock source TMD12 HD404669 Series Timer mode register D2 (TMD2: $015): Timer mode register D2 (TMD2: $015) is a 4-bit read/write register, used to switch the function of the R32/TOD pin and select the timer D output mode as shown in figure 51. Timer mode register D2 (TMD2: $015) is reset to $0 by an MCU reset and in stop mode. Timer mode register D2 (TMD2: $015) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W TMD23 TMD22 TMD21 TMD20 TMD23 TMD22 TMD21 TMD20 0 0 0 0 R32 R32 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 — Not used 1 TOD PWM output × R32 Input capture (R32 port) Bit name 1 1 0 R32/TOD mode selection 1 0 1 × 1 × × : Don’t care Figure 51 Timer Mode Register D2 (TMD2) Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of the lower digit (TWDL: $011) and the upper digit (TWDU: $012). The operation of timer write register D is basically the same as that of timer write register C (TWCL: $00E, TWCU: $00F). Timer write register D (lower digit) (TWDL: $011) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W TWDL3 TWDL2 TWDL1 TWDL0 Figure 52 Timer Write Register D Lower Digit (TWDL) 73 HD404669 Series Timer write register D (upper digit) (TWDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWDU3 TWDU2 TWDU1 TWDU0 Figure 53 Timer Write Register D Upper Digit (TWDU) Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of the lower digit (TRDL) and the upper digit (TRDU). The operation of timer read register D is basically the same as that of timer read registerC (TRCL: $00E, TRCU: $00F). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first. Timer read register D (lower digit) (TRDL: $011) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRDL3 TRDL2 TRDL1 TRDL0 Figure 54 Timer Read Register D Lower Digit (TRDL) Timer read register D (upper digit) (TRDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRDU3 TRDU2 TRDU1 TRDU0 Figure 55 Timer Read Register D Upper Digit (TRDU) 74 HD404669 Series Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function as shown in figure 56. It is reset to $0 by MCU reset. Port mode register C (PMRC: $025) bits 3 and 1 (PMRC3, PMRC1) are reset to 00 by an MCU reset or in stop mode. Bit 2 (PMRC2) is reset to 0 by an MCU reset, but retains its previous setting in stop mode. Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 0 — Read/Write W W W — Bit name PMRC2 PMRC3 PMRC2 PMRC1 Not Used D12/STOPC pin mode selection PMRC1 R40/EVND pin mode selection 0 D12 0 R40 1 STOPC 1 EVND PMRC3 D13/INT0 pin mode selection 0 D13 1 INT0 Figure 56 Port Mode Register C (PMRC) 75 HD404669 Series Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND as shown in figure 57. It is reset to $0 by an MCU reset or in stop mode. Detection edge select register 2 (ESR2: $027) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W ESR23 ESR22 ESR21 ESR20 Bit name EVND detection edge ESR23 ESR22 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 INT4 detection edge ESR21 ESR20 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 Note: * Both falling and rising edges are detected. Figure 57 Detection Edge Select Register 2 (ESR2) 76 HD404669 Series Serial Interface Serial Interface Overview Function • 8-bit serial data transmission/reception Features • Multiple transmit clock sources External clock Internal prescaler output clock System clock • High/low control in idle states Configuration • • • • • • • Serial data register 1 (SR1L: $006, SR1U: $007) Serial mode register 1 A (SM1A: $005) Serial mode register 1 B (SM1B: $028) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Octal counter (OC1) Selector The block diagram of the serial interface is shown in figure 58. 77 HD404669 Series Octal counter (OC1) Serial 1 interrupt request flag (IFS1) Idle control logic SCK1 Clock I/O control logic Serial data register 1 (SR1L, SR1U) ø PER 1/2 1/2 Selector Prescaler S (PSS) ÷2 ÷8 ÷32 ÷128 ÷512 ÷2048 Selector System clock Transfer control SI1 Serial mode register 1A (SM1A) Serial mode register 1B (SM1B) Data bus Clock line Signal line Figure 58 Block Diagram of Serial Interface 78 Internal data bus SO1 HD404669 Series Serial Interface Operation Selecting and Changing the Operating Mode: Table 19 lists the serial interface’s operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial mode register 1A (SM1A: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to serial mode register 1A (SM1A: $005). Note that the serial interface is initialized by writing data to serial mode register 1A(SM1A: $005). Refer to the following Serial Mode Register 1A section for details. Pin Setting: The R41/SCK 1 pin is controlled by writing data to serial mode register 1A (SM1A: $005). The R42/SI 1 and R43/SO 1 pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the following Registers for Serial Interface section for details. Transmit Clock Source Setting: The transmit clock source is set by writing data to serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). Refer to the following Registers for Serial Interface section for details. Data Setting: Transmit data is set by writing data to the serial data register 1 (SR1L: $006, SR1U: $007). Receive data is obtained by reading the contents of the serial data register 1 (SR1L: $006, SR1U: $007). The serial data is shifted by the transmit clock and is input from or output to an external system. The output level of the SO1 pin is invalid until the first data is output after MCU reset, or until the High/Low level control in idle states is performed. Table 19 Serial Interface Operating Modes SM1A PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Serial clock continuous output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and the transfer stops. When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4tcyc to 8192tcyc by setting bits 2 to 0 (SM1A2– SM1A0) of serial mode register 1A (SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 20. 79 HD404669 Series Table 20 Serial Transmit Clock (Prescaler Output) SM1B SM1A Bit 0 Bit 2 Bit 1 Bit 0 Transmit Clock Division Ratio Transmit Clock Frequency 0 0 0 0 (øPER / 2048) ÷ 2 4096t cyc 1 (øPER / 512) ÷ 2 1024t cyc 0 (øPER / 128) ÷ 2 256t cyc 1 (øPER / 32) ÷ 2 64t cyc 0 (øPER / 8) ÷ 2 16t cyc 1 (øPER / 2) ÷ 2 4t cyc 0 (øPER / 2048) ÷ 4 8192t cyc 1 (øPER / 512) ÷ 4 2048t cyc 0 (øPER / 128) ÷ 4 512t cyc 1 (øPER / 32) ÷ 4 128t cyc 0 (øPER / 8) ÷ 4 32t cyc 1 (øPER / 2) ÷ 4 8t cyc 1 1 1 0 0 0 1 1 0 Operating States: The serial interface has the operating states shown in figure 59 in external clock mode and internal clock mode. STS wait state Transmit clock wait state Transfer state Serial clock continuous output state (internal clock mode only) • STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 59). In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), the serial interface enters transmit clock wait state. 80 HD404669 Series External clock mode STS wait state (Octal counter 1 = 000, transmit clock disabled) SM1A write 00 MCU reset 06 SM1A write (IFS1 ← 1) 04 01 STS instruction 02 Transmit clock Transmit clock wait state (Octal counter 1 = 000) 03 8 transmit clocks Transfer state (Octal counter 1 = 000) 05 STS instruction (IFS1← 1) Internal clock mode STS wait state (Octal counter 1 = 000, transmit clock disabled) SM1A write 18 Continuous clock output state (PMRA 0, 1 = 00) 10 13 SM1A write 14 11 STS instruction MCU reset 8 transmit clocks 16 SM1A write (IFS1← 1) Transmit clock 17 12 Transmit clock Transmit clock wait state (Octal counter 1 = 000) Transfer state (Octal counter 1 = 000) 15 STS instruction (IFS1← 1) Note: Refer to the Operating States section for the corresponding encircled numbers. Figure 59 Serial Interface State Transitions • Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register 1 (SR1L: $006, SR1U: $007), and enters the serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04, 14) in transmit clock wait state. • Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes the serial interface, and STS wait state is entered. 81 HD404669 Series If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set by the octal counter that is reset to 000. • Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK 1 pin. When bits 1 and 0 (PMRA1, PMRA0) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait state is entered. High/Low Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state, the output level of the SO 1 pin can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B: $028) to 0 or 1. The high/low control example is shown in figure 60. Note that the high/low level cannot be controlled in transfer state. 82 , HD404669 Series Transmit clock wait state State STS wait state Transmit clock wait state Transfer state STS wait state MCU reset Port selection PMRA write External clock selection SM1A write Output level control in idle states Dummy write for state transition Output level control in idle states SM1B write Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (input) SO1 pin Undefined Idle LSB MSB Idle IFS1 External clock mode Flag reset at transfer completion Transmit clock wait state State STS wait state Transfer state STS wait state MCU reset Port selection PMRA write Internal clock selection SM1A write Output level control in idle states SM1B write Output level control in idle states Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (output) SO1 pin Undefined Idle LSB MSB Idle IFS1 Internal clock mode Flag reset at transfer completion Figure 60 Example of Serial Interface Operation Sequence 83 HD404669 Series Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 61. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. Meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial 1 interrupt request flag is reset, and a dummy write is performed to serial mode register 1A (SM1A: $005). The serial interface then returns to the STS wait state, and the serial 1 interrupt request flag (IFS1: $003, 2) is set again. It is therefore possible to detect a serial clock error by testing the serial 1 interrupt request flag after the dummy write to serial mode register 1A. 84 HD404669 Series Transfer completion (IFS1← 1) Interrupts inhibited IFS1← 0 SM1A write Yes IFS1 = 1? Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state State SCK1 pin (input) Transmit clock wait state Transfer state Transfer state Noise 1 SM1A write IFS1 2 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SM1A is written, IFS1 is set. Flag set because octal counter reaches 000 Flag reset at transfer completion Transmit clock error detection procedure Figure 61 Transmit Clock Error Detection 85 HD404669 Series Notes on Use: • Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register 1A (SM1A: $005) again. • Serial 1 interrupt request flag (IFS1: $003, bit 2) set: If the state is changed from transfer to another by writing to serial mode register 1A (SM1A: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag 1 (IFS1: $003, 2) is not set. To set the serial interrupt request flag, serial mode register 1A (SM1A: $005) write or STS instruction execution must be programmed to be executed after confirming that the SCK 1 pin is at 1, that is, after executing the input instruction to port R4. Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. Serial Mode Register 1A (SM1A: $005) Serial Mode Register 1B (SM1B: $028) Serial Data Register 1 (SR1L: $006, SR1U: $007) Port Mode Register A (PMRA: $004) Miscellaneous Register (MIS: $00C) Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 62). • • • • R4 1/SCK 1 pin function selection Transfer clock selection Prescaler division ratio selection Serial interface initialization Serial mode register 1A (SM1A: $005) is a 4-bit write-only register. It is reset to $0 by an MCU reset or when the MCU switches to stop mode. A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock to the serial data register 1 (SR1L: $006, SR1U: $007) and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that. 86 HD404669 Series Serial mode register 1A (SM1A: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name SM1A3 SM1A2 SM1A1 SM1A0 SM1A3 R41/SCK1 mode selection 0 R41 1 SCK 1 SM1A2 SM1A1 SM1A0 SCK 1 Prescaler Clock source division ratio 0 0 0 Output Prescaler Refer to table 20 0 Output System clock — 1 Input External clock — 1 1 0 1 1 0 0 1 1 Figure 62 Serial Mode Register 1A (SM1A) Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 63). • Serial clock division ratio selection • High/low level control in idle states Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data transfer. Setting bit 0 (SM1B0) of the serial mode register 1B (SM1B: $028) selects the divisor applied to the prescaler output used for the transfer clock. Only bit 0 (SM1B0) is cleared to 0 by an MCU reset or when the MCU switches to stop mode. Bit 1 (SM1B1) of the serial mode register (SM1B: $028) controls the high/low state of the SO1 pin during idle. The SO 1 pin changes state as soon as the high/low control bit is written. The value of this bit is undefined after a reset or when the MCU enters stop mode. 87 HD404669 Series Serial mode register 1B (SM1B: $028) Bit 3 2 1 0 Initial value — — Undefined 0 Read/Write — — W W Bit name SM1B1 Not used Not used SM1B1 SM1B0 Output level control in idle states SM1B0 Transmit clock division ratio 0 Low level 0 Prescaler output divided by 2 1 High level 1 Prescaler output divided by 4 Figure 63 Serial Mode Register 1B (SM1B) Serial Data Register 1 (SR1L: $006, SR1U: $007): This register has the following functions (figures 64 and 65). • Transmission data write and shift • Receive data shift and read Writing data in this register is output from the SO1 pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI1 pin at the rising edge of the transmit clock. Input/output timing is shown in figure 66. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. Serial data register 1 (lower digit) (SR1L: $006) Bit 3 Initial value Read/Write Bit name 2 1 0 Undefined Undefined Undefined Undefined R/W R/W R/W R/W SR1L3 SR1L2 SR1L1 SR1L0 Figure 64 Serial Data Register 1 (SR1L) Serial data register 1 (upper digit) (SR1U: $007) Bit 3 Initial value Read/Write Bit name 2 1 0 Undefined Undefined Undefined Undefined R/W R/W R/W R/W SR1U3 SR1U2 SR1U1 SR1U0 Figure 65 Serial Data Register 1 (SR1U) 88 HD404669 Series Transmit clock 1 2 3 4 5 6 7 8 Serial output LSB data MSB Serial input data latch timing Figure 66 Serial Interface Output Timing Port Mode Register A (PMRA: $004): This register has the following functions (figure 67). • R4 2/SI 1 pin function selection • R4 3/SO 1 pin function selection Port mode register A (PMRA: $004) is a 2-bit write-only register. It is reset to "--00" by an MCU reset or when the MCU switches to stop mode. Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value — — 0 0 Read/Write — — W W Bit name PMRA1 Not used Not used PMRA1 PMRA0 R42/SI1 mode selection PMRA0 R43/SO1 mode selection 0 R42 0 R43 1 SI1 1 SO1 Figure 67 Port Mode Register A (PMRA) 89 HD404669 Series Miscellaneous Register (MIS: $00C): This register has the following function (figure 68). • R4 3/SO 1 pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by an MCU reset or in stop mode. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 Bit name MIS3 Pull-up/Pull-down MOS control 0 Off 1 On MIS2 On 1 Off MIS0 0 0 tRC 0.12207 ms 0.24414 ms* R43/SO1 PMOS control 0 MIS1 1 1 7.8125 ms 0 31.25 ms 1 Not used Note: * The value is applied only when direct transfer operation is used. Figure 68 Miscellaneous Register (MIS) 90 HD404669 Series DTMF Generation Circuit The MCU provides a dual-tone multifrequency (DTMF) generation circuit. Figure 69 shows a block diagram of the DTMF circuit. A DTMF signal consists of two sine waves corresponding to the numbers and symbols on a telephone keypad. DTMF signals are used to access telephone switching equipment. Figure 70 shows the DTMF frequency matrix. The OSC clock (400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz, or 8 MHz) is changed into seven clock signals through the division circuit (1/2, 1/5, 1/9*, 1/10, 1/18*, and 1/20). The DTMF circuit uses one of the seven clock signals, which is selected by the system clock select register 1, 2 (SSR1: $029, SSR2: $02A) depending on the OSC clock frequency. The DTMF circuit has transformed programmable dividers, sine wave counters, and control registers. The DTMF generation circuit is controlled by the following three registers. 91 HD404669 Series Transformation program divider Sine wave counter D/A 2 Feedback VTref Tone generator mode register (TGM) TONER output control TONEC Transformation program divider Sine wave counter D/A Tone generator control register (TGC) 2 Feedback TONEC output control Internal data bus TONER 2 fOSC 1/2 System clock select register 1 (SSR1) 400 kHz* 1/9* 1/10 Selector 1/5 System clock select register 2 (SSR2) 1/18* 1/20 2 Data bus Clock line Signal line Note: * 397.8 kHz when an fOSC frequency of 3.58 MHz or 7.16 MHz is used. Figure 69 92 Block Diagram of DTMF Circuit HD404669 Series R1 (697Hz) 4 5 6 B R2 (770Hz) 7 8 9 C R3 (852Hz) 0 # D R4 (941Hz) C4 (1,633Hz) A C3 (1,477Hz) 3 C2 (1,336Hz) 2 C1 (1,209Hz) 1 Figure 70 DTMF Keypad and Frequencies Tone Generator Mode Register (TGM: $019): The tone generator mode register (TGM: $019) is a 4-bit write-only register that controls the generated DTMF frequencies as shown in figure 71. TGM is initialized to $0 by an MCU reset or in stop mode, watch mode, and subactive mode. Tone generator mode register (TGM: $019) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W TGM3 TGM2 TGM1 TGM0 Bit name TONER output frequencies TGM1 TGM0 C1 (1,209 Hz) 0 0 R1 (697 Hz) 1 C2 (1,336 Hz) 0 1 R2 (770 Hz) 1 0 C3 (1,477 Hz) 1 0 R3 (852 Hz) 1 1 C4 (1,633 Hz) 1 1 R4 (941 Hz) TGM3 TGM2 0 0 0 TONEC output frequencies Figure 71 Tone Generator Mode Register (TGM) 93 HD404669 Series Tone Generator Control Register (TGC: $01A): The tone generator control register (TGC: $01A) is a 3bit write-only register that controls starting and stopping of DTMF signal generation as shown in figure 72. TGC is initialized to 000- by an MCU reset or in stop mode, watch mode, or subactive mode. TONEC output and TONER output are controlled individually by TGC3 and TGC2, and overall DTMF control is performed by TGC1. Tone generator control register (TGC: $01A) Bit 3 2 1 0 Initial value 0 0 0 — Read/Write W W W — TGC3 TGC2 TGC1 Not used Bit name TGC3 TONEC output control (column) TGC1 DTMF enable bit 0 No output 0 DTMF disable 1 TONEC output (active) 1 DTMF enable TGC2 TONER output control (row) 0 No output 1 TONER output (active) Figure 72 Tone Generator Control Register (TGC) System Clock Select Registers 1 and 2 (SSR1: $029 and SSR2: $02A): The system clock select registers 1 and 2 (SSR1: $029 and SSR2: $02A) are 4-bit write-only registers. Applications must set these registers to the values shown in figure 73 that correspond to the frequency of the oscillator circuit connected to the OSC1 and OSC2 pins. If the oscillator frequency and the system clock select register settings differ from the combination shown in figure 73, the DTMF output frequencies will not have the correct values as shown in figure 71. Except for the SSR13 bit, the system clock select registers 1 and 2 (SSR1: $029 and SSR2: $02A) are initialized to $0 by an MCU reset or when the MCU switches to stop mode. 94 HD404669 Series System clock select register 1 (SSR1: $029) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SSR13*1 SSR12 SSR11 SSR10 Bit name SSR12 32 kHz division ratio switch 0 fSUB=fX/8 1 fSUB=fX/4 SSR23 SSR22 SSR11 SSR10 System clock selection 0 0 0 1 SSR13 32 kHz oscillation stop setting 0 Oscillation continues in stop mode 1 Oscillation stops in stop mode 1 0 400kHz 1 800 kHz 0 2 MHz 1 4 MHz 3.58 MHz 1 × × 0 1 1 8 MHz 1 × × 7.16 MHz × : Don't care System clock select register 2 (SSR2: $02A) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SSR23 SSR22 SSR21 SSR20 Bit name SSR21 SSR20 0 0 1 System clock division ratio selection*2 Division by 4 1 Division by 8 0 Division by 16 1 Division by 32 Notes: 1. SSR13 is cleared to 0 only by RESET input. In the case of STOPC input in stop mode it retains its current value. SSR13 is not reset in stop mode 2. The DTMF generation circuit frequencies are not affected by the system clock division ratio setting. Figure 73 System Clock Select Register 1 and 2 (SSR1, SSR2) 95 HD404669 Series DTMF Output: The sine waves of the row-group and column-group are output from the DTMF output pins (TONER and TONEC). These are output by a high-precision resistance-ladder type D/A converter. Figure 74 shows the TONE output pin equivalent circuit, and figure 75 shows the output waveform. One output waveform cycle is composed of 32 slots, giving stable output with a low distortion factor. Table 21 shows the deviation of the output frequencies with respect to the standard DTMF signals. Table 21 Frequency Deviation of the MCU from Standard DTMF (fOSC=400kHz, 800kHz, 2MHz, 4MHz, 8MHz ) Standard DTMF (Hz) MCU (Hz) Deviation from Standard (%) R1 697 694.44 –0.37 R2 770 769.23 –0.10 R3 852 851.06 –0.11 R4 941 938.97 –0.22 C1 1,209 1,212.12 0.26 C2 1,336 1,333.33 –0.20 C3 1,477 1,481.48 0.30 C4 1,633 1,639.34 0.39 Table 22 Frequency Deviation of the MCU from Standard DTMF (fOSC=3.58kHz, 7.16MHz ) Standard DTMF (Hz) MCU (Hz) Deviation from Standard (%) R1 697 690.58 –0.92 R2 770 764.96 –0.65 R3 852 846.33 –0.67 R4 941 933.75 –0.77 C1 1,209 1,205.39 –0.30 C2 1,336 1,325.92 –0.75 C3 1,477 1,473.25 –0.25 C4 1,633 1,630.23 –0.17 Notes: 1. The DTMF signal frequency deviation must be within ±1.5%, totaling the values in tables 21 and 22 and the precision of the oscillator used. When an f OSC frequency of 3.58 MHz or 7.16 MHz is used, in particular, the frequency deviation is greater (max - 0.92%) than with an fOSC frequency of 400 kHz, 800 kHz, 2 MHz, 4 MHz, or 8 MHz, and thorough consultation with the oscillator manufacturer is essential before deciding on the oscillator to be used. 2. This frequency deviation does not include the frequency deviation of the oscillator. Also, the ratio of oscillator waveform high-level width and low-level width in this case is 50% : 50%. 96 HD404669 Series Switch control VTref GND TONER TONEC Figure 74 Tone Output Equivalent Circuit VTref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND Time slots Figure 75 Waveform of Tone Output 97 HD404669 Series Comparator The MCU has a built-in comparator that compare an input voltage with the reference voltage (VCref ). The comparator block diagram is shown in figure 76. COMP1 + Comparator Compare data register (CDR) Internal data bus COMP0 Selector The comparator can operate in active mode and subactive mode. They are halted in other modes. VCref 2 Compare enable register (CER) Figure 76 Comparator Block Diagram Comparator Operation (1) Analog input pin selection is performed by bits 0 and 1 (CER0, CER1) of the compare enable register (CER). Setting bit 3 (CER3) to 1 places the RD0/COMP0 and RD1/COMP1 pins in analog input mode and starts comparator operation. While comparator operation is in progress, none of these pins (including pins not used for comparison) can be used as R port pins. (2) The compare result can be read by means of a bit test instruction (TM or TMD) on the compare data register (CDR) bit corresponding to the selected analog input pin. 98 HD404669 Series Registers Used by Comparator • Compare enable register (CER: $018) • Compare data register (CDR: $017) Compare enable register (CER: $018): The compare enable register (CER) is a 3-bit write-only register that selects comparator operation and the analog input pin (figure 77). CER is reset by an MCU reset or in stop mode. Compare enable register (CER: $018) Bit 3 2 1 0 Initial value 0 — 0 0 Read/Write W — W W Bit name CER3 Not Used CER1 CER1 CER0 0 0 COMP0 1 COMP1 × Not Used 1 CER3 CER0 Analog input pin selection Comparator operation selection 0 Comparator operation not selected: Digital input mode RD0/COMP0 and RD1/COMP1 pins function as R port pins 1 Comparator operation selected: Analog input mode RD0/COMP0 and RD1/COMP1 pins function as comparator pins × : Don't care Figure 77 Compare Enable Register (CER) Compare data register (CDR: $017): The compare data register (CDR) is a 2-bit read-only register that holds the result of the comparison between the analog input pin and the reference voltage (figure 78). When comparator operation is started (CER3 is set to 1), the result of the comparison between the analog input pin selected by the compare enable register (CER) and the reference voltage is read into the corresponding bit of the compare data register (CDR). The value of the other bits in CDR is undetermined. The CDR value is not retained after the comparator operation (when CER3 = 0), and is undetermined except during comparator operation. 99 HD404669 Series Compare data register (CDR: $017) Bit 3 2 Initial value — — Read/Write — — Bit name CDR 0 1 0 Undetermined Undetermined R Not Used Not Used CDR1 R CDR0 Result of comparison between COMP0 pin and reference voltage 0 COMP0 pin < reference voltage 1 COMP0 pin > reference voltage CDR1 Result of comparison between COMP1 pin and reference voltage 0 COMP1 pin < reference voltage 1 COMP1 pin > reference voltage Figure 78 Compare Data Register (CDR) 100 HD404669 Series ZTATTM Microcomputer with Built-in Programmable ROM 1. Precautions for use of ZTATTM microcomputer with built-in programmable ROM (1) Precautions for writing to programmable ROM built in ZTATTM microcomputer In the ZTAT TM microcomputer with built-in plastic mold one-time programmable ROM, incomplete electrical connection between the PROM writer and socket adapter causes writing errors and, makes the computer unoperatable. To enhance the writing efficiency, attention should be paid to the following points: (a) Make sure that the socket adapter is firmly fixed to the PROM writer and connected electrically with each other (neither opened nor shorted), before starting the writing process. (b) To secure the electrical connection between the contact pin and IC lead, make sure that there is no foreign substance on the contact pin of the socket adapter, which may cause improper electrical connection. (c) When inserting the IC, be careful to protect the IC lead from bending in order to secure the electrical connection between the contact pin and IC lead. If the lead is bent, correct the bending and insert it again. (d) If any trouble is noticed during a blank check to be performed to prevent erroneous writing due to improper electrical connection, carry out the writing process again according to above steps (a), (b), and (c). (e) During the writing process, do not touch the socket adapter and IC to prevent erroneous writing. (f) To write continuously in the IC, follow steps (a), (b), (c), (d) and (e). (g) If a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the PROM writer, socket adapter, etc. for defects. (h) If any problem is noticed in the written program or in the program after being left at a high temperature, consult our technical staff. (2) Precautions when new PROM writer, socket adapter or IC is used When a new PROM writer, socket adapter or IC is employed, breakdown of the IC may occur or its writing may become impossible because the noise, overshoot, timing or other electrical characteristics may be inconsistent with the assured IC writing characteristics. To avoid such troubles, check the following points before starting the writing process. (a) To ensure stable writing operation, check that the VCC of the power supplied to the PROM writer, power source current capacity of VPP, and current consumption at the time of writing to IC are provided with sufficient margin. (b) To prevent breakdown of the IC, check that the power source voltage between GND-V CC and GNDVPP, and overshoot or undershoot of the power source at the connecting terminal of the socket adapter are within the ratings. Particularly, if the overshoot or undershoot exceeds the maximum rating, the pin connection may be damaged, leading to permanent breakdown. If overshoot or undershoot occurs, recheck the power source damping resistance of capacity. (c) To prevent breakdown of the IC and for stable writing and reading operation, insert the IC into the socket adapter and check the power noise between the GND-VCC and GND-VPP near the IC connecting 101 HD404669 Series terminal. If power source noise is noticed, insert an appropriate capacitor between the GND power sources depending on the noise generated. In case of high frequency noise, insert a capacitor of low inductance. (d) For stable writing and reading operation, insert the IC into the socket adapter and check the input waveform, timing and noise near the R/W, CS, address and data terminals. Particularly, since recent ICs have increased in speed, caution should be exercised against the noise to the power source or address due to crosstalk from the output data terminal. To avoid these problems, inserting a low inductance capacitor between the GND and power source or inserting a damping resistance to the output data terminal is effective. (e) Particularly, when a multiple PROM writer is used, perform above items (a), (b), (c), and (d) assuming all ICs inserted into the socket adapter. (f) In the case of a multiple PROM writer, when an unacceptable result is noticed during a blank check performed to prevent erroneous writing due to improper electrical connection of the power source, etc., rewriting is impossible unless every writing process can be stopped. Therefore, the potential increases due to erroneous writing because of improper connection. Be sure to check the electrical connection between the PROM writer and socket adapter and IC. (g) If any abnormality is noticed while checking a written program, consult our technical staff. 2. Programming of Built-in programmable ROM The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM. PROM mode is set up by setting the TEST, M0, and M1 terminals to “Low” level and the RESET terminal to “High” level. Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256. Using a socket adapter for specific use of each product, programming is possible with a general-purpose PROM writer. Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to write to a 16kword of built-in PROM with a general-purpose PROM writer, specify 32kbyte address ($0000-$7FFF). An example of PROM memory map is shown in figure 80. Notes: 1. When programming with a PROM writer, set up each ROM size to the address given in table 24. If it is programmed erroneously to an address given in Table 24 or later, check of writing of PROM may become impossible. Particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. Set the data in unused addresses to $FF. 2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. Be sure to check that they are properly set to the writer before starting the writing process. 102 HD404669 Series 3. Two levels of program voltages (VPP) are available for the PROM: 12.5 V and 21 V. Our product employs a V PP of 12.5 V. If a voltage of 21 V is applied, permanent breakdown of the product will result. The VPP of 12.5 V is obtained for the PROM writer by setting it according to the Intel 27256 specifications. Writing/verification Programming of the built-in program ROM employs a high speed programming method. With this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. A basic programming flow chart is shown in figure81 and a timing chart in figure82. For precautions for PROM writing procedure, refer to "ZTAT TM Microcomputer On-chip Programmable ROM Characteristics and Usage Notes." Table 23 Selection of Mode Pins Mode CE OE VPP O0–O4 Writing “Low” “High” VPP Data input Verification “High” “Low” VPP Data output Prohibition of programming “High” “High” VPP High impedance Table 24 PROM Writer Program Address ROM size Address 8k $0000~$3FFF 12k $0000~$5FFF 16k $0000~$7FFF 103 HD404669 Series Programmable ROM (HD407A4669) The HD407A4669 is a ZTATTM microcomputer with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description Pin No. MCU Mode FP-64A Pin Name I/O 1 RE0/VCref I 2 TEST 3 4 5 RESET I VCC 6 X1 I GND 7 X2 O 8 GND – GND – 9 D0 I/O CE 10 D1 I/O OE 11 D2 I/O 12 D3 I/O 13 D4 14 D5 15 D9 I/O 16 D10 I/O A13 I 17 D11 I/O A14 18 D12 /STOPC I A9 19 D13 /INT0 I 20 R00/INT 1 I/O 21 R01/INT 2 I/O GND 22 R02/INT 3 I/O 23 R03/INT 4 I/O 24 R10 I/O A5 I 25 R11 I/O A6 26 R12 I/O A7 27 R13 I/O 28 R20 I/O 29 R21 30 R22 31 32 104 PROM Mode Pin No. MCU Mode FP-64A Pin Name PROM Mode Pin Name I/O I/O Pin Name I/O 33 R33 I/O I GND – 34 R32/TOD I/O OSC1 I VCC – 35 R31/TOC I/O OSC2 O 36 R40/EVND I/O – 37 R41/SCK1 I/O – 38 R42/SI1 I/O 39 R43/SO1 I/O 40 R60 I/O A1 I I 41 I 42 R61 I/O A2 I R62 I/O A3 I VCC – VCC – 43 R63 I/O A4 I 44 R70 I/O O0 I/O I/O 45 R71 I/O O1 I/O I/O 46 R72 I/O O2 I/O 47 R73 I/O O3 I/O 48 R80 I/O O4 I/O I 49 R81 I/O I 50 R82 I/O VPP – 51 R83 I/O GND – 52 R90 I/O O4 I/O – 53 R91 I/O O3 I/O 54 R92 I/O O2 I/O 55 R93 I/O O1 I/O 56 RA0 I/O O0 I/O I 57 RA1 I/O VCC – I 58 SEL I A8 I 59 VCC – VCC – A0 I 60 TONEC O I/O A10 I 61 TONER O I/O A11 I 62 VTref I R23 I/O A12 I 63 RD0/COMP0 I R30 I/O 64 RD1/COMP1 I HD404669 Series Notes: 1. I/O: I/O pin, I: Input pin, O: Output pin 2. As there are two each of pins O0 to O 4, the respective pairs should be shorted. 3. Unused data pins (O 5 to O 7) on the PROM programmer side should be handled as shown below on the socket side. VCC O5, O6, O7 4. Pin A 9 should be handled as shown below on the socket side. VCC A9 Programmer side HD407A4669 105 O2 O3 O4 54 53 52 49 O1 55 1 48 O4 GND 2 47 O3 VCC 3 46 O2 4 45 O1 VCC 5 44 O0 GND 6 43 A4 7 42 A3 41 A2 40 A1 GND CE 8 HD407A4669H 9 FP-64A (Top view) 13 36 14 35 15 34 16 33 Figure 79 Pin Arrangement in PROM Mode 32 31 A12 A11 30 A10 29 28 A0 27 A8 26 39 A7 A6 A5 GND GND VPP A9 17 A14 25 37 24 12 23 VCC 22 38 21 11 20 VCC 19 10 18 OE A13 106 50 O0 56 51 VCC 57 58 59 60 61 62 63 64 VCC HD404669 Series HD404669 Series $0000 $0001 . . . $001F $0020 . . . $007F $0080 . . . 1 1 1 1 1 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Lower 5 bits Upper 5 bits $0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern (4,096 words) $0FFF $1000 $1FFF $2000 Program (16,384 words) JMPL instruction (jump to RESET, STOPC routine) JMPL instruction (jump to INT 0 routine) JMPL instruction (jump to INT 1 routine) JMPL instruction (jump to timer A routine) JMPL instruction (jump to INT2 routine) JMPL instruction (jump to timer C, INT3 routine) JMPL instruction (jump to timer D, INT4 routine) JMPL instruction (jump to serial 1 routine) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $3FFF $7FFF Upper three bits are not to be used (fill them with 111) Figure 80 Memory Map in PROM Mode 107 HD404669 Series Start Set write/verify modes V CC = 6.0 ± 0.25 V, V PP = 12.5 ± 0.3 V Address = 0 n=0 n + 1→ n Yes No Program t PW =1 ms ± 5% n < 25? No Address + 1 → Address Verification OK? Yes Program t OPW = 3n ms Last address? No Yes VCC Reject Set read mode = 5.0 ± 0.5 V, V PP = V CC ± 0.6 V No Read all addresses ? Yes End Figure 81 Flowchart of High-Speed Programming 108 HD404669 Series Programming Electrical Characteristics DC Characteristics (VCC = 6.0 V ± 0.25 V, V PP = 12.5 V ± 0.3 V, GND = 0V, Ta = 25°C ± 5°C, unless otherwise specified) Item Pin(s) Symbol Min Typ Max Unit Test Condition Input high voltage level O0–O4, A0–A14, OE, CE VIH 2.2 — VCC + 0.3 V Input low voltage level O0–O4, A0–A14, OE, CE VIL –0.3 — 0.8 V Output high voltage level O0–O4 VOH 2.4 — — V I OH = –200 µA Output low voltage level O0–O4 VOL — — 0.4 V I OL = 1.6 mA Input leakage current O0–O4, A0–A14, OE, CE I IL — — 2 µA Vin = 5.25 V/0.5 V VCC current I CC — — 30 mA VPP current I PP — — 40 mA AC Characteristics (VCC = 6.0 V ± 0.25 V, V PP = 12.5 V ± 0.3 V, GND = 0V, Ta = 25°C ± 5°C, unless otherwise specified) Item Symbol Min Typ Max Unit Test Condition Address setup time t AS 2 — — µs See figure 82 OE setup time t OES 2 — — µs Data setup time t DS 2 — — µs Address hold time t AH 0 — — µs Data hold time t DH 2 — — µs Data output disable time t DF — — 130 ns VPP setup time t VPS 2 — — µs Program pulse width t PW 0.95 1.0 1.05 ms CE pulse width during overprogramming t OPW 2.85 — 78.75 ms VCC setup time t VCS 2 — — µs Data output delay time t OE 0 — 500 ns Note: Input pulse level: 0.8 V to 2.2 V Input rise/fall time: ≤ 20 ns Input timing reference levels: 1.0 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V 109 HD404669 Series Write Address Verify tAS tAH Data In Stable Data tDS VPP VCC Data Out Valid tDH tDF VPP GND tVPS VCC GND tVCS CE tPW tOES OE tOPW Figure 82 PROM Write/Verify Timing 110 tOE HD404669 Series ZTATTM Microcomputer Usage Notes ZTATTM Microcomputer On-Chip Programmable ROM Characteristics and Useage Notes Principles of Programming/Erasure: A memory cell in a ZTATT M microcomputer is the same as an EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an SiO 2 film. The change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0. The charge in a memory cell may decrease with time. This decrease is usually due to one of the following causes: • Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure principle. • Heat excites trapped electrons, allowing them to escape. • High voltages between the control gate and drain may erase electrons. If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However, electron erasure does not often occur because defective devices are detected and removed at the testing stage. Control gate Control gate SiO2 SiO2 Floating gate Floating gate Drain Source N+ N+ Write (0) Drain Source N+ N+ Erasure (1) Figure 83 Cross-Sections of a PROM Cell PROM Programming: PROM memory cells must be programmed under specific voltage and timing conditions. The higher the programming voltage VPP and the longer the programming pulse t PW is applied, the more electrons are injected into the floating gates. However, if V PP exceeds specifications, the pn junctions may be permanently damaged. Pay particular attention to overshooting in the PROM programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. The ZTAT TM microcomputer is electrically connected to the PROM programmer by a socket adapter. Therefore, note the following points: 111 HD404669 Series • Check that the socket adapter is firmly mounted on the PROM programmer. • Do not touch the socket adapter or the LSI during the programming. Touching them may affect the quality of the contacts, which will cause programming errors. PROM Reliability after Programming: In general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. These initial defects can be detected and rejected by screening. Baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure section.) ZTAT TM microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but Hitachi recommends that each device be exposed to 150°C at one atmosphere after it is programmed, to ensure its best performance. The recommended screening procedure is shown in figure 84. Write the program data and verify the values written Expose to high temperature, without power 150°C ± 10°C, 48 h +8 h * –0 h Program read check VCC = 4.5 V or 5.5 V Note: * Exposure time is measured from when the temperature in the heater reaches 150°C. Figure 84 Recommended Screening Procedure Note: If programming errors occur continuously during PROM programming, suspend programming and check for problems in the PROM programmer or socket adapter, using a windowed-package microcomputer with on-chip EPROM, etc. ..... If programming verification indicates errors in programming or after high-temperature exposure, please inform Hitachi. Write rate: A write rate of 95% or above is guaranteed. 112 HD404669 Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 85 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. For $090 to $25F, a bank setting must be made in the bank register (V: $03F). Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. W register W1 W0 RAM address X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Register Indirect Addressing 1st word of Instruction Opcode 2nd word of Instruction d RAM address 9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Direct Addressing Instruction Opcode 0 RAM address 0 0 1 m3 m2 0 m1 m0 0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Memory Register Addressing Figure 85 RAM Addressing Modes 113 HD404669 Series ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 86 and described below. 1st word of instruction [JMPL] [BRL] [CALL] Opcode p3 Program counter 2nd word of instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Program counter Opcode b7 b6 b5 b4 b3 b2 b1 b0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 Program counter 0 0 0 d5 Opcode 0 0 0 d4 d3 d2 d1 d0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 0 Program counter B0 A3 A2 A1 A0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 86 ROM Addressing Modes 114 B2 B1 Accumulator HD404669 Series Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13–PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC 7–PC0) with eight-bit immediate data. A branch by a BR instruction located at a page boundary differs from other cases: see figure 88. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000– $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight highorder bits (PC13–PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 88. If bit 8 of the ROM data is 1, the lower eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, the lower eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. Branch destination of a BR instruction on a page boundary: When a BR instruction is on a page boundary (256n + 255), the program counter will advance to the next page because of the hardware architecture. Therefore, when using a BR instruction on a page boundary, the branch destination should be set in the next page (see figure 88). HMCS400 Series cross assemblers are provided with an automatic paging function that automatically turns the ROM page, irrespective of the model. 115 HD404669 Series Instruction [P] Opcode p3 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register ROM data B3 B2 B1 B0 A3 A 2 A1 A 0 If RO 8 = 1 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R23 R22 R21 R20 R13 R12 R11 R10 If RO 9 = 1 Pattern Output Figure 87 P Instruction 256 (n – 1) + 255 BR AAA 256n AAA BBB 256n + 254 256n + 255 256 (n + 1) NOP BR BR BBB AAA NOP Figure 88 Branching when the Branch Destination is on a Page Boundary 116 HD404669 Series Instruction Set The MCU has 101 instructions, classified into the following 10 groups: • • • • • • • • • • Immediate instructions Register-to-register instructions RAM addressing instructions RAM register instructions Arithmetic instructions Compare instructions RAM bit manipulation instructions ROM addressing instructions Input/output instructions Control instructions The functions of these instructions are listed in tables 25 to 34, and an opcode map is shown in table 35. Table 25 Immediate Instructions Status Words/ Cycles Operation Mnemonic Operation Code Function Load A from immediate LAI i 1 0 0 0 1 1 i3 i2 i1 i0 i→A 1/1 Load B from immediate LBI i 1 0 0 0 0 0 i3 i2 i1 i0 i→B 1/1 Load memory from immediate LMID i,d 0 1 1 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i→M 2/2 Load memory from immediate, increment Y LMIIY i 1 0 1 0 0 1 i3 i2 i1 i0 i → M, Y + 1 → Y NZ 1/1 117 HD404669 Series Table 26 Register-Register Instructions Status Words/ Cycles Operation Mnemonic Operation Code Function Load A from B LAB 0 0 0 1 0 0 1 0 0 0 B→A 1/1 Load B from A LBA 0 0 1 1 0 0 1 0 0 0 A→B 1/1 Load A from W LAW 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W→A 2/2* Load A from Y LAY 0 0 1 0 1 0 1 1 1 1 Y→A 1/1 Load A from SPX LASPX 0 0 0 1 1 0 1 0 0 0 SPX → A 1/1 Load A from SPY LASPY 0 0 0 1 0 1 1 0 0 0 SPY → A 1/1 Load A from MR LAMR m 1 0 0 1 1 1 m3 m2 m1 m0 MR (m) → A 1/1 Exchange MR and A XMRA m 1 0 1 1 1 1 m3 m2 m1 m0 MR (m) ↔ A 1/1 Note: * The assembler automatically provides an operand for the second word of the LAW instruction. Table 27 RAM Address Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Load W from immediate LWI i 0 0 1 1 1 1 0 0 i1 i0 i→W 1/1 Load X from immediate LXI i 1 0 0 0 1 0 i3 i2 i1 i0 i→X 1/1 Load Y from immediate LYI i 1 0 0 0 0 1 i3 i2 i1 i0 i→Y 1/1 Load W from A LWA 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A→W 2/2* Load X from A LXA 0 0 1 1 1 0 1 0 0 0 A→X 1/1 Load Y from A LYA 0 0 1 1 0 1 1 0 0 0 A→Y 1/1 Increment Y IY 0 0 0 1 0 1 1 1 0 0 Y+1→Y NZ 1/1 Decrement Y DY 0 0 1 1 0 1 1 1 1 1 Y–1→Y NB 1/1 Add A to Y AYY 0 0 0 1 0 1 0 1 0 0 Y+A→Y OVF 1/1 Subtract A from Y SYY 0 0 1 1 0 1 0 1 0 0 Y–A→Y NB 1/1 Exchange X and SPX XSPX 0 0 0 0 0 0 0 0 0 1 X ↔ SPX 1/1 Exchange Y and SPY XSPY 0 0 0 0 0 0 0 0 1 0 Y ↔ SPY 1/1 Exchange X and SPX, Y and SPY XSPXY 0 0 0 0 0 0 0 0 1 1 X ↔ SPX,Y ↔ SPY 1/1 Note: * The assembler automatically provides an operand for the second word of the LWA instruction. 118 HD404669 Series Table 28 RAM Register Instructions Operation Mnemonic Operation Code Load A from memory LAM(XY) 0 0 1 0 0 1 0 0 y Load A from memory LAMD d Load B from memory Function Status Words/ Cycles M→A (X ↔ SPX, Y ↔ SPY) 1/1 0 1 1 0 0 1 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M→A 2/2 LBM(XY) 0 0 0 1 0 0 0 0 y x M→B (X ↔ SPX, Y ↔ SPY) 1/1 Load memory from A LMA(XY) 0 0 1 0 0 1 0 1 y x A→M (X ↔ SPX, Y ↔ SPY) 1/1 Load memory from A LMAD d 0 1 1 0 0 1 0 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A→M 2/2 Load memory from A, increment Y LMAIY(X) 0 0 0 1 0 1 0 0 0 x A → M, Y + 1 → Y (X ↔ SPX) NZ 1/1 Load memory from A, decrement Y LMADY(X) 0 0 1 1 0 1 0 0 0 x A → M, Y – 1 → Y (X ↔ SPX) NB 1/1 Exchange memory and A XMA(XY) 0 0 1 0 0 0 0 0 y M↔A (X ↔ SPX, Y ↔ SPY) 1/1 Exchange memory and A XMAD d 0 1 1 0 0 0 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M↔A 2/2 Exchange memory and B XMB(XY) 0 0 1 1 0 0 0 0 y M↔B (X ↔ SPX, Y ↔ SPY) 1/1 x x x Note: The meanings of (XY) and (X) are as follows: Each instruction marked with (XY) has 4 mnemonics, each with different object codes. For example, different values of x and y of the opcode of the LAM(XY) instruction are given below. Mnemonic y x Function LAM 0 0 None LAMX 0 1 X ↔ SPX LAMY 1 0 Y ↔ SPY LAMXY 1 1 X ↔ SPX, Y ↔ SPY Each instruction marked with (X) has 2 mnemonics, each with different object codes. For example, different values of x of the opcode of the LMAIY(X) instruction are given below. Mnemonic x Function LMAIY 0 None LMAIYX 1 X ↔ SPX 119 HD404669 Series Table 29 Arithmetic Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Add immediate to A AI i 1 0 1 0 0 0 i3 i2 i1 i0 A+i→A OVF 1/1 Increment B IB 0 0 0 1 0 0 1 1 0 0 B+1→B NZ 1/1 Decrement B DB 0 0 1 1 0 0 1 1 1 1 B–1→B NB 1/1 Decimal adjust for addition DAA 0 0 1 0 1 0 0 1 1 0 1/1 Decimal adjust for subtraction DAS 0 0 1 0 1 0 1 0 1 0 1/1 Negate A NEGA 0 0 0 1 1 0 0 0 0 0 A+1→A 1/1 Complement B COMB 0 1 0 1 0 0 0 0 0 0 B→ B 1/1 Rotate right A with carry ROTR 0 0 1 0 1 0 0 0 0 0 1/1 Rotate left A with carry ROTL 0 0 1 0 1 0 0 0 0 1 1/1 Set carry SEC 0 0 1 1 1 0 1 1 1 1 1 → CA 1/1 Reset carry REC 0 0 1 1 1 0 1 1 0 0 0 → CA 1/1 Test carry TC 0 0 0 1 1 0 1 1 1 1 Add A to memory AM 0 0 0 0 0 0 1 0 0 0 Add A to memory AMD d Add A to memory with carry CA 1/1 M+A→A OVF 1/1 0 1 0 0 0 0 1 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M+A→A OVF 2/2 AMC 0 0 0 0 0 1 1 0 0 0 M + A + CA → A OVF → CA OVF 1/1 Add A to memory with carry AMCD d 0 1 0 0 0 1 1 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M + A + CA → A OVF → CA OVF 2/2 Subtract A from memory with carry SMC 0 0 1 0 0 1 1 0 0 0 M – A – CA → A NB → CA NB 1/1 Subtract A from memory with carry SMCD d 0 1 1 0 0 1 1 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M – A – CA → A NB → CA NB 2/2 OR A and B OR 0 1 0 1 0 0 0 1 0 0 A∪B→A AND memory with A ANM 0 0 1 0 0 1 1 1 0 0 A∩M→A NZ 1/1 AND memory with A ANMD d 0 1 1 0 0 1 1 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A∩M→A NZ 2/2 OR memory with A ORM 0 0 0 0 0 0 1 1 0 0 A∪M→A NZ 1/1 OR memory with A ORMD d 0 1 0 0 0 0 1 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A∪M→A NZ 2/2 EOR memory with A EORM 0 0 0 0 0 1 1 1 0 0 A⊕M→A NZ 1/1 EOR memory with A EORMD d 0 1 0 0 0 1 1 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A⊕M→A NZ 2/2 120 1/1 HD404669 Series Table 30 Compare Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Immediate not equal to memory INEM i 0 0 0 0 1 0 i3 i2 i1 i0 i≠M NZ 1/1 Immediate not equal to memory INEMD i,d 0 1 0 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i≠M NZ 2/2 A not equal to memory ANEM 0 0 0 0 0 0 0 1 0 0 A≠M NZ 1/1 A not equal to memory ANEMD d 0 1 0 0 0 0 0 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A≠M NZ 2/2 B not equal to memory BNEM 0 0 0 1 0 0 0 1 0 0 B≠M NZ 1/1 Y not equal to immediate YNEI i 0 0 0 1 1 1 i3 i2 i1 i0 Y≠i NZ 1/1 Immediate less than or equal to memory ILEM i 0 0 0 0 1 1 i3 i2 i1 i0 i≤M NB 1/1 Immediate less than or equal to memory ILEMD i,d 0 1 0 0 1 1 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i≤M NB 2/2 A less than or equal to memory ALEM 0 0 0 0 0 1 0 1 0 0 A≤M NB 1/1 A less than or equal to memory ALEMD d 0 1 0 0 0 1 0 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A≤M NB 2/2 B less than or equal to memory BLEM 0 0 1 1 0 0 0 1 0 0 B≤M NB 1/1 A less than or equal to immediate ALEI i 1 0 1 0 1 1 i3 i2 i1 i0 A≤i NB 1/1 Status Words/ Cycles Table 31 RAM Bit Manipulation Instructions Operation Mnemonic Operation Code Function Set memory bit SEM n 0 0 1 0 0 0 0 1 n1 n0 1 → M (n) 1/1 Set memory bit SEMD n,d 0 1 1 0 0 0 0 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 → M (n) 2/2 Reset memory bit REM n 0 0 1 0 0 0 1 0 n1 n0 0 → M (n) 1/1 Reset memory bit REMD n,d 0 1 1 0 0 0 1 0 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 → M (n) 2/2 Test memory bit TM n 0 0 1 0 0 0 1 1 n1 n0 M (n) 1/1 Test memory bit TM n,d 0 1 1 0 0 0 1 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M (n) 2/2 121 HD404669 Series Table 32 ROM Address Instructions Status Words/ Cycles 1 1 b7 b6 b5 b4 b3 b2 b1 b0 1 1/1 BRL u 0 1 0 1 1 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2/2 Long jump unconditionally JMPL u 0 1 0 1 0 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Subroutine jump on status 1 CAL a 0 1 1 1 a5 a4 a3 a2 a1 a0 1 1/2 Long subroutine jump on status 1 CALL u 0 1 0 1 1 0 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2/2 Table branch TBR p 0 0 1 0 1 1 p3 p2 p1 p0 1 1/1 Return from subroutine RTN 0 0 0 0 0 1 0 0 0 0 Return from interrupt RTNI 0 0 0 0 0 1 0 0 0 1 Operation Mnemonic Operation Code Branch on status 1 BR b Long branch on status 1 Function 2/2 1/3 1 → IE, carry restored ST 1/3 Status Words/ Cycles Table 33 Input/Output Instructions Operation Mnemonic Operation Code Function Set discrete I/O latch SED 0 0 1 1 1 0 0 1 0 0 1 → D (Y) 1/1 Set discrete I/O latch direct SEDD m 1 0 1 1 1 0 m3 m2 m1 m0 1 → D (m) 1/1 Reset discrete I/O latch RED 0 0 0 1 1 0 0 1 0 0 0 → D (Y) 1/1 Reset discrete I/O latch direct REDD m 1 0 0 1 1 0 m3 m2 m1 m0 0 → D (m) 1/1 Test discrete I/O latch TD 0 0 1 1 1 0 0 0 0 0 D (Y) 1/1 Test discrete I/O latch direct TDD m 1 0 1 0 1 0 m3 m2 m1 m0 D (m) 1/1 Load A from R-port register LAR m 1 0 0 1 0 1 m3 m2 m1 m0 R (m) → A 1/1 Load B from R-port register LBR m 1 0 0 1 0 0 m3 m2 m1 m0 R (m) → B 1/1 Load R-port register from A LRA m 1 0 1 1 0 1 m3 m2 m1 m0 A → R (m) 1/1 Load R-port register from B LRB m 1 0 1 1 0 0 m3 m2 m1 m0 B → R (m) 1/1 Pattern generation Pp 0 1 1 0 1 1 p3 p2 p1 p0 122 1/2 HD404669 Series Table 34 Control Instructions Function Status Words/ Cycles Operation Mnemonic Operation Code No operation NOP 0 0 0 0 0 0 0 0 0 0 1/1 Start serial STS 0 1 0 1 0 0 1 0 0 0 1/1 Standby mode/watch mode* SBY 0 1 0 1 0 0 1 1 0 0 1/1 Stop mode/watch mode STOP 0 1 0 1 0 0 1 1 0 1 1/1 Note: * Only after a transition from subactive mode. 123 HD404669 Series Table 35 Opcode Map 0 R8 L 0 1 2 3 4 R9 H 0 NOP XSPX XSPY XSPXY ANEM 1 RTN RTNI 6 ALEM LBM(XY) NEGA C ORM EORM LAB IB AYY LASPY IY RED D E LASPX F TC YNEI i(4) 8 9 XMA(XY) SEM n(2) LAM(XY) LMA(XY) ROTR ROTL REM n(2) SMC DAA B TM n(2) ANM DAS LAY TBR p(4) C XMB(XY) BLEM LBA D LMADY(X) SYY LYA E TD SED LXA F B BNEM 7 A A AM ILEM i(4) LMAIY(X) 9 AMC INEM i(4) 6 DB DY REC SEC LWI i(2) 0 LBI i(4) 1 LYI i(4) 2 LXI i(4) 3 LAI i(4) 4 LBR m(4) 5 LAR m(4) 6 REDD m(4) 7 LAMR m(4) 8 AI i(4) 9 LMIIY i(4) A TDD m(4) B ALEI i(4) C D LRB m(4) LRA m(4) E SEDD m(4) F XMRA m(4) 1-word/2-cycle instruction 124 8 2 5 1 7 3 4 0 5 1-word/3-cycle instruction RAM direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction HD404669 Series 1 R8 L 0 1 2 3 4 5 6 7 8 9 A B C R9 H 0 LAW ANEMD AMD ORMD 1 LWA ALEMD AMCD EORMD 2 INEMD i(4) 3 ILEMD i(4) 4 0 COMB OR STS 5 JMPL p(4) 6 CALL p(4) 7 BRL p(4) 8 XMAD 9 LAMD SEMD n(2) LMAD SBY REMD n(2) SMCD A LMID i(4) B P p(4) D E F STOP TMD n(2) ANMD C D CAL a(6) E F 0 1 2 3 4 5 6 7 1 BR b(8) 8 9 A B C D E F 1-word/2-cycle instruction 1-word/3-cycle instruction RAM direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction 125 HD404669 Series Absolute Maximum Ratings Item Symbol Value Unit Supply voltage VCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +14.0 V Pin voltage VT –0.3 to (VCC + 0.3) V Total permissible input current (to chip) ∑Io 100 mA 2 Total permissible output current (from chip) –∑Io 50 mA 3 Maximum input current (to chip) Io 4 mA 4, 5 30 mA 4, 6 4 mA 7, 8 20 mA 7, 9 Maximum output current (from chip) –I o Notes 1 Operating temperature Topr –20 to +75 °C 10 Storage temperature Tstg –55 to +125 °C 11 Notes: 1. Applies to D 13 (VPP) of the HD407A4669. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to ground. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from each I/O pin to ground. 5. Applies to D 0–D 3, R0–R4 and R6–RA. 6. Applies to D 4, D5 and D 9–D 11 7. The maximum output current is the maximum current flowing out from V CC to each I/O pin. 8. Applies to D 4, D5, D9–D 11, R0–R4 and R6–RA. 9. Applies to D 0–D 3. 10. The operating temperature indicates the temperature range in which power can be supplied to the LSI (voltage V CC shown in the electrical characteristics tables can be applied). 11. In the case of chips, the storage specification differs from that of the package products. Please consult your Hitachi sales representative for details. Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 126 HD404669 Series Electrical Characteristics DC Characteristics (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404669: VCC = 1.8 to 5.5 V, GND = 0 V, T a = +75°C; HD407A4669: V CC = 2.2 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Input high voltage VIH RESET, SCK1, SI 1, INT0, INT1, INT2, INT3, INT4, STOPC, EVND OSC1 0.9VCC — VCC + 0.3 V — VCC – 0.3 — VCC + 0.3 V RESET, SCK1, SI 1, INT0, INT1, INT2, INT3, INT4, STOPC, EVND OSC1 –0.3 — 0.10VCC V External clock operation — –0.3 — 0.3 V VCC – 0.5 — — V External clock operation –I OH = 0.3 mA — — 0.4 V IOL = 0.4 mA — — 1.0 µA Vin = 0 V to V CC 1 — 2.5 5.0 mA VCC = 5.0 V, fOSC = 4 MHz 2 VCC = 3.0 V, fOSC = 800 kHz HD40A4668, HD40A46612, HD40A4669, HD407A4669: VCC = 5 V, fOSC = 8 MHz 2 Input low voltage VIL Output high voltage Output low voltage I/O leakage current VOH Active mode current dissipation (digital input mode) ICC1 SCK 1, SO1, TOC, TOD SCK 1, SO1, TOC, TOD RESET, SCK1, SI 1, INT0, INT1, INT2, INT3, INT4, STOPC, EVND, OSC1, SO 1, TOC, TOD VCC ICC2 VCC — 0.3 1.0 mA ICC3 VCC — 5.0 9.0 mA VOL II L Notes 2 127 HD404669 Series Item Active mode current dissipation (analog compare mode) Standby mode current dissipation Subactive mode current dissipation Watch mode current dissipation Stop mode current dissipation Stop mode retention voltage Comparator input reference voltage range Symbol ICMP1 Pin(s) VCC Min — Typ 6.5 Max 9.0 Unit mA Test Condition VCC = 5V, fOSC = 4MHz Notes 3 ICMP2 VCC — 2.8 3.5 mA 3 ICMP3 VCC — 9.0 13.0 mA ISBY1 VCC — 1.0 2.0 mA VCC = 3V, fOSC = 800kHz HD40A4668, HD40A46612, HD40A4669, HD407A4669: VCC = 5V, fOSC = 8MHz VCC = 5V, fOSC = 4MHz ISBY2 VCC — 0.1 0.3 mA 4 ISBY3 VCC — 2.0 4.0 mA ISUB VCC — 18 35 µA VCC = 3V, fOSC = 800kHz HD40A4668, HD40A46612, HD40A4669, HD407A4669: VCC = 5V, fOSC = 8MHz VCC = 3 V, 32 kHz oscillator used IWTC VCC — 4 7.5 µA VCC = 3 V, 32 kHz oscillator used 5 ISTOP VCC — 0.5 5 µA VCC = 3 V, no 32 kHz oscillator 5 VSTOP VCC 1.5 — — V No 32 kHz oscillator 6 VCref VCref 0 — VCC—1.2 V 3 4 4 5 Notes: 1. Output buffer current is excluded. 2. Power supply current when the MCU is in the reset state and there are no I/O currents. Test conditions: MCU: Reset Pins: RESET at V CC (VCC – 0.3 V to VCC) TEST at V CC (VCC – 0.3 V to VCC) 3. Power supply current when pins RD0 and RD1 are in analog input mode and there are no I/O currents. Test conditions: MCU: DTMF not operating Pins: • RD 0/COMP0: At GND (0 V to 0.3 V) • RD 1/COMP1: At GND (0 V to 0.3 V) • RE0/VCref: At GND (0 V to 0.3 V) 128 HD404669 Series 4. Power supply current when the on-chip timers are operating and there are no I/O currents. Test conditions: MCU: I/O reset Serial interface stopped DTMF not operating Standby mode Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (VCC – 0.3 V to VCC) 5. These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (VCC – 0.3 V to VCC) D13 at V CC (VCC – 0.3 V to VCC) for the HD407A4669 6. The required voltage for RAM data retention. 129 HD404669 Series I/O Characteristics for Standard Pins (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = +75°C; HD407A4669: VCC = 2.2 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Input high voltage VIH D12 , D13 , R0 to R4, R6 to RA, RD, RE0 0.7VCC — VCC + 0.3 V — Input low voltage VIL D12 , D13 , R0 to R4, R6 to RA, RD, RE0 –0.3 — 0.3VCC V — Output high voltage VOH R0 to R4, R6 to RA VCC – 0.5 — — V –I OH = 0.3 mA Output low voltage VOL R0 to R4, R6 to RA — — 0.4 V IOL = 0.4 mA I/O leakage current II L D12 , R0 to R4, R6 to RA, RD, RE0 — — 1 µA Vin = 0 V to V CC 1 D13 — — 1 µA HD404668, HD4046612, HD404669, HCD404669, HD40A4668, HD40A46612, HD40A4669: Vin = 0V to V CC 1 — — 1 µA HD407A4669: Vin = VCC – 0.3V to VCC 1 — — 20 µA HD407A4669: Vin = 0V to 0.3V 1 Pull-up MOS current –I PU R0 to R4, R6 to RA 10 50 150 µA VCC = 3.0 V, Vin = 0 V Input high voltage VIHA COMP0, COMP1 VC ref +0.1 — — V Analog compare mode Input low voltage VILA COMP0, COMP1 — — VC ref – 0.1 V Analog compare mode Note: 1. Output buffer current is excluded. 130 Notes HD404669 Series I/O Characteristics for High-Current (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: VC C = 1.8 to 5.5 V, GND = 0 V, T a = –20°C to +75°C; HCD404669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = +75°C; HD407A4669: VCC = 2.2 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Input high voltage VIH D0 to D5, D9 to D11 0.7VCC — VCC + 0.3 V — Input low voltage VIL D0 to D5, D9 to D11 –0.3 — 0.3VCC V — Output high voltage VOH D0 to D5, D9 to D11 VCC – 0.5 — — V –I OH = 0.3 mA D0 to D3 VCC – 2.0 — — V –I OH = 10 mA Notes VCC = 4.5V to 5.5V Output low voltage VOL D0 to D5, D9 to D11 — — 0.4 V IOL = 0.4 mA D4, D5, D9 to D11 — — 2.0 V IOL = 15 mA, VCC = 4.5 V to 5.5 V I/O leakage current II L D0 to D5, D9 to D11 — — 1 µA Vin = 0 V to V CC Pull-up MOS current –I PU D4, D5, D9 to D11 10 50 150 µA VCC = 3 V, Vin = 0 V Pull-down MOS current IPD D0 to D3 10 50 150 µA VCC = 3 V, Vin = 3 V 1 Note: 1. Output buffer current is excluded. 131 HD404669 Series DTMF Characteristics (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = +75°C; HD407A4669: VCC = 2.2 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Condition Notes Tone output voltage (1) VOR TONER 500 660 — mVr ms VTref – GND = 2.0 V, R L = 100 kΩ, VCC = 2.2 to 5.0V 1 Tone output voltage (2) VOC TONEC 520 690 — mVr ms VTref – GND = 2.0 V, R L = 100 kΩ, VCC = 2.2 to 5.0V 1 Tone output distortion %DIS — — 3 7 % Short circuit between TONER and TONEC, R L = 100 kΩ 2 Tone output ratio dBCR — — 2.5 — dB Short circuit between TONER and TONEC, R L = 100 kΩ 2 Notes: These characteristics are guaranteed with an operating frequency, fOSC, of 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz, or 8 MHz. 1. See figure 89. 2. See figure 90. 132 HD404669 Series AC Characteristics (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = +75°C; HD407A4669: VCC = 2.2 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Clock oscillation frequency fOSC OSC1, OSC2 — 400 — kHz 1 — 800 — kHz 1 — 2 — MHz 1 — 3.58 — MHz 1 — 4 — MHz — 7.16 — MHz — 8 — MHz X1, X2 — 32.768 — kHz — — 8 — — 4 — Instruction cycle time tcyc tsubcyc — Test Condition Notes 1 HD40A4668, HD40A46612, HD40A4669, HD407A4669: VCC = 4.0V to 5.5V 1 µs fOSC = 4 MHz, division by 32 2 — µs fOSC = 4 MHz, division by 16 2 2 — µs fOSC = 4 MHz, division by 8 2 — 1 — µs fOSC = 4 MHz, division by 4 2 — 244.14 — µs 32 kHz oscillator used, division by 8 3 — 122.07 — µs 32 kHz oscillator used, division by 4 3 Oscillation stabilization time (ceramic oscillator) tRC OSC1, OSC2 — — 7.5 ms 4, 5 Oscillation stabilization time (crystal oscillator) tRC OSC1, OSC2 — — 30 ms 4, 5, 12 X1, X2 — — 2 s Ta = –10°C to +60°C 4 OSC1 1100 — — ns fOSC = 400 kHz 6 550 — — ns fOSC = 800 kHz 215 — — ns fOSC = 2 MHz 115 — — ns fOSC = 3.58 MHz 105 — — ns fOSC = 4 MHz 57.5 — — ns fOSC = 7.16 MHz 52.5 — — ns fOSC = 8 MHz External clock high width tCPH 6, 11 133 HD404669 Series Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes External clock low width tCPL OSC1 1100 — — ns fOSC = 400 kHz 6 550 — — ns fOSC = 800 kHz 215 — — ns fOSC = 2 MHz 115 — — ns fOSC = 3.58 MHz 105 — — ns fOSC = 4 MHz 57.5 — — ns fOSC = 7.16 MHz 52.5 — — ns fOSC = 8 MHz — — 150 ns fOSC = 400 kHz — — 75 ns fOSC = 800 kHz — — 35 ns fOSC = 2 MHz — — 25 ns fOSC = 3.58 MHz — — 20 ns fOSC = 4 MHz — — 12.5 ns fOSC = 7.16 MHz — — 10 ns fOSC = 8 MHz — — 150 ns fOSC = 400 kHz — — 75 ns fOSC = 800 kHz — — 35 ns fOSC = 2 MHz — — 25 ns fOSC = 3.58 MHz — — 20 ns fOSC = 4 MHz — — 12.5 ns fOSC = 7.16 MHz — — 10 ns fOSC = 8 MHz — tcyc / — 7 — 7 External clock rise time External clock fall time tCPr tCPf INT0–INT4, EVND high widths tI H INT0–INT4, EVND low widths tI L RESET high width STOPC low width OSC1 OSC1 6, 11 6 6, 11 6 6, 11 INT0 to INT4, EVND 2 INT0 to INT4, EVND 2 tRSTH RESET 2 — — tcyc — 8 tSTPL STOPC 1 — — tRC — 9 RESET fall time tRSTf RESET — — 20 ms — 8 STOPC rise time tSTPr STOPC — — 20 ms — 9 Input capacitance Cin All pins except D 13 — — 15 pF f = 1 MHz Vin = 0 V, D13 — — 15 pF HD40A4668, HD40A46612, HD40A4669, HCD404669, HD404668, HD4046612, HD404669: f = 1MHz, Vin = 0V — — 40 pF HD407A4669: — tsubcyc — — tcyc / tsubcyc f = 1MHz, Vin = 0V 134 HD404669 Series Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Analog comparator stabilization time tCSTB COMP0 to COMP1 — — 2 tcyc VCC = 2.2 V to 5.5V 10 — — 10 tcyc VCC = 1.8 V to less than 2.2V Notes: 1. Set bits 0 and 1 (SSR10, SSR11) of system clock select register 1 (SSR1: $029) and bits 2 and 3 (SSR22, SSR23) of system clock select register 2 (SSR2: $02A) according to the system clock frequency used. 2. Set bits 0 and 1 (SSR20, SSR21) of system clock select register 2 (SSR2: $02A) according to the system clock frequency division ratio used. 3. Set bit 2 (SSR12) of system clock select register 1 (SSR1: $029) according to the subsystem clock frequency division ratio used. 4. The oscillation stabilization time is defined as follows: (1) The time required for the oscillation to settle after VCC has reached the minimum specification value at power-on. (2) The time required for the oscillation to settle after RESET input has gone high when stop mode is cleared. (3) The time required for the oscillation to settle after STOPC input has gone low when stop mode is cleared. To ensure enough time for the oscillation to settle at power-on or when stop mode is cleared, input the RESET or STOPC signal for at least time tRC. The oscillation stabilization time will depend on the circuit constants and stray capacitance. The oscillator should be determined in consultation with the oscillator manufacturer. 5. Set bits 0 and 1 (MIS0, MIS1) in the miscellaneous register (MIS: $00C) according to the oscillation stabilization time of the system oscillator. 6. See figure 91. 7. See figure 92. Unit tcyc applies when the MCU is in standby mode or active mode. Unit tsubcyc applies when the MCU is in watch mode or subactive mode. 8. See figure 93. 9. See figure 94. 10. This is the time required for the analog comparator to settle, ensuring that the correct data is read, after pins RD 0 /COMP0 and RD1/COMP1 are set to analog input mode. 11. Applies to the HD40A4668, HD40A46612, HD40A4669, and HD407A4669. The test condition is VCC = 4.0 to 5.5 V. 12. Applies to the HD404668, HD4046612, HD404669, HCD404669, HD40A4668, HD40A46612, and HD40A4669. The test condition is VCC = 2.0 to 5.5 V. 135 HD404669 Series Serial Interface Timing Characteristics (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: VCC = 1.8 to 5.5 V, GND = 0 V, T a = –20°C to +75°C; HCD404669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = +75°C; HD407A4669: VCC = 2.2 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) During Transmit Clock Output Item Symbol Pin Min Typ Max Unit Test Condition Notes Transmit clock cycle time tScyc SCK1 1.0 — — tcyc Load shown in figure 96 1 Transmit clock high width tSCKH SCK1 0.4 — — tScyc Load shown in figure 96 1 Transmit clock low width tSCKL SCK1 0.4 — — tScyc Load shown in figure 96 1 Transmit clock rise time tSCKr SCK1 — — 100 ns Load shown in figure 96 1 Transmit clock fall time tSCKf SCK1 — — 100 ns Load shown in figure 96 1 Serial output data delay time tDSO SO 1 — — 300 ns Load shown in figure 96 1 Serial input data setup time tSSI SI 1 200 — — ns — 1 Serial input data hold time tHSI SI 1 200 — — ns — 1 Note: 1. Refer to figure 95. During Transmit Clock Input Item Symbol Pin Min Typ Max Unit Test Condition Notes Transmit clock cycle time tScyc SCK1 1.0 — — tcyc — 1 Transmit clock high width tSCKH SCK1 0.4 — — — 1 Transmit clock low width tSCKL SCK1 0.4 — — tScyc — 1 Transmit clock rise time tSCKr SCK1 — — 100 ns — 1 Transmit clock fall time tSCKf SCK1 — — 100 ns — 1 Serial output data delay time tDSO SO 1 — — 300 ns Load shown in figure 96 1 Serial input data setup time tSSI SI 1 200 — — ns — 1 Serial input data hold time tHSI SI 200 — — ns — 1 Note: 1. Refer to figure 95. 136 1 tScyc HD404669 Series RL = 100 kΩ TONEC GND TONER RL = 100 kΩ Figure 89 Tone Output Load Circuit TONEC RL = 100 kΩ TONER GND Figure 90 Distortion and dBCR Load Circuit OSC1 1/fCP tCPL VCC – 0.3 V 0.3 V tCPH tCPr tCPf Figure 91 External Clock Timing INT0 to INT4, EVND 0.9 VCC tIH tIL 0.1 VCC Figure 92 Interrupt Timing 137 HD404669 Series RESET 0.9 VCC 0.1 VCC tRSTH tRSTf Figure 93 Reset Timing STOPC 0.9 VCC tSTPL 0.1 VCC tSTPr Figure 94 STOPC Timing tScyc tSCKf tSCKr tSCKL VCC – 0.5 V (0.9 VCC) * SCK1 SO1 0.4 V (0.1 VCC) * tSCKH tDSO VCC – 0.5 V 0.4 V tSSI SI1 tHSI 0.9 VCC 0.1VCC Note: * VCC – 0.5 V and 0.4 V are the threshold voltages during serial clock output. 0.9 VCC and 0.1 VCC are the threshold voltages during serial clock input. Figure 95 Serial Interface Timing 138 HD404669 Series VCC RL = 2.6 kΩ Test point C = 30 pF R = 12 kΩ 1S2074 H or equivalent Figure 96 Timing Load Circuit 139 HD404669 Series Notes on ROM Out Please note the following when ordering HD404668, HD4046612, HD40A4668, or HD40A46612 ROM. On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version (HD404669, HD40A4669). A 16-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 16-kword version. This limitation applies when using an EPROM or a data base. 8-kword ROM versions: HD404668, HD40A4668 Write all-1 data to addresses $2000 to $3FFF. $0000 12-kword ROM versions: HD4046612, HD40A46612 Write all-1 data to addresses $3000 to $3FFF. $0000 Vector addresses $000F $0010 $003F $0040 Zero page subroutine area (64 words) Vector addresses $000F $0010 $003F $0040 Program and pattern area (8,192 words) Zero page subroutine area (64 words) Program and pattern area (12,288 words) $1FFF $2000 $2FFF $3000 Not used Not used $3FFF Note: Write all-1 data in shaded areas. 140 $3FFF HD404669 Series HD404668/HD4046612/HD404669/HCD404669/HD40A4668/HD40A46612/HD40A4669 Option List Please check off the appropriate applications and enter the necessary information. Date of order / / Customer Department Name ROM code name LSI number (Hitachi entry) 1. ROM Size Standard operation version: HD404668 8-kword High-speed operation version: HD40A4668 Standard operation version: HD4046612 12-kword High-speed operation version: HD40A46612 Standard operation version: HD404669 16-kword High-speed operation version: HD40A4669 Chip version: HCD404669 2. Optional Functions * With 32-kHz CPU operation, with time-base for clock * Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base for clock Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. ROM Code Data Type Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMs 4. System Oscillator (OSC 1 and OSC2) Ceramic oscillator f= MHz Crystal oscillator f= MHz External clock f= MHz 5. Stop Mode Used Not used 6. Package FP-64A Chip Note: The specifications of shipped chips differ from of the package product. Please contact our sales staff for details. 141 HD404669 Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 142