HD404374/HD404384/ HD404389/HD404082 Series Low-Voltage AS Microcomputers with On-Chip A/D Converter ADE-202-086A (O) Rev. 2.0 Jun. 1999 Description The HD404374, HD404384, and HD404389 Series comprises low-voltage, 4-bit single-chip microcomputers equipped with four 10-bit A/D converter channels, a serial interface, and large-current I/O pins. These devices are suitable for use in applications requiring high resolution A/D converter control, such as battery chargers. The HD404082 series offers less advanced features than the HD404384 series. It is a 4-bit microcomputer that supports low-voltage operation for backward software compatibility. HD404374 Series microcomputers have a 32.768 kHz sub-resonator for realtime clock use, providing a time counting facility, and a variety of low-power modes to reduce current drain. The HD407A4374, HD407A4384, HD407A4389, HD407C4374, HD407C4384, and HD407C4389 are a ZTAT TM microcomputers with on-chip PROM that drastically shortens development time and ensures a smooth transition from debugging to mass production. (The PROM programming specifications are the same as for the 27256 type.) ZTAT TM: Zero Turn-Around Time. ZTAT TM is a trademark of Hitachi, Ltd. Features • 20 I/O pins Large-current I/O pins (source: 10 mA max.):4 Large-current I/O pins (sink: 15 mA max.):4 Analog input multiplexed pins: 4 (HD404374, HD404384, and HD404389 Series) • 8-bit timer: 1 channel 16-bit timer: 1 channel (Can also be used as two 8-bit timer channels) • Two timer outputs (including PWM output) • Event counter inputs (edge-programmable) • Clock-synchronous 8-bit serial interface • A/D converter HD404374/HD404384/HD404389/HD404082 Series 4 channels × 10-bits (HD404374 and HD404384 Series) 6 channels × 10-bits (HD404389 Series) None (HD404082 Series) • On-chip oscillators HD404374 Series • Main clock (ceramic resonator, crystal resonator, CR oscillation* or external clock operation possible) • Sub-clock (32.768 kHz crystal resonator) HD404384, HD404389, and HD404082 Series • Main clock (ceramic resonator, crystal resonator, CR oscillation* or external clock operation possible) Note: CR oscillation in an optional function. • Interrupts External: 2 (including one edge-programmable) Internal : 5 (HD404374/HD404384/HD404389 Series) : 4 (HD404082 Series) • Subroutine stack up to 16 levels, including interrupts • Low-power dissipation modes HD404374 Series: 4 HD404384, HD404389 and HD404082 Series: 2 • Module standby (timers, serial interface, A/D converter) • System clock division software switching (1/4 or 1/32) • Inputs for return from stop mode (wakeup): 1 • Instruction execution time Min. 0.89 µs (fOSC = 4.5 MHz, division by 1/4) Min. 0.47 µs (fOSC = 8.5 MHz, division by 1/4) • Operation voltage 1.8 V to 5.5 V 2.0 V to 5.5 V (ZTAT TM) Cautions about operation! • Electrical properties presented on the data sheet for the mask ROM and ZTATTM versions will surely and sufficiently satisfy the standard values. However, real capabilities, operation margin, noise margin, and other properties may vary depending on differences of manufacturing processes, internal wiring patterns, etc. Therefore, it is requested for users to carry out an evaluation test for each product on an actual system under the same conditions to see its operation. • After power supply has been connected, the values for the memory register, data and stack areas will be undefined. Initialize prior to use. 2 HD404374/HD404384/HD404389/HD404082 Series Ordering Information HD404374 Series Type Product Name Model Name Mask ROM HD404372 HD40A4372 HD40C4372 HD404374 Package 2,048 512 30-pin plastic SSOP(FP-30D) HD404372H 48-pin plastic LQFP(FP-48B) *1 HD40A4372FT 30-pin plastic SSOP(FP-30D) HD40A4372H 48-pin plastic LQFP(FP-48B) *1 HD40C4372FT 30-pin plastic SSOP(FP-30D) HD40C4372H 48-pin plastic LQFP(FP-48B) *1 HD404374FT 4,096 30-pin plastic SSOP(FP-30D) 48-pin plastic LQFP(FP-48B) *1 HD40A4374FT 30-pin plastic SSOP(FP-30D) HD40A4374H 48-pin plastic LQFP(FP-48B) *1 HD40C4374FT 30-pin plastic SSOP(FP-30D) HD40C4374H 48-pin plastic LQFP(FP-48B) *1 HD407A4374 HD407A4374FT 4,096 30-pin plastic SSOP (FP-30D) HD407C4374 HD407C4374FT 30-pin plastic SSOP(FP-30D) HD40C4374 TM RAM (Digits) HD404374H HD40A4374 ZTAT HD404372FT ROM (Words) 3 HD404374/HD404384/HD404389/HD404082 Series HD404384 Series Type Product Name Model Name Mask ROM HD404382 HD40A4382 HD40C4382 HD404384 HD40A4384 HD40C4384 TM ZTAT HD407A4384 HD407C4384 4 HD404382FT ROM (Words) RAM (Digits) Package 2,048 512 30-pin plastic SSOP (FP-30D) HD404382S 28-pin plastic DILP (DP-28S) HD404382H 48-pin plastic LQFP (FP-48B)*1 HD40A4382FT 30-pin plastic SSOP (FP-30D) HD40A4382S 28-pin plastic DILP (DP-28S) HD40A4382H 48-pin plastic LQFP (FP-48B)*1 HD40C4382FT 30-pin plastic SSOP (FP-30D) HD40C4382S 28-pin plastic DILP (DP-28S) HD40C4382H 48-pin plastic LQFP (FP-48B)*1 HD404384FT 4,096 30-pin plastic SSOP (FP-30D) HD404384S 28-pin plastic DILP (DP-28S) HD404384H 48-pin plastic LQFP (FP-48B)*1 HD40A4384FT 30-pin plastic SSOP (FP-30D) HD40A4384S 28-pin plastic DILP (DP-28S) HD40A4384H 48-pin plastic LQFP (FP-48B)*1 HD40C4384FT 30-pin plastic SSOP (FP-30D) HD40C4384S 28-pin plastic DILP (DP-28S) HD40C4384H 48-pin plastic LQFP (FP-48B)*1 HD407A4384FT 4,096 30-pin plastic SSOP (FP-30D) HD407A4384S 28-pin plastic DILP (DP-28S) HD407C4384FT 30-pin plastic SSOP (FP-30D) HD407C4384S 28-pin plastic DILP (DP-28S) HD404374/HD404384/HD404389/HD404082 Series HD404389 Series Type Product Name Model Name Mask ROM HD404388 TM ZTAT HD404388FT ROM (Words) RAM (Digits) Package 8,192 512 30-pin plastic SSOP (FP-30D) HD40A4388 HD40A4388FT HD40C4388 HD40C4388FT HD404389 HD404389FT HD40A4389 HD40A4389FT HD40C4389 HD40C4389FT HD407A4389 HD407A4389FT 16,384 HD407C4389 HD407C4389FT 16,384 5 HD404374/HD404384/HD404389/HD404082 Series HD404082 Series Type Product Name Model Name Mask ROM HD404081 HD40A4081 HD40C4081 HD404082 Package 1,024 128 30-pin plastic SSOP (FP-30D) HD404081S 28-pin plastic DILP (DP-28S) HD404081H 48-pin plastic LQFP (FP-48B)*2 HD40A4081FT 30-pin plastic SSOP (FP-30D) HD40A4081S 28-pin plastic DILP (DP-28S) HD40A4081H 48-pin plastic LQFP (FP-48B)*2 HD40C4081FT 30-pin plastic SSOP (FP-30D) HD40C4081S 28-pin plastic DILP (DP-28S) HD40C4081H 48-pin plastic LQFP (FP-48B)*2 HD404082FT 2,048 30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S) HD404082H 48-pin plastic LQFP (FP-48B)*2 HCD404082 HCD404082 chip HD40A4082 HD40A4082FT 30-pin plastic SSOP (FP-30D) HD40A4082S 28-pin plastic DILP (DP-28S) HD40A4082H 48-pin plastic LQFP (FP-48B)*2 HD40C4082FT 30-pin plastic SSOP (FP-30D) HD40C4082S 28-pin plastic DILP (DP-28S) HD40C4082H 48-pin plastic LQFP (FP-48B)*2 HCD40C4082 chip HCD40C4082 ZTAT RAM (Digits) HD404082S HD40C4082 TM HD404081FT ROM (Words) TM Uses HD404384 series ZTAT . Notes: 1. The FP-48B is subject to the following limitations: (1) It is available in a mask ROM version only. For debugging, etc., the ZTATTM version of a different package will need to be used. (2) The WS version will become available at the beginning of mass production. 2. Currently in planning stage. 6 HD404374/HD404384/HD404389/HD404082 Series List of Functions Product Name HD404372, HD40A4372, HD40C4372 ROM(words) 2,048 RAM (digit) 512 I/O 20 (max) Large-current I/O pins HD404374, HD40A4374, HD40C4374, HD407A4374, HD407C4374 4,096 ZTAT PROM HD404382, HD40A4382, HD40C4382 2,048 HD404384, HD40A4384, HD40C4384, HD407A4384, HD407C4384 4,096 ZTAT PROM HD404388, HD40A4388, HD40C4388 8,192 4 (source, 10 mA max), 4 (sink, 15 mA max) Analog input 4 multiplexed pins Timer/ counter 3 Timer output 2 (PWM output possible) Event input 1 (edge selection possible) Serial interface 1 (8-bit synchronous) A/D converter 10 bits × 4 channels Interrupt External 2 sources Internal 5 Low-power modes 4 Stop mode Available Watch mode Available Standby mode Available Subactive mode Available 10 bits × 6 channels 2 — — Module standby Available System clock division software switching Available Main oscillator Ceramic oscillation Available Crystal oscillation Available CR oscillation Available (HD40C4372, HD40C4374, HD407C4374, HD40C4382, HD40C4384, HD407C4384, HD40C4388, HD40C4389, HD407C4389, HD40C4081, HD40C4082, HCD40C4082) Crystal oscillation Available (32.768kHz) Sub-oscillator — 7 HD404374/HD404384/HD404389/HD404082 Series HD404372, HD40A4372, HD40C4372 Product Name Minimum instruction execution time HD404374, HD40A4374, HD40C4374, HD407A4374, HD407C4374 HD404382, HD40A4382, HD40C4382 HD404384, HD40A4384, HD40C4384, HD404388, HD407A4384, HD40A4388, HD407C4384 HD40C4388 0.47 ms (f OSC = 8.5 MHz) : HD40A4372, HD40A4374, HD407A4374, HD40A4382, HD40A4384, HD407A4384, HD40A4388, HD40A4389, HD407A4389, HD40A4081, HD40A4082 0.89 ms (f OSC = 4.5 MHz) : HD404372, HD404374, HD404382, HD404384, HD404388, HD404389, HD404081, HD404082, HCD404082 1.14 ms (f OSC = 3.5 MHz) : HD40C4372, HD40C4374, HD407C4374, HD40C4382, HD40C4384, HD407C4384, HD40C4388, HD40C4389, HD407C4389, HD40C4081, HD40C4082, HCD40C4082 Operating voltage (V) Package 1.8 to 5.5 V : Mask ROM, 2.0 to 5.5 V : ZTATTM FP-30D Available DP-28S — FP-48B Available Chip — Guaranteed operation temperature(°C) –20 to +75: Mask ROM –40 to +85: ZTAT TM 8 Available — — HD404374/HD404384/HD404389/HD404082 Series HD404389, HD40A4389, HD40C4389, HD407A4389, HD407C4389 Product Nme HD404081, HD40A4081, HD40C4081 HD404082, HD40A4082, HD40C4082 2,048 ROM(words) 16,384 ZTAT PROM 1,024 RAM (digit) 512 128 I/O 20 (max) Large-current I/O pins 4 (source, 10 mA max), 4 (sink, 15 mA max) Analog input 4 multiplexed pins Timer/ counter — 3 Timer output 2 (PWM output possible) Event input 1 (edge selection possible) Serial interface 1 (8-bit synchronous) A/D converter 10 bits × 6 channels — Interrupt External 2 sources Internal 5 Low-power modes HCD404082, HCD40C4082 4 4 Stop mode Available Watch mode Available Standby mode Available Subactive mode Available Module standby Available System clock division software switching Available Main oscillator Ceramic oscillation Available Crystal oscillation Available CR oscillation Available (HD40C4372, HD40C4374, HD407C4374, HD40C4382, HD40C4384, HD407C4384, HD40C4388, HD40C4389, HD407C4389, HD40C4081, HD40C4082, HCD40C4082) Crystal oscillation Available (32.768kHz) Sub-oscillator 9 HD404374/HD404384/HD404389/HD404082 Series HD404389, HD40A4389, HD40C4389, HD407A4389, HD407C4389 Product Nme Minimum instruction execution time HD404081, HD40A4081, HD40C4081 HD404082, HD40A4082, HD40C4082 HCD40482, HCD40C4082 0.47 µs (fOSC = 8.5 MHz) : HD40A4372, HD40A4374, HD407A4374, HD40A4382, HD40A4384, HD407A4384, HD40A4388, HD40A4389, HD407A4389, HD40A4081, HD40A4082 0.89 µs (fOSC = 4.5 MHz) : HD404372, HD404374, HD404382, HD404384, HD404388, HD404389, HD404081, HD404082, HCD404082 1.14 µs (fOSC = 3.5 MHz) : HD40C4372, HD40C4374, HD407C4374, HD40C4382, HD40C4384, HD407C4384, HD40C4388, HD40C4389, HD407C4389, HD40C4081, HD40C4082, HCD40C4082 1.8 to 5.5 V : Mask ROM, 2.0 to 5.5 V : ZTAT TM Operating voltage (V) Package FP-30D Available DP-28S — Available FP-48B Available In planning stage Chip — Available Guaranteed operation temperature(°C) –20 to +75: Mask ROM –40 to +85: ZTAT TM +75 10 HD404374/HD404384/HD404389/HD404082 Series Pin Arrangement HD404374 Series GND Vcc AVcc R70/AN0 R71/AN1 R72/AN2 R73/AN3 AVss OSC1 OCS2 TEST X2 X1 RESET R00/WU0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R70/AN0 R71/AN1 R72/AN2 R73/AN3 NC AVSS OSC1 NC OSC2 NC TEST X2 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 FP-48B 31 6 (Top View) 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 FP-30D D9 D8 D7 D6 N-MOS large current pins D5 D4 D3 D2 P-MOS large current pins D1 D0/INT0 R22/SI/SO R21/SCK R20/TOC R13/TOB R10/EVNB AVCC VCC NC GND NC D9 NC NC D8 D7 NC D6 (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 N-MOS large current pins X1 NC RESET NC R00/WU0 NC R10/EVNB NC R13/TOB NC R20/TOC R21/SCK D5 D4 NC D3 NC D2 NC P-MOS large current pins D1 NC D0/INT0 NC R22/SI/SO 11 HD404374/HD404384/HD404389/HD404082 Series HD404384 Series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND Vcc AVcc R70/AN0 R71/AN1 R72/AN2 R73/AN3 AVss OSC1 OCS2 TEST RESET R00/WU0 R10/EVNB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FP-30D (Top View) DP-28S (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 D9 D8 D7 D6 N-MOS large current pins D5 D4 D3 D2 P-MOS large current pins D1 D0/INT0 R22/SI/SO R21/SCK R20/TOC R13/TOB R10/EVNB 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D9 D8 D7 D6 N-MOS large current pins D5 D4 D3 D2 P-MOS large current pins D1 D0/INT0 R22/SI/SO R21/SCK R20/TOC R13/TOB AVCC VCC NC GND NC D9 NC NC D8 D7 NC D6 GND Vcc AVcc R70/AN0 R71/AN1 R72/AN2 R73/AN3 AVss OSC1 OCS2 TEST NC NC RESET R00/WU0 N-MOS large current pins NC NC RESET NC R00/WU0 NC R10/EVNB NC R13/TOB NC R20/TOC R21/SCK R70/AN0 R71/AN1 R72/AN2 R73/AN3 NC AVSS OSC1 NC OSC2 NC TEST NC 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 31 6 FP-48B 30 7 (Top View) 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 12 D5 D4 NC D3 NC D2 NC N-MOS large current pins D1 NC D0/INT0 NC R22/SI/SO HD404374/HD404384/HD404389/HD404082 Series HD404389 Series GND Vcc AVcc R70/AN0 R71/AN1 R72/AN2 R73/AN3 AN4 AN5 AVSS TEST OSC1 OSC2 RESET R00/WU0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FP-30D (Top View) D9 D8 D7 D6 N-MOS large current pins D5 D4 D3 D2 P-MOS large current pins D1 D0/INT0 R22/SI/SO R21/SCK R20/TOC R13/TOB R10/EVNB 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HD404082 Series GND VCC NC R70 R71 R72 R73 NC OSC1 OSC2 TEST NC NC RESET R00/WU0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND VCC NC R70 R71 R72 R73 NC OSC1 OSC2 TEST RESET R00/WU0 R10/EVNB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FP-30D (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0/INT0 R22/SI/SO R21/SCK R20/TOC R13/TOB R10/EVNB DP-28S (Top View) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0/INT0 R22/SI/SO R21/SCK R20/TOC R13/TOB N-MOS large current pins P-MOS large current pins N-MOS large current pins P-MOS large current pins 13 HD404374/HD404384/HD404389/HD404082 Series Pad Arrangement 23 24 25 26 1 2 3 HCD404082 22 5 6 21 Model Name 4 20 19 7 18 8 17 9 15 14 13 12 11 10 16 Model Name: HD404082 (HCD404082) 14 HD404374/HD404384/HD404389/HD404082 Series Pad Coordinates HCD404082 Y Chip size (X × Y): Coordinates: 4.63 × 4.77 (mm) Pad center Mold Home point position: Chip center Pad size (X × Y): 90 × 90 (µm) Chip thickness: X 280 (µm) Chip center (X=0,Y=0) Pad Coodinates Pad Coodinates No. Pad name X (µm) Y (µm) No. Pad name X (µm) Y (µm) 1 GND -458 1403 14 R2 0 572 -1403 2 VCC -826 1403 15 R2 1 982 -1403 3 R7 0 -1338 1403 16 R2 2 1338 -1403 4 R7 1 -1338 1006 17 D0 1338 -1020 5 R7 2 -1338 525 18 D1 1338 -637 6 R7 3 -1338 285 19 D2 1338 -254 7 OSC1 -1338 -550 20 D3 1338 129 8 OSC2 -1338 -954 21 D4 1338 768 9 TEST -1338 -1251 22 D5 1338 1170 10 RESETN -1197 -1403 23 D6 1153 1403 11 R0 0 -577 -1403 24 D7 751 1403 12 R1 0 -194 -1403 25 D8 349 1403 13 R1 3 189 -1403 26 D9 -53 1403 15 HD404374/HD404384/HD404389/HD404082 Series Pin Description HD404374/HD404384 Series Pin Number Item Symbol FP-30D DP-28S*2 DP-48B I/O Function Power supply VCC 2 2 47 — Apply the power supply voltage to this pin. GND 1 1 45 — Connect to ground. Test TEST 11 11 11 Input Not for use by the user application. Connect to GND potential. Reset RESET 14 12 15 Input Used to reset the MCU. 9 9 7 Input Internal oscillator input/output pins. Connect a ceramic resonator, crystal resonator, or external oscillator circuit. OSC2 10 10 9 Output When using CR oscillation, connect a resistor. X1 13*1 — 13*1 Input X2 12*1 — 12*1 Output Realtime clock oscillator input/output pins. Connect a 32.768 kHz crystal. If 32.768 kHz crystal oscillation is not used, fix the X1 pin to VCC and leave the X2 pin open. D0–D9 21–30 19–28 27, 29, 31, 33, 35– I/O 37, 39, 40, 43 I/O pins addressed bit by bit. D 0 to D3 are large-current source pins (max. 10 mA), and D4 to D9 are large-current sink pins (max. 15 mA). R00, R1 0, R1 3, 15–20, R20, R2 1, R2 2, 4–7 R70–R7 3 13–18, 4–7 17, 19, 21, 23–25, I/O 1–4 I/O pins, addressed in 4-bit units. Interrupt INT0 21 19 27 Input External interrupt input pin Wakeup WU0 15 13 17 Input Input pin used for transition from stop mode to active mode. Serial SCK 19 17 24 I/O Serial interface clock I/O pin interface SI 20 18 25 Input Serial interface receive data input pin SO 20 18 25 Output Serial interface transmit data output pin TOB,TOC 17, 18 15, 16 21, 23 Output Timer output pins EVNB 16 14 19 Input Event count input pin AV CC 3 3 48 — A/D converter power supply pin. Connect as close as possible to the VCC pin so as to be at the same potential as V CC. AV SS 8 8 6 — Ground pin for AVCC. Connect as close as possible to the GND pin so as to be at the same potential as GND. AN0–AN 3 4–7 4–7 1–4 Input A/D converter analog input pins NC 12*2, 13*2 — 5, 8, 10, 12*2, — 13*2, 14, 16, 18, 20, 22, 26, 28, 30, 32, 34, 38, 41, 42, 44, 46 Oscillation OSC1 Port Timer A/D converter Other Notes: *1 Applies to HD404374 Series. *2 Applies to HD404384 Series. 16 Connect to GND potential. HD404374/HD404384/HD404389/HD404082 Series HD404389 Series Pin Number Item Symbol FP-30D I/O Function Power supply VCC 2 — Apply the power supply voltage to this pin. GND 1 — Connect to ground. Test TEST 11 Input Not for use by the user application. Connect to GND potential. Reset RESET 14 Input Used to reset the MCU. Oscillation OSC1 12 Input Internal oscillator input/output pins. Connect a ceramic resonator, crystal resonator, or external oscillator circuit. OSC2 13 Output When using CR oscillation, connect a resistor. D0–D9 21–30 I/O I/O pins addressed bit by bit. D 0 to D3 are large-current source pins (max. 10 mA), and D 4 to D9 are large-current sink pins (max. 15 mA). R00, R1 0, R1 3, 15–20, R20, R2 1, R2 2, 4–7 R70–R7 3 I/O I/O pins, addressed in 4-bit units. Interrupt INT0 21 Input External interrupt input pin Wakeup WU0 15 Input Input pin used for transition from stop mode to active mode. Serial SCK 19 I/O Serial interface clock I/O pin interface SI 20 Input Serial interface receive data input pin SO 20 Output Serial interface transmit data output pin TOB,TOC 17, 18 Output Timer output pins EVNB 16 Input Event count input pin AV CC 3 — A/D converter power supply pin. Connect as close as possible to the V CC pin so as to be at the same potential as VCC. AV SS 10 — Ground pin for AVCC. Connect as close as possible to the GND pin so as to be at the same potential as GND. AN0–AN 5 4–9 Input A/D converter analog input pins Port Timer A/D converter 17 HD404374/HD404384/HD404389/HD404082 Series HD404082 Series Pin Number Item Symbol FP-30D DP-28S Chip I/O Function Power supply VCC 2 2 2 — Apply the power supply voltage to this pin. GND 1 1 1 — Connect to ground. Test TEST 11 11 9 Input Not for use by the user application. Connect to GND potential. Reset RESET 14 12 10 Input Used to reset the MCU. 9 9 7 Input Internal oscillator input/output pins. Connect a ceramic resonator, crystal resonator, or external oscillator circuit. OSC2 10 10 8 Output When using CR oscillation, connect a resistor. D0–D9 21–30 19–28 17–26 I/O I/O pins addressed bit by bit. D 0 to D3 are large-current source pins (max. 10 mA), and D4 to D9 are large-current sink pins (max. 15 mA). R00, R1 0, R1 3, 15–20, R20, R2 1, R2 2, 4–7 R70–R7 3 13–18, 4–7 11–16, 3–6 I/O I/O pins, addressed in 4-bit units. Interrupt INT0 21 19 17 Input External interrupt input pin Wakeup WU0 15 13 11 Input Input pin used for transition from stop mode to active mode. Serial SCK 19 17 15 I/O Serial interface clock I/O pin interface SI 20 18 16 Input Serial interface receive data input pin SO 20 18 16 Output Serial interface transmit data output pin TOB,TOC 17, 18 15, 16 13, 14 Output Timer output pins EVNB 16 14 12 Input Event count input pin NC 3, 8, 12, 3, 8 13 — — Connect to GND potential. Oscillation OSC1 Port Timer Other 18 HD404374/HD404384/HD404389/HD404082 Series Block Diagram D Port D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 R0 Port R00 R1 Port R10 R13 R2 Port R20 R21 R22 R7 Port RESET TEST OSC1 OSC2 X1 * X2 * Vcc GND HD404374/HD404384 Series R70 R71 R72 R73 HMCS400 CPU ROM INT0 WU0 RAM External interrupt control circuit 8-bit timer A TOB P-MOS large current buffer N-MOS large current buffer 8-bit timer B EVNB TOC 8-bit timer C SCK SI/SO 8-bit synchronous serial interface AVcc AN0 AN1 AN2 AN3 AVss A/D converter 10 bit × 4 channels : Data bus : Signal line Note : * Applies to HD404374 Series. 19 HD404374/HD404384/HD404389/HD404082 Series D Port D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 R0 Port R00 R1 Port R10 R13 R2 Port R20 R21 R22 R7 Port Vcc GND RESET TEST OSC1 OSC2 HD404389 Series R70 R71 R72 R73 HMCS400 CPU ROM INT0 WU0 RAM External interrupt control circuit 8-bit timer A TOB P-MOS large current buffer N-MOS large current buffer 8-bit timer B EVNB TOC 8-bit timer C SCK SI/SO 8-bit synchronous serial interface AVcc AN0 AN1 AN2 AN3 AN4 AN5 AVss A/D converter 10 bit × 6 channels : Data bus 20 : Signal line HD404374/HD404384/HD404389/HD404082 Series D Port D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 R0 Port R00 R1 Port R10 R13 R2 Port R20 R21 R22 R7 Port Vcc GND RESET TEST OSC1 OSC2 HD404082 Series R70 R71 R72 R73 HMCS400 CPU ROM INT0 WU0 RAM External interrupt control circuit 8-bit timer A TOB P-MOS large current buffer N-MOS large current buffer 8-bit timer B EVNB TOC 8-bit timer C SCK SI/SO 8-bit synchronous serial interface : Data bus : Signal line 21 HD404374/HD404384/HD404389/HD404082 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and is described below. Vector address area ($0000 to $000F): When an MCU reset or interrupt handling is performed, the program is executed from the vector address. A JMPL instruction should be used to branch to the start address of the reset routine or the interrupt routine. Zero page subroutine area ($0000 to $003F):A branch can be made to a subroutine in the area $0000 to $003F with the CAL instruction. Pattern area ($0000 to $0FFF): ROM data in the area $0000 to $0FFF can be referenced as pattern data with the P instruction. Program area ($0000 to $03FF (HD404081, HD40A4081, HD40C4081)), ($0000 to $07FF (HD404372, HD40A4372, HD40C4372, HD404382, HD40A4382, HD40C4382, HD404082, HCD404082, HD40A4082, HD40C4082, HCD40C4082)), ($0000 to $0FFF (HD404374, HD40A4374, HD40C4374, HD404384, HD40A4384, HD40C4384, HD407A4374, HD407C4374, HD407A4384, HD407C4384)), ($0000 to $1FFF (HD404388, HD40A4388, HD40C4388)), ($0000 to $3FFF (HD404389, HD40A4389, HD40C4389, HD407A4389, HD407C4389)). 22 HD404374/HD404384/HD404389/HD404082 Series ROM address $0000 $000F $0010 $003F $0040 $03FF $0400 ROM address $0000 Vector addresses (16 words) $0001 $0002 Zero page subroutine area (64 words) $0003 Pattern and program area (1,024 words) *1 $0005 Pattern and program area (2,048 words) *2 $0004 $0008 $0009 $07FF $0800 $000A $000B $000C Pattern and program area (4,096 words) *3 $000D $000E $000F JMPL instruction (Jump to reset routine) JMPL instruction (Jump to WU0 routine) JMPL instruction (Jump to INT0 routine) JMPL instruction (Jump to timer A routine) JMPL instruction (Jump to timer B routine) JMPL instruction (Jump to timer C routine) JMPL instruction (Jump to A/D or serial interface routine) $0FFF $1000 Pattern and program area (8,192 words) *4 $1FFF $2000 Notes: *1 HD404081, HD40A4081, HD40C4081 *2 HD40372, HD40A4372, HD40C4372, HD404382, HD40A4382, HD40C4382, HD404082, HCD404082, HD40A4082, HD40C4082, HCD40C4082 *3 HD404374, HD40A4374, HD40C4374, HD404384, HD40A4384, HD40C4384, HD407A4374, HD407C4374, HD407A4384, HD407C4384 *4 HD404388, HD40A4388, HD40C4388 *5 HD404389, HD40A4389, HD40C4389, HD407A4389, HD407C4389 Pattern and program area (16,384 words) *5 $3FFF Figure 1 ROM Memory Map RAM Memory Map The MCU has on-chip RAM comprising a memory register area, data area, and stack area. In addition to these areas, an interrupt control bit area, special register area, and register flag area are mapped onto RAM memory space as a RAM-mapped register area.The RAM memory map is shown in figure 2 and described below. After power supply has been connected, regardless of a reset, the values for the memory register, data and stack areas will be undefined. Make sure to initialize prior to use. 23 HD404374/HD404384/HD404389/HD404082 Series HD404374 Series HD404384 Series HD404389 Series HD404082 Series $000 $000 RAM–mapped register area $03F $040 $04F $050 RAM–mapped register area $03F $040 $04F $050 Memory register (MR) area (16 digits) Memory register (MR) area (16 digits) Not used Not used $08F $090 $08F $090 Data (48 digits) $0BF $0C0 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 Interrupt control bit area Speed Select Reg. Miscellaneous Reg. (SSR) (MIS) W W (PMR0) (PMR1) (PMR2) (PMR3) W W W W Not used Port Mode Reg.0 Port Mode Reg.1 Port Mode Reg.2 Port Mode Reg.3 Not used Module Standby Reg.1 (MSR1) Module Standby Reg.2 (MSR2) Timer Mode Reg.A (TMA) Timer Mode Reg.B1 (TMB1) Timer Mode Reg.B2 (TMB2) (TRBL/TWBL) Timer-B (TRBU/TWBU) Timer Mode Reg.C1 (TMC1) Timer Mode Reg.C2 (TMC2) (TRCL/TWCL) Timer-C (TRCU/TWCU) W W W W W R/W R/W W W R/W R/W *1 *1 Not used $01F $020 Register flag area Data (432 digits) Not used $23F $240 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C Serial Mode Reg.1 Serial Mode Reg.2 Serial Data Reg.Lower Serial Data Reg.Upper A/D Mode reg. A/D Data Reg.Lower A/D Data Reg.Middle A/D Data Reg.Upper (SMR1) W (SMR2) W (SRL) R/W (SRU) R/W (AMR) W (ADRL) R (ADRM) R (ADRU) R Not used $02F $030 $031 $032 $033 $034 $035 $036 $037 Not used $3BF $3C0 $3BF $3C0 Port D0~D3 DCR Port D4~D7 DCR Port D8~D9 DCR (DCD0) (DCD1) (DCD2) W W W (DCR0) (DCR1) (DCR2) W W W (DCR7) W Not used Port R0 DCR Port R1 DCR Port R2 DCR Not used Stack area Stack area (64 digits) (64 digits) $03A $03B $03C Port R7 DCR Not used $03F $3FF $3FF Notes: R W : Read : Write R/W : Read/Write *1 Two registers are mapped onto $012 $013 Timer Read Reg.B Lower Timer Read Reg.B Upper (TRBL) (TRBU) R R Timer Write Reg.B Lower Timer Write Reg.B Upper (TWBL) W (TWBU) W $016 $017 Timer Read Reg.C Lower Timer Read Reg.C Upper (TRCL) (TRCU) R R Timer Write Reg.C Lower Timer Write Reg.C Upper (TWCL) W (TWCU) W the same address ($012, $013, $016, $017). *2 Applies to HD404374, HD404384, and HD404389 Series. Figure 2 RAM Memory Map 24 *2 *2 *2 *2 HD404374/HD404384/HD404389/HD404082 Series RAM-mapped register area ($000 to $03F): • Interrupt control bit area ($000 to $003) This area consists of bits used for interrupt control. Its configuration is shown in figure 3. Individual bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). There are restrictions on access to certain bits. The individual bits and instruction restrictions are shown in figure 4. • Special register area ($004 to $01F, $024 to $03F) This area comprises mode registers and data registers for external interrupts, the serial interface, timers, A/D converter, etc., and I/O pin data control registers. Its configuration is shown in figures 2 and 5. These registers are of three kinds: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used on the other registers. • Register flag area ($020 to $023) This area consists of the DTON and WDON flags and interrupt control bits. Its configuration is shown in figure 3. Individual bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). There are restrictions on access to certain bits. The individual bits and instruction restrictions are shown in figure 4. Memory register (MR) area ($040 to $04F): In this data area, the 16 memory register digits (MR(0) to MR(15)) can also be accessed by the registerregister instructions LAMR and XMRA. The configuration of this area is shown in figure 6. Data area ($090 to $23F (HD404374, HD404384, HD404389 Series)) ($090 to $0BF (HD404082 Series)) Stack area ($3C0 to $3FF): This is the stack area used to save the contents of the program counter (PC), status flag (ST), and carry flag (CA) when a subroutine call (CAL or CALL instruction) or interrupt handling is performed. As four digits are used for one level, the area can be used as a subroutine stack with a maximum of 16 levels. The saved data and saved status information are shown in figure 6. The program counter is restored by the RTN and RTNI instructions. The status and carry flags are restored by the RTNI instruction, but are not affected by the RTN instruction. Any part of the area not used for saving can be used as a data area. 25 HD404374/HD404384/HD404389/HD404082 Series $000 Bit 3 IMWU (WU0 interrupt mask) Bit 2 IFWU (WU0 interrupt request flag) $001 Not used Not used IMTB (Timer B interrupt mask) IMAD *2 (A/D converter interrupt mask) Bit 1 RSP (Stack pointer reset) Bit 0 IE (Interrupt enable flag) IFTB (Timer B interrupt request flag) IFAD *2 (A/D converter interrupt request flag) IM0 (INT0 interrupt mask) IMTA (Timer A interrupt mask) IMTC (Timer C interrupt mask) IF0 (INT0 interrupt request flag) IFTA (Timer A interrupt request flag) IFTC (Timer C interrupt request flag) DTON *1 (DTON flag) ADSF *2 (A/D start flag) WDON (Watchdog on flag) LSON *1 (Low speed on flag) $021 GEF (Gear enable flag) Not used Not used Not used $022 Not used Not used Not used Not used $023 IMS (Serial interrupt mask) IFS (Serial interrupt request flag) Not used Not used RAM address $002 $003 $020 IF IM IE SP : Interrupt Request Flag : Interrupt Mask : Interrupt Enable Flag : Stack Pointer Notes: *1 Applies to HD404374 Series. *2 Applies to HD404374, HD404384, and HD404389 Series. Figure 3 Interrupt Control Bit and Register Flag Area Configuration 26 HD404374/HD404384/HD404389/HD404082 Series Bits in the interrupt control bit area and register flag area can be set and reset by the SEM or SEMD instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not affected by any other instructions. The following restrictions apply to individual bits. SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed GEF Allowed Allowed RSP Not executed Allowed Inhibited Inhibited Allowed Not executed Inhibited Allowed Inhibited Allowed Allowed Allowed Not executed Inhibited IE IM LSON *1 IF ICSF ICEF WDON ADSF *2 DTON *1 Not Used Not executed in active mode Used in subactive mode Not executed Notes : The WDON bit is reset only by stop mode clearance by means of an MCU reset. Do not use the REM or REMD instruction on the ADSF bit during A/D conversion. The DTON bit is always in the reset state in active mode. If the TM or TMD instruction is used on a bit for which its use is prohibited, or on a nonexistent bit, the status flag value will be undetermined * 1 Applies to HD404374 Series. * 2 Applies to HD404374, HD404384, and HD404389 Series. Figure 4 Instruction Restrictions 27 HD404374/HD404384/HD404389/HD404082 Series RAM address SSR MIS PMR0 PMR1 PMR2 PMR3 MSR1 MSR2 TMA TMB1 TMB2 TRBL/TWBL TRBU/TWBU TMC1 TMC2 TRCL/TWCL TRCU/TWCU $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 Bit 3 Bit 2 Bit 1 Bit 0 Interrupt control bit area *1 32 kHz oscillation stop setting 32 kHz frequency division*1 ratio selection Pull-up MOS control Not used System clock selection *1 System clock frequency division ratio switching Interrupt frame period selection *1 Not used Not used D0/INT0 Not used R00/WU0 Not used R13/TOB R10/EVNB R20/TOC R22/SI/SO R21/SCK Not used Timer B lock on/off Timer C clock on/off Not used Serial clock on/off A/D clock on/off *2 Not used Timer A / time base Timer A clock source selection Reload on/off Timer B clock source selection Timer B output mode setting EVNB edge detection selection Not used Timer B register (lower) Timer B register (upper) Timer C clock source selection Reload on/off Time C output mode selection Not used Not used Timer C register (lower) Timer C register (upper) Not used SMR1 SMR2 SRL SRU AMR ADRL ADRM ADRU $01F $020 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C Register flag area Serial transfer clock speed selection Not used Not used SO idle H/L setting Serial data register (lower) Serial data register (upper) Analog channel selection *2 A/D conversion time *2 A/D data register (bit 1, 0) *2 Not used A/D data register (bit 5 to 2) *2 A/D data register (bit 9 to 6) *2 R22/SI/SO PMOS control Not used DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 $02F $030 $031 $032 $033 $034 $035 $036 $037 PortD3DCR PortD2DCR PortD1DCR PortD6DCR PorD5DCR PortD7DCR Not used PortD9DCR Not used Not used Not used PortR13DCR Not used PortR22DCR PortR21DCR PortD0DCR PortD4DCR PortD8DCR PortR00DCR PortR10DCR PortR20DCR Not used $03A DCR7 $03B $03C PortR73DCR PortR72DCR PortR71DCR Not used $03F Notes: *1 Applies to HD404374 Series. *2 Applies to HD404374, HD404384, and HD404389 Series. Figure 5 Special Function Register Area 28 PortR70DCR HD404374/HD404384/HD404389/HD404082 Series $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04A $04B $04C $04D $04E $04F MR (0) MR (1) MR (2) MR (3) MR (4) MR (5) MR (6) MR (7) MR (8) MR (9) MR (10) MR (11) MR (12) MR (13) MR (14) MR (15) (a) Memory registers 960 Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level 1,023 Level 16 $3C0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 $3FF Bit 3 Bit 2 Bit 1 Bit 0 1020 ST PC13 PC12 PC11 $3FC 1021 PC10 PC9 PC8 PC7 $3FD 1022 CA PC6 PC5 PC4 $3FE 1023 PC3 PC2 PC1 PC0 $3FF (b) Stack area PC13 to PC0 ST CA : Program counter : Status flag : Carry flag Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position 29 HD404374/HD404384/HD404389/HD404082 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. they are shown in figure 7 and described below. 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register 0 (B) Initial value: Undefined, R/W 1 W register (W) Initial value: Undefined, R/W 3 X register 0 (X) Initial value: Undefined, R/W 3 Y register 0 (Y) Initial value: Undefined, R/W 3 SPX register 0 (SPX) Initial value: Undefined, R/W 3 SPY register Carry flag Status flag Program counter Initial value: $0000, no R/W 0 (SPY) Initial value: Undefined, R/W Initial value: Undefined, R/W 0 (CA) Initial value: 1, no R/W 0 (ST) 13 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 0 5 1 1 1 1 0 (SP) Figure 7 Registers and Flags Accumulator (A) and B register (B): The accumulator and B register are 4-bit registers used to hold the result of an ALU operation, and for data transfer to or from memory, an I/O area, or another register. 30 HD404374/HD404384/HD404389/HD404082 Series W register (W), X register (X) and Y register (Y): The W register is a 2-bit register, and the X and Y registers are 4-bit registers, used for RAM register indirect addressing. The Y register is also used for D port addressing. SPX register (SPX) and SPY register (SPY): The SPX and SPY registers are 4-bit registers used as X register and Y register auxiliary registers, respectively. Carry flag (CA): This flag holds ALU overflow when an arithmetic/logic instruction is executed. It is also affected by the SEC, REC, ROTL, and ROTR instructions. The contents of the carry flag are saved to the stack when interrupt handling is performed, and are restored from the stack by the RTNI instruction (but are not affected by the RTN instruction). Status flag (ST): This flag holds ALU overflow when an arithmetic/logic or compare instruction is executed, and the result of an ALU non-zero or bit test instruction. It is used as the branch condition for the BR, BRL, CAL, and CALL instructions. The status flag is a latch-type flag, and does not change until the next arithmetic/logic, compare, or bit test instruction is executed. After a BR, BRL, CAL, or CALL instruction, the status flag is set to 1 regardless of whether the instruction is executed or skipped. The contents of the status flag are saved to the stack when interrupt handling is performed, and are restored from the stack by the RTNI instruction (but are not affected by the RTN instruction). Program counter (PC): This is a 14-bit binary counter that holds ROM address information. Stack pointer (SP): The stack pointer is a 10-bit register that holds the address of the next save space in the stack area. The stack pointer is initialized to $3FF by an MCU reset. The stack pointer is decremented by 4 each time data is saved, and incremented by 4 each time data is restored. The upper 4 bits of the stack pointer are fixed at 1111, so that a maximum of 16 stack levels can be used. There are two ways in which the stack pointer is initialized to $3FF: by an MCU reset as mentioned above, or by resetting the RSP bit with the REM or REMD instruction. Reset An MCU reset is performed by driving the RESET pin low. At power-on, and when subactive mode, watch mode, or stop mode is cleared, RESET should be input for at least tRC to provide the oscillation settling time for the oscillator.In other cases, the MCU is reset by inputting RESET for at least two instruction cycles. Table 1 shows the areas initialized by an MCU reset, and their initial values. 31 HD404374/HD404384/HD404389/HD404082 Series Table 1 (1) Initial Values after MCU Reset Abbr. Initial value Contents Program counter (PC) $0000 Program executed from ROM start address Status flag (ST) 1 Branching by conditional branch instruction enabled Stack pointer (SP) $3FF Stack level is 0 Interrupt (IE) 0 All interrupts disabled Item Interrupt enable flag flags/ mask Interrupt request flag I/O Timers 32 (IF) 0 No interrupt requests Interrupt mask (IM) 1 Interrupt requests masked Port data register (PDR) All bits 1 "1" level output possible Data control registers (DCD0 ~ 2) All bits 0 Output buffer off (high impedance) Data control registers (DCR00 , DCR10, DCR13, DCR20 – DCR22, DCR70 – DCR73) All bits 0 Port mode register 0 (PMR0) ---0 See port mode register 0 section Port mode register 1 (PMR1) ---0 See port mode register 1 section Port mode register 2 (PMR2) 0--0 See port mode register 2 section Port mode register 3 (PMR3) 0000 See port mode register 3 section Timer mode register A (TMA) 0000 See timer mode register A section Timer mode register B1 (TMB1) 0000 See timer mode register B1 section Timer mode register B2 (TMB2) -000 See timer mode register B2 section Timer mode register C1 (TMC1) 0000 See timer mode register C1 section Timer mode register C2 (TMC2) -0-- See timer mode register C2 section Prescaler S (PSS) $000 Prescaler W (PSW) $00 Timer/counter A (TCA) $00 Timer/counter B (TCB) $00 Timer/counter C (TCC) $00 Timer write register B (TWBU,L) $X0 Timer write register C (TWCU,L) $X0 HD404374/HD404384/HD404389/HD404082 Series Table 1 (2) Initial Values after MCU Reset Abbr. Initial value Contents Serial mode register 1 (SMR1) 0000 See serial mode register 1 section Serial mode register 2 (SMR2) -0X- See serial mode register 2 section Serial data register (SRU,L) Item Serial interface Octal counter A/D converter Bit registers Others $XX 000 A/D mode register (AMR) 0000 See A/D mode register section A/D data register U (ADRU) 0111 See A/D data register section A/D data register M (ADRM) 1111 A/D data register L (ADRL) 11- - Low speed on flag (LSON) 0 See low-power mode section Watchdog timer on flag (WDON) 0 See timer C section A/D start flag (ADSF) 0 See A/D converter section Direct transfer on flag (DTON) 0 See low-power mode section Gear enable flag (GEF) 0 See system clock gear function Miscellaneous register (MIS) 0-00 See low-power mode and input/output sections System clock select register (SSR) 0000 See low-power mode and oscillator circuit sections Module standby register 1 (MSR1) --00 See timer section Module standby register 2 (MSR2) --00 See serial interface and A/D converter sections Notes: 1. The state of registers and flags other than those listed above after an MCU reset is shown in table 1 (3). 2. X: Indicates invalid value, - indicates that the bit does not exist. Table 1 (3) Initial Values after MCU Reset Item Abbr. After Stop Mode Clearance by WU0 After Other MCU Reset Carry flag (CA) Accumulator (A) Retain value immediately prior to entering stop mode Value immediately prior to MCU reset is not guaranteed. Must be initialized by program. B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) RAM 33 HD404374/HD404384/HD404389/HD404082 Series Interrupts There are a total of seven interrupt sources, comprising wakeup input (WU0), external interrupts (INT0), timer/counter (timer A, timer B, timer C) interrupts, a serial interface interrupt, and an A/D converter interrupt. Each interrupt source is provided with an interrupt request flag, interrupt mask, and vector address, used for storing and controlling interrupt requests. In addition, an interrupt enable flag is provided to control interrupts as a whole. Of the interrupt sources, the A/D converter and serial interface share the same vector address. Software must therefore determine which of the interrupt sources is requesting an interrupt at the start of interrupt handling. Interrupt control bits and interrupt handling: The interrupt control bits are mapped onto RAM addresses $000 to $003 and $023, and can be accessed by RAM bit manipulation instructions. However, the interrupt request flags (IF) cannot be set by software. When the MCU is reset, the interrupt enable flag (IE) and interrupt request flags (IF) are initialized to 0, and the interrupt masks (IM) are initialized to 1. Figure 8 shows a block diagram of the interrupt control circuit, table 2 shows interrupt priorities and vector addresses, and table 3 lists the conditions for executing interrupt handling for each of the nine kinds of interrupt source. When the interrupt request flag is set to 1 and the interrupt mask is cleared to 0, an interrupt is requested. If the interrupt enable flag is set to 1 at this time, interrupt handling is started. The vector address corresponding to the interrupt source is generated by the priority control circuit. The interrupt handling sequence is shown in figure 9, and the interrupt handling flowchart in figure 10. When an interrupt is accepted, execution of the previous instruction is completed in the first cycle. In the second cycle, the interrupt enable flag (IE) is reset. In the second and third cycles, the contents of the carry flag, status flag, and program counter are saved on the stack. In the third cycle, a jump is made to the vector address and instruction execution is resumed from that address. In each vector address area, a JMPL instruction should be written that branches to the start address of the interrupt routine. In the interrupt routine, the interrupt request flag that caused interrupt handling must be reset by software. 34 HD404374/HD404384/HD404389/HD404082 Series Table 2 Vector Addresses and Interrupt Priorities Interrupt Source Priority Vector Address RESET — $0000 WU0 1 $0002 INT0 2 $0004 Timer A 3 $0008 Timer B 4 $000A Timer C 5 $000C Serial interface, A/D converter 6 $000E 35 HD404374/HD404384/HD404389/HD404082 Series $000,0 I/E Interrupt request $000,2 (WU0 interrupt) IFWU $000,3 IMWU $001,0 (INT0 interrupt) Priority control circuit Vector address IF0 $001,1 IM0 $002,0 (Timer A interrupt) IFTA $002,1 IMTA $002,2 (Timer B interrupt) IFTB $002,3 IMTB $003,0 (Timer C interrupt) IFTC $003,1 IMTC (A/D interrupt) $003,2 $023,2 IFAD IFS $003,3 $023,3 IMAD IMS Figure 8 Block Diagram of Interrupt Control Circuit 36 (Serial interrupt) HD404374/HD404384/HD404389/HD404082 Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Control Bit WU0 INT0 Timer A Timer B Timer C A/D or Serial IE 1 1 1 1 1 1 IFWU•IMWU 1 0 0 0 0 0 IF0•IM0 * 1 0 0 0 0 IFTA•IMTA * * 1 0 0 0 IFTB•IMTB * * * 1 0 0 IFTC•IMTC * * * * 1 0 IFAD•IMAD+IFS•IMS * * * * * 1 Note: Operation is not affected whether the value is 0 or 1. Instruction cycle 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Save to stack IE reset Save to stack Vector address generated Execution of JMPL instruction at vector address Execution of instruction at start address of interrupt routine Note: The stack is accessed and the IE reset after the instruction is executed, even if it is a 2cycle instruction. Figure 9 Interrupt Sequence 37 HD404374/HD404384/HD404389/HD404082 Series Power ON RESET="0"? No Yes Interrupt request? Yes No IE="1"? Yes Execute instruction Accept interrupt Reset MCU IE←"0" Stack←(PC) Stack←(CA) Stack←(ST) PC←(PC)+1 PC←$0002 Yes WU0 interrupt? No PC←$0004 Yes INT0 interrupt? No PC←$0008 Yes Timer A interrupt? No PC←$000A Yes Timer B interrupt? No PC←$000C Yes Timer C interrupt? No PC←$000E (A/D, serial interrupt) Figure 10 Interrupt Handling Flowchart 38 HD404374/HD404384/HD404389/HD404082 Series Interrupt enable flag (IE: $000,0): The interrupt enable flag controls interrupt enabling/disabling of all interrupt requests as shown in table 4. The interrupt enable flag is reset by interrupt handling and set by the RTNI instruction. Table 4 Interrupt Enable Flag (IE: $000,0) Interrupt Enable Flag (IE) Interrupt Enabling/Disabling 0 Interrupts disabled 1 Interrupts enabled Wakeup interrupt request flag (IFWU: $000,2): The wakeup interrupt request flag (IFWU) is set by the detection of a falling edge in WU0 input in active mode, subactive mode,watch mode, or standby mode. In stop mode, when a falling edge is detected at the wakeup pin, the MCU waits for the oscillation settling time, then switches to active mode. When a transition is made from stop mode to active mode with IE set to 1 and IMWU cleared to 0, wakeup interrupt handling is executed after the switch to active mode. The wakeup interrupt request flag (IFWU) is not set in this case (table 5). Table 5 Wakeup Interrupt Request Flag (IFWU: $000,2) Wakeup Interrupt Request Flag (IFWU) Interrupt Request 0 No wakeup interrupt request 1 Wakeup interrupt request generated Wakeup Interrupt Mask (IMWU: $000,3): This bit masks an interrupt request by the wakeup interrupt request flag (table 6). Table 6 Wakeup Interrupt Request Mask (IMWU: $000,3) Wakeup Interrupt Mask (IMWU) Interrupt Request 0 Wakeup interrupt request enabled 1 Wakeup interrupt request masked (held pending) 39 HD404374/HD404384/HD404389/HD404082 Series External interrupt request flag (IF0: $001, 0): The external interrupt request flag is set by an INT0 input falling edge (table 7). Table 7 External Interrupt Request Flag (IF0: $001, 0) External Interrupt Request Flag (IF0) Interrupt Request 0 No external interrupt request 1 External interrupt request generated External interrupt mask (IM0: $001, 1): This bit masks an interrupt request by the external interrupt request flag (table 8). Table 8 External Interrupt Mask (IM0: $001, 1) External Interrupt Mask (IM0) Interrupt Request 0 External interrupt request enabled 1 External interrupt request masked (held pending) Timer A interrupt request flag (IFTA: $002,0): The timer A interrupt request flag is set by timer A overflow output (table 9). Table 9 Timer A Interrupt Request Flag (IFTA: $002,0) Timer A Interrupt Request Flag (IFTA) Interrupt Request 0 No timer A interrupt request 1 Timer A interrupt request generated Timer A interrupt mask (IMTA: $002,1): This bit masks an interrupt request by the timer A interrupt request flag (table 10). Table 10 Timer A Interrupt Mask (IMTA: $002,1) Timer A Interrupt Mask (IMTA) Interrupt Request 0 Timer A interrupt request enabled 1 Timer A interrupt request masked (held pending) 40 HD404374/HD404384/HD404389/HD404082 Series Timer B interrupt request flag (IFTB: $002,2): The timer B interrupt request flag is set by timer B overflow output (table 11). Table 11 Timer B Interrupt Request Flag (IFTB: $002,2) Timer B Interrupt Request Flag (IFTB) Interrupt Request 0 No timer B interrupt request 1 Timer B interrupt request generated Timer B interrupt mask (IMTB: $002,3): This bit masks an interrupt request by the timer B interrupt request flag (table 12). Table 12 Timer B Interrupt Mask (IMTB: $002,3) Timer B Interrupt Mask (IMTB) Interrupt Request 0 Timer B interrupt request enabled 1 Timer B interrupt request masked (held pending) Timer C interrupt request flag (IFTC: $003,0): The timer C interrupt request flag is set by timer C overflow output (table 13). Table 13 Timer C Interrupt Request Flag (IFTC: $003,0) Timer C Interrupt Request Flag (IFTC) Interrupt Request 0 No timer C interrupt request 1 Timer C interrupt request generated (held pending) Timer C interrupt mask (IMTC: $003,1): This bit masks an interrupt request by the timer C interrupt request flag (table 14). Table 14 Timer C Interrupt Mask (IMTC: $003,1) Timer C Interrupt Mask (IMTC) Interrupt Request 0 Timer C interrupt request enabled 1 Timer C interrupt request masked (held pending) 41 HD404374/HD404384/HD404389/HD404082 Series Serial interrupt request flag (IFS: $023,2): The serial interrupt request flag is set on completion of serial data transfer, or if data transfer is halted midway (table 15). Table 15 Serial Interrupt Request Flag (IFS: $023,2) Serial Interrupt Request Flag (IFS) Interrupt Request 0 No serial interrupt request 1 Serial interrupt request generated Serial interrupt mask (IMS: $023,3): This bit masks an interrupt request by the serial interrupt request flag (table 16). Table 16 Serial Interrupt Mask (IMS: $023,3) Serial Interrupt Mask (IMS) Interrupt Request 0 Serial interrupt request enabled 1 Serial interrupt request masked (held pending) A/D interrupt request flag (IFAD: $003,2) (Applies to HD404374, HD404384, and HD404389 Series): The A/D interrupt request flag is set on completion of A/D conversion (table 17). Table 17 A/D Interrupt Request Flag (IFAD: $003,2) A/D Interrupt Request Flag (IFAD) Interrupt Request 0 No A/D interrupt request 1 A/D interrupt request generated A/D interrupt mask (IMAD: $003,3) (Applies to HD404374, HD404384, and HD404389 Series): This bit masks an interrupt request by the A/D interrupt request flag (table 18). Table 18 A/D Interrupt Mask (IMAD: $003,3) Serial Interrupt Mask (IMAD) Interrupt Request 0 A/D interrupt request enabled 1 A/D interrupt request masked (held pending) 42 HD404374/HD404384/HD404389/HD404082 Series Operating Modes The five operating modes shown in table 19 can be used for the MCU. The function of each mode is shown in table 20, and the state transition diagram among each mode in figure 11. Table 19 Operating Modes and Clock Status Mode Name Stop Watch*1 Subactive*1, 3 SBY RESET cancellation, instruction interrupt request, WU0 input in stop mode STOP/SBY instruction in subactive mode (when direct transfer is selected) STOP instruction when TMA3 = 0 STOP instruction when TMA3 = 1 INT0/timer A or WU0 interrupt request in watch mode OP Stopped Stopped Stopped OP OP Active Activation method Status System oscillator 1 Subsystem oscillator* OP Cancellation method RESET input, STOP/SBY instruction Standby OP 2 OP OP* RESET input, interrupt request RESET input, WU0 input RESET input, RESET STOP/SBY input, INT0/timer A instruction or WU0 interrupt request Notes: OP: implies in operation. 1. Applies to HD404374 Series. 2. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $004) 3. Subactive mode is an optional function; specify it on the fnction option list. 43 HD404374/HD404384/HD404389/HD404082 Series Table 20 Operation in Low-Power Dissipation Modes Function Stop Mode Watch mode*1 Standby Mode Subactive Mode*1, 3 CPU Retained Retained Retained OP RAM Retained Retained Retained OP Timer A Stopped OP OP OP Timer B Stopped Stopped OP OP Timer C Stopped OP OP OP OP Serial interface 4 Stopped * Stopped 2 Stopped * 2 A/D * Stopped Stopped OP Stopped I/O Retained Retained Retained OP Notes: OP: implies in operation. 1. Applies to HD404374 Series. 2. Transmission/Reception is activated if a clock is input in external clock mode. However, interrupts stop. 3. Subactive mode is an optional function specified on the function option list. 4. Applies to HD404374, HD404384, and HD404389 Series. 44 HD404374/HD404384/HD404389/HD404082 Series Reset by RESET pin input or watchdog timer Stop mode (TMA3=0,SSR3=0,LSON=0) fosc fx øCPU øCLK øPER Reset Standby mode fosc fx øCPU øCLK øPER : Active : Active : Stop : fcyc : fcyc : Stop : Active : Stop : Stop : Stop WU0 Active mode SBY instruction fosc fx øCPU øCLK øPER interrupt : Active : Active : fcyc : fcyc : fcyc (TMA3=0,SSR3=1,LSON=0) STOP instruction fosc : Stop fx : Stop WU0 øCPU : Stop øCLK : Stop STOP øPER : Stop instruction (TMA3=0) *4 fosc fx øCPU øCLK øPER : Active : Active : Stop : fw : fcyc Subactive mode (TMA3=1) SBY instruction fosc fx øCPU øCLK øPER interrupt : Active : Active : fcyc : fw : fcyc fosc fx øCPU øCLK øPER *1 : Stop : Active : fSUB : fw : fSUB STOP instruction *2 Timer A, WU0 or INT0 interrupt STOP instruction Timer A, WU0 or INT0 interrupt *3 Watch mode fosc : Main oscillator frequency fx : Sub-oscillator frequency (for realtime clock) fcyc : fOSC/32 or fOSC/4 (selected by software) fw : fx/8 fSUB : fx/8 or fx/4 (selected by software) øCPU : System clock øCLK : Clock for realtime clock øPER : Peripheral function clock LSON : Low speed on flag DTON : Direct transfer on flag TMA3 : Timer mode register A bit3 fosc fx øCPU øCLK øPER : Stop : Active : Stop : fw : Stop (TMA3=1,LSON=0) fosc fx øCPU øCLK øPER : Stop : Active : Stop : fw : Stop (TMA3=1,LSON=1) Transition Condition DTON LSON TMA3 *1 STOP/SBY instruction 1 0 1 *2 STOP/SBY instruction 0 0 1 *3 STOP/SBY instruction Don’t care 1 1 *4 STOP/SBY instruction 0 0 0 Note: Watch mode and subactive mode apply to HD404374 Series. Figure 11 MCU Status Transitions 45 HD404374/HD404384/HD404389/HD404082 Series Active mode: In active mode all functions operate. In this mode, the MCU operates on clocks generated by the OSC1 and OSC2 oscillator circuits. Standby mode: In standby mode the oscillators continue to operate but clocks relating to instruction execution halt. As a result, CPU operation stops, and registers, RAM, and the D port/R port set for output retain their state immediately prior to entering standby mode. Interrupts, timers, the serial interface, and other peripheral functions continue to operate. Power consumption is lower than in active mode due to the halting of the CPU. The MCU is switched to standby mode by executing the SBY instruction in active mode. Standby mode is cleared by RESET input or an interrupt request. When standby mode is cleared by RESET input, an MCU reset is performed. When standby mode is cleared by an interrupt request, the MCU enters active mode and executes a instruction following the SBY instruction. After executing the instruction, if the interrupt enable flag is set to 1, interrupt handling is executed; if the interrupt enable flag is cleared to 0, the interrupt request is held pending and normal instruction execution is continued. MCU operation flowchart is shown in figure 12. 46 HD404374/HD404384/HD404389/HD404082 Series Stop mode No RESET=0? No RESET=0? Yes Yes No WU0 = Watch mode*1 Standby mode IFWU·IMWU =1? No Yes ? IF0·IM0 = 1? Yes No Yes IFTA · IMTA = 1? No Yes No IFTB · IMTB = 1? Yes*2 IFTC· IMTC = 1? System clock oscillator started No Yes*2 System reset IFAD·IMAD+ IFS·IMS = 1? No Yes*2 System clock oscillator started Next Instruction execution NOP Notes: 1. Applies to HD404374 Series No 2. Only when clearing from standby mode System clock oscillator started IF = 1, IM = 0, IE = 1? Yes Next Instruction execution Interrupts enabled Figure 12 MCU Operation Flowchart 47 HD404374/HD404384/HD404389/HD404082 Series Stop mode: In stop mode, all MCU function stop except that states prior to entry into stop mode are retained. This mode thus has the lowest power consumption of all operating mode. In stop mode, the OSC1 and OSC2 oscillators stop. Bit 3 (SSR3) of the system clock select register (SSR: $004) (figure 22) can be used to select the active (= 0) or stopped (= 1) state for the X1 and X2 oscillators. The MCU is switched to stop mode by executing a STOP instruction while bit 3 (TMA3) of timer mode register A (TMA: $00F) (figure 33) is cleared to 0 in active mode. Stop mode is cleared by RESET or WU0 input. When stop mode is cleared by RESET, the RESET signal should be input for at least the oscillation settling time (tRC) (see "AC Characteristics") shown in figure 13. Then, the MCU is initialized and starts instruction execution from the start (address 0) of the program (IE = 0, IMWU = 0). If IE is set before entering stop mode (IE = 1, IMWU = 0), wakeup interrupt handling is executed after the transition to active mode. When the MCU detects a falling edge at WU0 in stop mode, it automatically waits for the oscillation settling time, then switches to active mode. After the transition to active mode, the MCU resumes program execution from the instruction following the STOP instruction. If stop mode is cleared by wakeup input, RAM data and registers retain their values prior to entering stop mode. Stop mode Oscillator Internal clock RESET tres STOP instruction executed (At least oscillation settling time (tRC)) Figure 13 Timing Chart for Clearing Stop Mode by RESET Input Note: If stop mode is cleared by wakeup input when an external clock is used as the system clock (OSC1), the subclock should not be stopped in stop mode. Watch mode ( Applies to HD404374 Series) : In watch mode, the realtime clock function (timer A) and LCD function using the X1 and X2 oscillators operate, but other functions stop. This mode thus has the second lowest power consumption after stop mode, and is useful for performing realtime clock display only. In watch mode, the OSC 1 and OSC2 oscillators stop but the X1 and X2 oscillators continue to operate. 48 HD404374/HD404384/HD404389/HD404082 Series The MCU is switched to watch mode by executing a STOP instruction while TMA3 = 1 in active mode, or by executing a STOP/SBY instruction in subactive mode. Watch mode is cleared by RESET input or an INT0,timer A or WU 0 interrupt request. For RESET input, refer to the section on stop mode. When watch mode is cleared by an INT0, timer A or W U0 interrupt request, the mode transition depends on the value of the LSON bit: the MCU enters active mode if LSON = 0, and enters subactive mode if LSON = 1. In the case of a transition to active mode, interrupt request generation is delayed to secure the oscillation settling time: the delay is the tRC set time for the timer A interrupt, and, for the INT0 interrupt or WU0 interrupt, Tx (T + tRC < Tx < 2T + tRC) if bit 1 and 0 (MIS1, MIS0) of the miscellaneous register are set to 00, or Tx (tRC < Tx < T + tRC) if MIS1 and MIS0 are set to 01 or 10 (figures 14 and 15). Other operations when the transition is made are the same as when watch mode is cleared (figure 12). Subactive mode ( Applies to HD404374 Series): In subactive mode, the OSC1 and OSC2 oscillator circuits stop and the MCU operates on clocks generated by the X1 and X2 oscillator circuits. In this mode, functions other than the A/D converter operate, but since the operating clocks are slow, power consumption is the lowest after watch mode. A CPU instruction processing speed of 244 µs or 122 µs can be selected according to whether bit 2 (SSR2) of the system clock select register (SSR: $004) is set to 1 or cleared to 0. The value of the SSR2 bit should be changed (0→1 or 1→0) only in active mode. If the value is changed in subactive mode, the MCU may operate incorrectly. Subactive mode is cleared by executing a STOP/SBY instruction. A transition is then made to either watch mode or active mode according to the value of the low speed on flag (LSON: $020,0) and the direct transfer on flag (DTON: $020,3). Subactive mode is a function option, and should be specified in the function option list. Interrupt frame ( Applies to HD404374 Series): In watch mode and subactive mode, øCLK is supplied to the timer A, WU0, and INT0 acceptance circuits. Prescaler W and timer A operate as time bases, and generate interrupt frame timing. Either of two values can be selected for the interrupt frame period, T, by means of the miscellaneous register (MIS: $005) (figure 15). In watch mode and subactive mode, the timing for generation of timer A, INT0 and WU0 interrupts is synchronized with the interrupt frame. Except for the case of an active mode transition, the interrupt strobe timing is used for interrupt request generation. Timer A generates overflow and interrupt requests at the interrupt strobe timing. 49 HD404374/HD404384/HD404389/HD404082 Series Oscillation stabilization period Active mode Watch mode Active mode Interrupt strobe INT0, WU0 Interrupt request generation T T Only in case of transition to active mode tRC TX T: Interrupt frame period tRC : Oscillation stabilization period Note: If the time from the fall of the INT0 or WU0 signal until the interrupt is accepted and active mode is entered and is designated TX, then TX will be in the following range : T+tRC≤TX≤2T+tRC (MIS1, MIS0=00) tRC≤TX≤T+tRC (MIS1, MIS0=01 or 10) Figure 14 Interrupt Frame Miscellaneous Register (MIS: $005) Bit 3 2 1 0 Read/Write W W W W Reset 0 0 0 0 Bit name MIS3 Not used*4 MIS1*1 See pull-up MOS control, figure 30 MIS1 0 1 MIS0*1 MIS0 0 1 0 1 Interrupt Frame Oscillation Settling period T(ms)*2 Time tRC(ms)*2 0.24414 3.90625 3.90625 Oscillator Circuit Condition 0.12207(0.24414)*3 External clock input, CR oscillation frequency 7.8125 Ceramic resonator 31.25 Crystal resonator Not used Notes: *1. Applies to HD404374 series. *2. T and tRC values are for use of a 32.768 kHz crystal oscillator at the X1-X2 pins. *3. This value applies only in case of direct transition operation. *4. Must always be cleared to 0. Setting to 1 will cause incorrect operation. Figure 15 Miscellaneous Register (MIS) 50 HD404374/HD404384/HD404389/HD404082 Series Direct transition from subactive to active mode (Applies to HD404374 Series): A direct transition can be made from subactive mode to active mode by controlling the direct transfer on flag (DTON: $020,3) and low speed on flag (LSON: $020,0). The procedure is shown below. (a) Set LSON = 0 and DTON = 1 in subactive mode. (b) Execute a STOP or SBY instruction. (c) After the lapse of the MCU internal processing time and the oscillation settling time, the MCU automatically switches from subactive mode to active mode (figure 16). Notes: 1. The DTON flag ($020,3) can be set in only subactive mode. It is always in the reset state in active mode. 2. The condition for transition time TD from the subactive mode to active mode is as follows: tRC < TD < T + tRC. STOP/SBY instruction execution MCU internal processing time Subactive mode Oscillation stabilization time Active mode (Set LSON =0, DTON =1) Interrupt strobe Direct transition completion timing T tRC TD T: Interrupt frame period tRC: Oscillation settling time TD: Direct transition time Figure 16 Direct Transition Timing MCU operation sequence: The MCU operates in accordance with the flowchart shown in figure 17. RESET input is asynchronous input, and the MCU immediately enters the reset state upon RESET input, regardless of its current state. In the low-power mode operation sequence, if a STOP/SBY instruction is executed while the IE flag is cleared and the interrupt flag is set, releasing the relevant interrupt mask, the STOP/SBY instruction is canceled (regarded as NOP) and the next instruction is executed. Therefore, when executing a STOP/SBY instruction, all interrupt flags must be cleared, or interrupts masked, beforehand. 51 HD404374/HD404384/HD404389/HD404082 Series STOP/SBY instruction IF=1 IM=0 No Yes Standby/watch mode (HD404374 Series) No Interrupt handling routine Stop Mode IE=0 Yes No IF=1 IM=0 WU0 = No Yes Yes Clearing Standby watch mode Clearing Stop mode Hardware NOP Execution NOP PC←(PC)+1 PC←(PC)+2 Hardware NOP Execution PC←(PC)+1 Instruction Execution MCU Operation Cycle Note: See figure 12, MCU Operation Flowchart, for IF and IM operation. Figure 17 MCU Operating Sequence (Low-Power Mode Operation) 52 Instruction Execution HD404374/HD404384/HD404389/HD404082 Series Usage notes (Applies to HD404374 Series): In watch mode and subactive mode, an interrupt will not be detected correctly if the INT0 or WU0 high or low-level period is shorter than the interrupt frame period. The MCU’s edge sensing method is shown in figure 18. The MCU samples the INT0 and WU0 signals at regular intervals, and if consecutive sampled values change from high to low, it determines that a falling edge has been generated. Interrupt detection errors occur since this sampling is performed at the interrupt frame period. If the highlevel period of the INT0 or WU0 signal is within an interrupt frame, as shown in figure 19 (a), the signal will be low at point A and point B, with the result that the falling edge will not be recognized. Similarly, If the low-level period of the INT0 or WU0 signal is within an interrupt frame, as shown in figure 19 (b), the signal will be high at point A and point B, with the result that the falling edge will not be recognized. In watch mode and subactive mode, therefore, ensure that the high-level and low-level periods of the INT 0 and WU 0 signals is at least as long as the interrupt frame period. INT0 or WU0 Sampling High Low Low Figure 18 Edge Sensing Method (a) High-level mode (b) Low-level mode INT0 or WU0 INT0 or WU0 Interrupt frame Point A: Low Point B: Low Interrupt frame Point A: High Point B: High Figure 19 Sampling Examples 53 HD404374/HD404384/HD404389/HD404082 Series Internal Oscillator Circuit Figure 20 shows the clock pulse generator circuit. As shown in table 21, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768 kHz crystal oscillator can be connected to X1 and X2. External clock operation is possible for the system oscillator. CR oscillation for system oscillator is possible. CR oscillation function is optional. Set bit 1 (SSR1) of the system clock select register (SSR: $004) according to the frequency of the oscillator connected to OSC1 and OSC2 (figure 22). Note: If the setting of bit 1 in the system clock select register does not match the frequency of the system oscillator, the subsystem using 32.768 kHz oscillation will not operate correctly in the HD404374 Series. Also, the CR oscillation frequency differs depending on the operating voltage and resistance value. Set bit 1 of the system clock select register to match the operating frequency. Note that if the frequency being used does not match the setting of bit 1 of the system clock select register, subsystems using the 32.768 kHz oscillation frequency will not operate correctly. LSON OSC2 CPU •ROM System oscillator fOSC 1/4 or 1/32 fcyc Timing tcyc generation division circuit* circuit øCPU •RAM • Registers, flags •I/O System clock selection circuit OSC1 Peripheral functions Interrupts øPER X2 Sub system clock oscillator fx 1/8 or 1/4 fSUB Timing division tsubcyc generator circuit* circuit TMA3 bit X1 1/8 division circuit Timing fW twcyc generation circuit Time base clock selection circuit øCLK Timer A interrupts HD404374 series Notes: The division ratio can be selected by setting bit 0 or bit 2 in the system clock select register (SSR:$004). Figure 20 Clock Pulse Generator Circuit 54 HD404374/HD404384/HD404389/HD404082 Series System Clock Gear Function The MCU has a built-in system clock gear function that allows the system clock divided by 4 or by 32 to be selected by software for the instruction execution time. Efficient power consumption can be achieved by operating at the divided-by-4 rate when high-speed processing is needed, and at the divided-by-32 rate at the other times. Figure 21 shows the system clock conversion method. System clock conversion from division-by-4 to division-by-32 is performed as follows. First, make the division-by-32 setting (SSR0 write), then set the gear enable flag (GEF: $021,3). This flag is used to distinguish between gear conversion and a transition to standby mode. Next, execute an SBY instruction. When the gear enable flag is not set, standby mode is entered; when this flag is set, gear conversion mode is entered. In this case a transition is made to standby mode for the duration of the gear conversion, but after the synchronization time has elapsed, a transition is made automatically to active mode. As soon as the transition is made to active mode, the gear enable flag is reset. The same procedure is used for conversion from division-by-32 to division-by-4. Clear all interrupts, then disable interrupts, before carrying out gear conversion. Incorrect operation may result if an interrupt is generated during gear conversion. Division-by-32 setting (SSR0 = 1) Set gear enable flag Execute SBY instruction Synchronization time Execute next instruction Division-by-4 setting (SSR0 = 0) Set gear enable flag Execute SBY instruction Synchronization time Execute next instruction Figure 21 System Clock Division Ratio Conversion Flowchart 55 HD404374/HD404384/HD404389/HD404082 Series Make sure to set bit 3 of the system clock select register to 1 if the HD404374 series is being used without the subsystem clock, and on the HD404384, HD404389, and HD404082 series. The microcomputer will malfunction if the setting is not 1. System clock select register (SSR: $004) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 SSR3 SSR2* SSR1* SSR0 Bit name System clock division ratio switch 0 Division-by-4 (fcyc - fOSC/4) 1 Division-by-32 (fcyc - fOSC/32) System clock division ratio switch 0 fosc=0.4–1.0MHz 1 fosc=1.6–8.5MHz Subsystem clock division ratio switch 0 fSUB=fx/8 1 fSUB=fx/4 Subsystem clock stop setting (HD404374 Series) 0 Subsystem clock operates in stop mode 1 Subsystem clock stops in stop mode This bit must be set to 1 following power-on and reset if the HD404374 series is being used without the subsystem clock, and on the HD404384, HD404389, and HD404082 series. If it is set to 0 (the initial value), malfunctioning may occur in the stop mode. Note: * Applies to HD404374 Series. The CR oscillation frequency differs depending on the operating voltage and resistance value. Set SSR1 to match the operating frequency. Note that if the frequency being used does not match the SSR1 setting, subsystems using the 32.768 kHz oscillation frequency will not operate correctly. Figure 22 System Clock Select Register 56 HD404374/HD404384/HD404389/HD404082 Series Table 21 Oscillator Circuit Examples Circuit Structure External clock operation External oscillator Circuit Constants OSC1 Open OSC2 C1 Ceramic oscillator (OSC1, OSC 2) Ceramic oscillator: CSA4.00MG (Murata) OSC1 Ceramic oscillator Rf GND OSC2 C2 C1 Crystal oscillator (OSC1, OSC 2) Rf=1MΩ±20% C1=C2=24pF±20% OSC1 Rf=1MΩ±20% C1=C2=10–20pF±20% Crystal oscillator Rf GND OSC2 C2 4 CR oscillator* (OSC1, OSC 2) Rf=20kΩ±1% OSC1 Rf OSC2 Crystal oscillator (X1, X2) HD404374 Series C1 X1 Crystal oscillator Crystal: 32.768 kHz: MX38T (Nihon Denpa Kogyo) C1=C2=20pF±20% X2 GND C2 Notes: 1. With a crystal or ceramic oscillator, circuit constants will differ depending on the resonator, stray capacitance in the interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator manufacturer. 2. Make the connections between the OSC1 and OSC 2 pins (X1 and X2 pins) and external components as short as possible, and ensure that no other lines cross these lines (see layout example in figure 23). 3. When 32.768 kHz crystal oscillation is not used, fix the X1 pin at V CC and leave the X2 pin open. 4. Applies to HD40C4372, HD40C4374, HD40C4382, HD40C4384, HD40C4388, HD40C4389, HD40C4081, HD40C4082, HCD40C4082, HD407C4374 and HD407C4384. 57 HD404374/HD404384/HD404389/HD404082 Series AVSS AVSS OSC1 OSC1 OSC2 OSC2 TEST TEST X2 NC X1 NC (GND) RESET RESET (GND) HD404374 Series HD404384/HD404389/HD404082 Series Figure 23 Typical Layouts of Crystal and Ceramic Oscillator 58 HD404374/HD404384/HD404389/HD404082 Series Input/Output The MCU has 20 input/output pins (D 0 to D9, R0, R10, R13, R20 to R2 2, R70 to R73). The features of these pins are described below. • The four pins D 0 to D3 are source large-current (10 mA max.) I/O pins. • The four pins D 4 to D7 are sink large-current (15 mA max.) I/O pins. • I/O pins comprise pins (D0, R0 0, R1 0, R1 3, R2 0 to R22, R70 to R73) that also have a peripheral function (timer, serial interface, etc.). With these pins, the peripheral function setting has priority over the D port or R port pin setting. When a peripheral function setting has been made for a pin, the pin function and input/output mode will be switched automatically in accordance with that setting. • Selection of input or output for I/O pins, or selection of the port or peripheral function for pins multiplexed as peripheral function pins, is performed by the program. • All output of the peripheral function pins are CMOS outputs. The SO pin and R2 2 port pin can be designated as NMOS open-drain output by the program. • A reset clears peripheral function selection. And since the data control registers (DCD, DCR) are also reset, input/output pins go to the high-impedance state. • Each I/O pin has a built-in pull-up MOS that can be turned on and off individually by the program. Figure 24 shows the I/O buffer configuration, and table 22 shows I/O pin circuit configuration control by the program. Table 23 shows the circuit configuration of each I/O pin. VCC Pull-up control signal Pull-up MOS MIS3 VCC PMOS Buffer control signal Output data NMOS DCD, DCR PDR Input data Input control signal Figure 24 I/O Pin Circuit Configuration 59 HD404374/HD404384/HD404389/HD404082 Series Table 22 Programmable I/O Circuits MIS3 (bit 3 of MIS) 0 DCD,DCR 0 PDR CMOS buffer 1 0 1 0 1 0 1 0 1 0 1 PMOS — — — ON — — — ON NMOS — — ON — — — ON — — — — — — ON — ON Pull-up MOS Note: 1 — : OFF Table 23 Circuit Configurations of I/O Pins Type I/O pins Circuit Configuration VCC VCC Pins Pull-up control signal MIS3 Buffer control signal DCD, DCR Output data D0-D9 R0 0 R1 0, R1 3 R2 0, R2 1 PDR Input data Input control signal VCC VCC Pull-up control signal Buffer control signal Output data MIS3 DCR SMR22 PDR R2 2 R7 0–R7 3 *2 R7 0-R73 AN 0-AN3 *1 Input data Input control signal VCC Pull-up control signal VCC Buffer control signal Output data MIS3 DCR PDR A/D input A/D channel control signal Input data Input control signal Notes: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared. 1. Applies to HD404374, HD404384, and HD404389 Series. 2. Applies to HD404082 Series. 60 HD404374/HD404384/HD404389/HD404082 Series Table 23 Circuit Configurations of I/O Pins (cont) Type Peripheral function pins Circuit Configuration I/O pins VCC VCC Pins Pull-up control signal Output data Input data Output pins VCC VCC Pull-up control signal Output data VCC SCK MIS3 PDR SMR22 SO Pull-up control signal Output data Input pins Input data SCK SCK PMOS control signal VCC MIS3 PDR I/O control signal MIS3 PDR SO TOB, TOC TOB, TOC RESET RESET VCC MIS3 WU0, INT0, EVNB, SI PDR WU0 etc. A/D Input AN 4, AN 5 *1 A/D channel control signal Note: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared. 1. Applies to HD404389 Series. 61 HD404374/HD404384/HD404389/HD404082 Series D Port The D port consists of 10 I/O pins that are addressed bit-by-bit. Ports D0 to D3 are source large-current I/O pins, and ports D4 to D7 are sink large-current I/O pins. The D port can be set and reset by the SED and RED instructions or the SEDD and REDD instructions. Output data is stored in the port data register (PDR) for each pin. The entire D port can be tested by the TD or TDD instruction. The D port output buffer is turned on and off by the D port data control registers (DCD0 to DCD2: $030 to $032). The DCD registers are mapped onto memory addresses (figure 25). Port D0 is multiplexed as interrupt input pin INT0. Setting as interrupt pin is performed by bit 0 (PMR00) of port mode register 0 (PMR0: $008) (figure 26). Data control registers (DCD0–2 : $030–$032) (DCR0–2, 7 : $034–$036, $03B) Register Name DCDn (n=0 to 2) DCRm (m=0 to 2, 7) Bit 3 2 1 0 Read/Write W W W W Reset 0 0 0 0 Bit name DCDn3 DCDn2 DCDn1 DCDn0 Read/Write W W W W Reset 0 0 0 0 Bit name DCRm3 DCRm2 DCRm1 DCRm0 All bits CMOS buffer control 0 CMOS buffer off (high impedance) 1 CMOS buffer active Correspondence between each bit of DCD and DCR and ports Register Name Bit 3 Bit 2 Bit 1 Bit 0 DCD0 D3 D2 D1 D0 DCD1 D7 D6 D5 D4 D9 D8 DCD2 R00 DCR0 DCR1 R13 DCR2 DCR7 R73 R10 R22 R21 R20 R72 R71 R70 Figure 25 Data Control Registers (DCD, DCR) 62 HD404374/HD404384/HD404389/HD404082 Series R Port The R port consists of 10 I/O pins that are addressed in 4-bit units. Input can be performed by means of the LAR and LBR instructions, and output by means of the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The R port output buffer is turned on and off by the R port data control registers (DCR0 to DCR2, DCR7: $034 to $036, $03B). The DCR registers are mapped onto memory addresses (figure 25). Port R00 is multiplexed as wakeup input pin WU0 . Setting of this pin as peripheral function pins is performed by port mode register 1 (PMR1: $009) (figure 27). Port R1 0 is multiplexed as peripheral function pin EVNB. Setting of this pin as peripheral function pins is performed by bit 0 (PMR20) of port mode register 2 (PMR2: $00A) (figure 28). Ports R1 3 and R20 are multiplexed as peripheral function pins TOB, and TOC, respectively. Setting of these pins as peripheral function pins is performed by bits 3 (PMR23) of port mode register 2 (PMR2: $00A) and bit 0 (PMR30) of port mode register 3 (PMR3: $00B)(figures 28 and 29). Ports R21 and R22 are multiplexed as peripheral function pins SCK and SI/SO, respectively. Setting of these pins as peripheral function pins is performed by bits 1 to 3 (PMR31 to PMR33) of port mode register 3 (PMR3: $00B) (figure 29). Ports R7 0 to R73 are multiplexed as peripheral function pins AN0 to AN3 (HD404374, HD404384, and HD404389 Series only). Setting of these pins as peripheral function pins is performed by bits 1 to 3 (AMR1 to AMR3) of the A/D mode register (AMR: $028) (see figure 64 in section 8, A/D Converter). Port mode register 0 (PMR0: $008) Bit 3 2 1 0 Read/Write W Initial value on reset 0 Bit name Not used Not used Not used PMR00 PMR00 D0/INT0 pin mode selection 0 D0 1 INT0 Figure 26 Port Mode Register 0 (PMR0: $008) 63 HD404374/HD404384/HD404389/HD404082 Series Port mode register 1 (PMR1: $009) Bit 3 2 1 0 Read/Write W Initial value on reset 0 Bit name Not used Not used Not used PMR10 PMR10 R00/WU0 pin mode selection 0 R00 1 WU0 Figure 27 Port Mode Register 1 (PMR1: $009) Port mode register 2 (PMR2: $00A) 2 1 Bit 3 Read/Write W W Initial value on reset 0 0 Bit name PMR23 Not used Not used PMR23 R13/TOB pin mode selection 0 R13 1 TOB 0 PMR20 PMR20 R10/EVNB pin mode selection 0 R10 1 EVNB Figure 28 Port Mode Register 2 (PMR2: $00A) 64 HD404374/HD404384/HD404389/HD404082 Series Port mode register 3 (PMR3: $00B) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 PMR33 PMR32 PMR31 PMR30 Bit name PMR30 R20/TOC pin mode selection 0 R20 1 TOC PMR31 R21/SCK pin mode selection 0 R21 1 SCK PMR33 PMR32 R22/SI/SO pin mode selection 0 ∗ R22 1 0 SI 1 SO ∗ : Don't care Figure 29 Port Mode Register 3 (PMR3: $00B) Pull-Up MOS Control Program-controllable pull-ups MOS are incorporated in all I/O pins. On/off control of all pull-ups MOS is performed by bit 3 (MIS3) of the miscellaneous register (MIS: $005) and the port data register (PDR) for each pin, enabling the pull-up MOS to be turned on or off independently for each pin (table 22, figure 30). Except for analog input multiplexed pins, the pull-up MOS on/off setting can be made independent of the setting as an on-chip supporting module pin. 65 HD404374/HD404384/HD404389/HD404082 Series Bit 2 of the miscellaneous register must always be set to 0. The microcomputer will malfunction if it is set to 1. Miscellaneous register (MIS: $005) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 MIS3 Not used*1 MIS1 MIS0 Bit name tRC selection (See figure 15 in the Operating Modes section) MIS2 MIS3 Setting bit2 0 Set to 0 1 Use prohibited pull-up MOS control 0 All pull-ups MOS off 1 pull-up MOS active Note: 1. This bit must always be set to 0. The microcomputer will malfunction if it is set to 1. Figure 30 Miscellaneous Register (MIS:$005) Handling of I/O Pins Not Used by User System If I/O pins that are not used by the user system are left floating, they may generate noise that can result in chip malfunctions. Therefore, the pin potential must be fixed. In this case, pull the pins up to VCC with the built-in pull-up MOS or with an external resistor of approximately 100 kΩ. 66 HD404374/HD404384/HD404389/HD404082 Series Prescalers The MCU has the following prescalers, S and W (HD404374 Series). The operating conditions for each prescaler are shown in table 24, and the output supply destinations in figure 31. Timer A to C input clocks other than external events, and serial transfer clocks other than external clocks are selected from the prescaler outputs in accordance with the respective mode register. Prescaler Operation Prescaler S (PSS): Prescaler S is an 11-bit counter that has the system clock as input. When the MCU is reset, prescaler S is reset to $000, then divides the system clock. Prescaler S operation is stopped by a reset by the MCU, and in stop mode and watch mode*1. It does not stop in any other modes. Prescaler W (PSW) (HD404374 Series): Prescaler W is a counter that has a clock divided from the X1 input (32 kHz crystal oscillation) as input. When the MCU is reset, prescaler W is reset to $00, then divides the input clock. Prescaler W can also be reset by software. Table 24 Prescaler Operating Conditions Prescaler Input Clock Prescaler S System clock in active and MCU reset, stop mode standby modes, subsystem clearance clock in subactive mode*1 MCU reset, stop mode, watch mode*1 Prescaler W Clock obtained by division- MCU reset, software*2 by-8 of 32.768 kHz oscillation by subsystem clock oscillator MCU reset, stop mode Notes: 1 2 Reset Conditions Stop Conditions Applies to HD404374 Series If bits TMA3 to TMA1 in timer mode register A (TMA) are all set to 1, PSW is cleared to $00. 67 HD404374/HD404384/HD404389/HD404082 Series Subsystem clock Prescaler W Timer A HD404374 series Timer B Timer C System clock Clock selector Prescaler S Figure 31 Prescaler Output Destinations 68 Serial interface HD404374/HD404384/HD404389/HD404082 Series Timers The MCU incorporates three timers, A to C. • Timer A: Free-running timer • Timer B: Multifunctional timer • Timer C: Multifunctional timer Timer A is an 8-bit free-running timer. Timers B and C are 8-bit multifunctional timers; Each one of their have the functions shown in table 25 and their operating mode can be set by the program. Table 25 Timer Functions Functios Clock source Timer functions Timer outputs Timer A Timer B Timer C Prescaler S Available Available Available Prescaler W* Available — — External event — Available — Free-running Available Available Available Time-base* Available — — Event counter — Available — Reload — Available Available Watchdog — — Available Toggle — Available Available PWM — Available Available Note: — implies not available * Applies to HD404374 Series Timer A Timer A Functions Timer A has the following functions. • Free-running timer • Realtime clock time base The block diagram of timer A is shown in figure 32. 69 HD404374/HD404384/HD404389/HD404082 Series 1/4 1/2 2 fW fW t Wcyc Timer A interrupt request flag (IFTA) Prescaler W (PSW) ÷2 ÷8 ÷ 16 ÷ 32 32.768-kHz oscillator 1/2 t Wcyc Clock Timer counter A (TCA) Overflow ø PER System clock ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 1024 ÷ 2048 Selector Internal data bus Selector Selector HD404374 Series Prescaler S (PSS) 3 Timer mode register A (TMA) Data bus Clock line Signal line Figure 32 Timer A Block Diagram Timer A Operation Free-running timer operation: The timer A input clock is selected by timer mode register A (TMA: $00F). Timer A is reset to $00 by an MCU reset, and counts up each time the input clock is input. When the input clock is input after the timer A value reaches $FF, overflow output is generated, and the timer A value becomes $00. The generated overflow output sets the timer A interrupt request flag (IFTA: $002,0). Timer A continues counting up after the count value returns to $00, so that an interrupt is generated regularly every 256 input clock cycles. Realtime clock time base operation (HD404374 Series): Timer A can be used as the realtime clock time base by setting bit 3 (TMA3) of timer mode register A to 1. As the prescaler W output is input to timer/counter A, interrupts are generated with accurate timing using the 32.768 kHz crystal oscillator as the basic clock. When timer A is used as the realtime clock time base, prescaler W and timer/counter A can be reset to $00 by the program. 70 HD404374/HD404384/HD404389/HD404082 Series Timer A Register Timer A operation is set by means of the following register. Timer mode register A (TMA: $00F): Timer mode register A (TMA: $00F) is a 4-bit write-only register. Timer A operation and input clock selection are set as shown in figure 33. 71 HD404374/HD404384/HD404389/HD404082 Series Timer mode register A (TMA: $00F) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 TMA3*4 TMA2 TMA1 TMA0 TMA3*4 TMA2 TMA1 TMA0 Source prescaler 0 PSS 2,048 tcyc 1 PSS 1,024 tcyc 0 PSS 512 tcyc 1 PSS 128 tcyc 0 PSS 32 tcyc 1 PSS 8 tcyc 0 PSS 4 tcyc 1 PSS 2 tcyc 0 PSW 32 twcyc 1 PSW 16 twcyc 0 PSW 8 twcyc 1 PSW 2 twcyc 0 PSW Bit name Input clock period Operating mode 0 0 1 0 0 Timer A mode 1 1 0 0 1 1 0 1 1 Time base mode 1/2 twcyc 1 Not Used x PSW, TCA reset x : Don't care Notes : 1. twcyc = 244.14 µs (using 32.768 kHz crystal oscillator) 2. Timer/counter overflow output period (s) = input clock period (s) × 256. 3. The division ratio must not be changed while time base mode is being used, as this will result in an error in the overflow period. 4. Applies to HD404374 Series. In HD404384 Series, write as 0. Figure 33 Timer Mode Register A (TMA) 72 HD404374/HD404384/HD404389/HD404082 Series Timer B Timer B Functions: Timer B has the following functions. • Free-running/reload timer • External event counter • Timer output operation (toggle output, PWM output) The block diagram of timer B is shown in figure 34. Timer B ineterrupt request flag (IFTB) Timer C clock source Timer output control logic Edge detection logic EVNB Timer read register BL (TRBL) 2 ÷2 Timer read register BU (TRBU) 4 ÷8 ÷32 ÷128 Timer counter B ÷512 ÷2048 3 Free-runnning/Reload control øPER Selector System clock Prescaler S (PSS) ÷4 (TCBL) (TCBU) 4 4 Internal data bus 1 Overflow TOB Timer write register B (TWBL) (TWBU) Timer mode register B1 (TMB1) 3 Timer mode register B2 (TMB2) Data bus Clock line Signal line Figure 34 Timer B Block Diagram 73 HD404374/HD404384/HD404389/HD404082 Series Timer B Operation • Free-running/reload timer: Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected by means of timer mode register B1 (TMB1). Timer B is initialized to the value written to timer write register B (TWBL, TWBU) by software, and counts up by 1 each time the input clock is input. When the input clock is input after the timer B value reaches $FF, overflow output is generated. Timer B is then set to the value in timer write register B if the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts counting up again. Overflow output sets the timer B interrupt request flag (IFTB). This flag is reset by the program or by an MCU reset. For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial Values after MCU Reset. • External event counter operation: When external event input is designated for the input clock, timer B operates as an external event counter. When external event input is used, the R1 0/EVNB pin is designated as the EVNB pin by port mode register 2 (PMR2). The external event detected edge for timer B can be designated as a falling edge, rising edge, or both falling and rising edges in the input signal by means of timer mode register B2 (TMB2). If both falling and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc. Timer B counts up by 1 each time a falling edge is detected in the signal input at the EVNB pin. Other operations are the same as for the free-running/reload timer function. • Timer output operation: With timer B, the R13/TOB pin is designated as the TOB pin by the setting of bit 3 of port mode register 2 (PMR2), and toggle waveform output or PWM waveform output can be selected by timer mode register B2 (TMB2). Toggle output: With toggle output, the output level is changed upon input of the next clock pulse after the timer B value reaches $FF. Use of this function in combination with the reload timer allows a clock signal with any period to be output, enabling it to be used as buzzer output. The output waveform is shown in figure 35 (1). PWM output: With PWM output, variable-duty pulses are output. The output waveform is as shown in figure 35 (2), according to the contents of timer mode register B1 (TMB1) and timer write register B (TWBL, TWBU). When the waveform is output with bit 3 (TMB13) of timer mode register B1 cleared to 0, the write to timer write register B to change the duty is effective from the next frame, whereas if the waveform is output with the TMB13 bit set to 1 (reload setting), the next frame is output immediately after the timer write register write. • Module standby: With timer B, the supply of the system clock to the timer/counter can be halted by setting bit 0 of module standby register 1 (MSR1: $00D) to 1. In the module standby state, the mode register value is retained but the counter value is not guaranteed. 74 HD404374/HD404384/HD404389/HD404082 Series (1) Toggle output waveform (timer B, timer C) Free-running timer 256 clock periods 256 clock periods (256 – N) clock periods (256 – N) clock periods Reload timer (2) PWM output waveform (timer B, timer C) T × (N + 1) TMB13 = 0 TMC13 = 0 (free-running timer) T × 256 T TMB13 = 1 TMC13 = 1 (reload timer) T × (256 – N) Notes: T: Counter input clock period The clock input source and division ratio are controlled by timer mode register B1 and timer mode register C1. N: Value in timer write register B or timer write register C When N = 255 (= $FF), PWM output is always fixed at the timer low level.) ) ( Figure 35 Timer Output Waveforms 75 HD404374/HD404384/HD404389/HD404082 Series Timer B Registers Timer B operation setting and timer B value reading/writing is controlled by the following registers. Timer mode register B1 (TMB1: $010) Timer mode register B2 (TMB2: $011) Timer write register B (TWBL: $012, TWBU: $013) Timer read register B (TRBL: $012, TRBU: $013) Port mode register 2 (PMR2: $00A) Module standby register 1 (MSR1: $00D) • Timer mode register B1 (TMB1: $010): Timer mode register B1 (TMB1) is a 4-bit write-only register, used to select free-running/reload timer operation and the input clock as shown in figure 36. Timer mode register B1 (TMB1) is reset to $0 by an MCU reset: A modification of timer mode register B1 (TMB1) becomes effective after execution of two instructions following the timer mode register B1 (TMB1) write instruction. The program must provide for timer B initialization by writing to timer write register B (TWBL, TWBU) to be executed after the postmodification mode has become effective. 76 HD404374/HD404384/HD404389/HD404082 Series Timer mode register B1 (TMB1: $010) Bit 3 2 1 0 Read/Write W W W W Initial value on reset Bit name 0 0 0 0 TMB13 TMB12 TMB11 TMB10 TMB12 TMB11 TMB10 0 0 1 0 1 1 TMB13 Input clock period and input clock source 0 2,048 tcyc 1 512 tcyc 0 128 tcyc 1 32 tcyc 0 8 tcyc 1 4 tcyc 0 2 tcyc 1 R10/EVNB (external event input) Free-running/reload timer 0 Free-running timer 1 Reload timer Figure 36 Timer Mode Register B1 (TMB1) • Timer mode register B2 (TMB2: $011): Timer mode register B2 (TMB2) is a 3-bit write-only register, used to select the timer B output mode and EVNB pin detected edge as shown in figure 37. Timer mode register B2 (TMB2) is reset to $0 by an MCU reset. 77 HD404374/HD404384/HD404389/HD404082 Series Timer mode register B2 (TMB2: $011) Bit 3 2 1 0 Read/Write — W W W Initial value on reset — 0 0 0 Bit name — TMB22 TMB21 TMB20 TMB21 TMB20 0 1 TMB22 EVNB pin detected edge 0 Not detected 1 Falling edge detection 0 Rising edge detection 1 Both rising and falling edge detection Timer B output waveform 0 Toggle output 1 PWM output Figure 37 Timer Mode Register B2 (TMB2) • Timer write register B (TWBL: $012, TWBU:$013): Timer write register B (TWBL, TWBU) is a write-only register composed of a lower digit (TWBL) and an upper digit (TWBU) (figures 38 and 39). The lower digit (TWBL) of timer write register B is reset to $0 by an MCU reset, while the upper digit (TWBU) is undetermined. Timer B can be initialized by writing to timer write register B (TWBL, TWBU). To write the data, first write the lower digit (TWBL). The lower digit write does not change the timer B value. Next, write the upper digit (TWBU). Timer B is then initialized to the timer write register B (TWBL, TWBU) value. When writing to timer write register B (TWBL, TWBU) from the second time onward, if it is not necessary to change the lower digit (TWBL) reload value, timer B initialization is completed by the upper digit write alone. Timer write register B (lower) (TWBL: $012) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 TWBL3 TWBL2 TWBL1 TWBL0 Bit name Figure 38 Timer Write Register B (Lower) (TWBL) 78 HD404374/HD404384/HD404389/HD404082 Series Timer write register B (upper) (TWBU: $013) Bit Read/Write Initial value on reset Bit name 3 2 1 0 W W W W Undetermined Undetermined Undetermined Undetermined TWBU3 TWBU2 TWBU1 TWBU0 Figure 39 Timer Write Register B (Upper) (TWBU) • Timer read register B (TRBL: $012, TRBU: $013): Timer read register B (TRBL, TRBU) is a read-only register composed of a lower digit (TRBL) and an upper digit (TRBU) from which the value of the upper digit of timer B is read directly (figures 40 and 41). First, read the upper digit (TRBU) of timer read register B. The current value of the timer B upper digit is read and, at the same time, the value of the timer B lower digit is latched in the lower digit (TRBL) of timer read register B. The timer B value is obtained when the upper digit (TRBU) of timer read register B is read by reading the lower digit (TRBL) of timer read register B. Timer read register B (lower) (TRBL: $012) Bit 3 2 1 0 Read/Write R R R R Initial value on reset Bit name Undetermined Undetermined Undetermined Undetermined TRBL3 TRBL2 TRBL1 TRBL0 Figure 40 Timer Read Register B (Lower) (TRBL) Timer read register B (upper) (TRBU: $013) Bit Read/Write Initial value on reset Bit name 3 2 1 0 R R R R Undetermined Undetermined Undetermined Undetermined TRBU3 TRBU2 TRBU1 TRBU0 Figure 41 Timer Read Register B (Upper) (TRBU) 79 HD404374/HD404384/HD404389/HD404082 Series • Port mode register 2 (PMR2: $00A): Port mode register 2 (PMR2) is a write-only register used to set the function of the R10/EVNB and R1 3/TOB pins as shown in figure 42. Port mode register 2 (PMR2) is reset to $0 by an MCU reset. Port mode register 2 (PMR2: $00A) Bit 3 2 1 0 Read/Write W — — W Initial value on reset 0 — — 0 PMR23 Not used Not used PMR20 Bit name PMR23 R13/TOB pin mode selection 0 R13 1 TOB PMR20 R10/EVNB pin mode selection 0 R10 1 EVNB Figure 42 Port Mode Register 2 (PMR2: $00A) • Module standby register 1 (MSR1: $00D): Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the clock to timer B as shown in figure 43. Module standby register 1 (MSR1) is reset to $0 by an MCU reset. 80 HD404374/HD404384/HD404389/HD404082 Series Module standby register 1 (MSR1: $00D) Bit 3 2 1 0 Read/Write — — W W Initial value on reset — — 0 0 Not used Not used MSR11 MSR10 Bit name MSR10 Timer B clock supply control 0 Supplied 1 Stopped MSR11 Timer C clock supply control 0 Supplied 1 Stopped Figure 43 Module Standby Register 1 (MSR1) 81 HD404374/HD404384/HD404389/HD404082 Series Timer C Timer C Functions:Timer : C has the following functions. • Free-running/reload timer • Watchdog timer • Timer output operation (toggle output, PWM output) The block diagram of timer C is shown in figure 44. 82 HD404374/HD404384/HD404389/HD404082 Series System reset signal Watchdog on flag (WDON) Timer output control logic Timer B overflow Timer read register CL (TRCL) ÷2 Timer read register CU (TRCU) 4 ÷4 ÷8 Prescaler (PSS) ÷ 32 ÷ 128 Timer counter C Selector ÷ 512 ÷ 2048 3 Timer mode register C1 (TMC1) Timer output control Data bus (TCCL) (TCCU) 4 4 Internal data bus ø PER Overflow System clock Watchdog timer control logic Free-running/reload control TOC Timer C interrupt request flag (IFTC) Timer write register C (TWCL) (TWCU) Timer mode register C2 (TMC2) Clock line Signal line Figure 44 Timer C Block Diagram 83 HD404374/HD404384/HD404389/HD404082 Series Timer C Operation • Free-running/reload timer: Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected by means of timer mode register C1 (TMC1). Timer C is initialized to the value written to timer write register C (TWCL, TWCU) by software, and counts up by 1 each time the input clock is input. When the input clock is input after the timer C value reaches $FF, overflow output is generated. Timer C is then set to the value in timer write register C (TWCL, TWCU) if the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts counting up again. Overflow output sets the timer C interrupt request flag (IFTC). This flag is reset by the program or by an MCU reset. For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial Values after MCU Reset. • 16-bit timer operation: When timer B overflow flag is selected as the clock source, timer C can be used as a 16-bit timer that counts the timer B clock source pulses. In this case, since the timer B and timer C free-running/reload settings are independent, the settings should be made to suit the purpose. • Watchdog timer operation: By using the timer C overflow output, timer C can be used as a watchdog timer for detecting program runaway. The watchdog timer is enabled when the watchdog on flag (WDON) is set to 1, and generates an MCU reset when timer C overflows. Usually, timer C initialization is performed by the program before the timer C value reaches $FF, so controlling program runaway. • Timer output operation: With timer C, the R20/TOC pin is designated as the TOC pin by setting bit 0 of port mode register 3 (PMR3) to 1, and toggle waveform output or PWM waveform output can be selected by timer mode register C2 (TMC2). Toggle output The operation is similar to that for timer B toggle output. PWM output The operation is similar to that for timer B PWM output. • Module standby: The operation is similar to that for timer B module standby. 84 HD404374/HD404384/HD404389/HD404082 Series Timer C Registers Timer C operation setting and timer C value reading/writing is controlled by the following registers. Timer mode register C1 (TMC1: $014) Timer mode register C2 (TMC2: $015) Timer write register C (TWCL: $016, TWCU: $017) Timer read register C (TRCL: $016, TRCU: $017) Port mode register 3 (PMR3: $00B) Module standby register 1 (MSR1: $00D) • Timer mode register C1 (TMC1: $014): Timer mode register C1 (TMC1) is a 4-bit write-only register, used to select free-running/reload timer operation, the input clock, and the prescaler division ratio as shown in figure 45. Timer mode register C1 (TMC1) is reset to $0 by an MCU reset. A modification of timer mode register C1 (TMC1) becomes effective after execution of two instructions following the timer mode register C1 (TMC1) write instruction. The program must provide for timer C initialization by writing to timer write register C (TWCL, TWCU) to be executed after the postmodification mode has become effective. 85 HD404374/HD404384/HD404389/HD404082 Series Timer mode register C1 (TMC1: $014) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 TMC13 TMC12 TMC11 TMC10 TMC12 TMC11 TMC10 Input clock period 0 2,048 tcyc 1 512 tcyc 0 128 tcyc 1 32 tcyc 0 8 tcyc 1 4 tcyc 0 2 tcyc Bit name 0 0 1 0 1 1 TMC13 1 Free-running/reload timer 0 Free-running timer 1 Reload timer Figure 45 Timer Mode Register C1 (TMC1) 86 Timer B overflow HD404374/HD404384/HD404389/HD404082 Series • Timer mode register C2 (TMC2: $015): Timer mode register C2 (TMC2) is a 1-bit write-only register, used to select the timer C output mode as shown in figure 46. Timer mode register C2 (TMC2) is reset to $0 by an MCU reset. Timer mode register C2 (TMC2: $015) Bit 3 2 1 0 Read/Write — W — — Initial value on reset — 0 — — Bit name — TMC22 — — TMC22 Timer C output waveform 0 Toggle output 1 PWM output Figure 46 Timer Mode Register C2 (TMC2) • Timer write register C (TWCL: $016, TWCU: $017): Timer write register C (TWCL, TWCU) is a write-only register composed of a lower digit (TWCL) and an upper digit (TWCU) (figures 47 and 48). Timer write register C (TWCL, TWCU) operation is similar to that for timer write register B (TWBL, TWBU). Timer write register C (lower) (TWCL: $016) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 TWCL3 TWCL2 TWCL1 TWCL0 Bit name Figure 47 Timer Write Register C (Lower) (TWCL) 87 HD404374/HD404384/HD404389/HD404082 Series Timer write register C (upper) (TWCU: $017) Bit 3 2 1 0 Read/Write W W W W Initial value on reset Bit name Undetermined Undetermined Undetermined Undetermined TWCU3 TWCU2 TWCU1 TWCU0 Figure 48 Timer Write Register C (Upper) (TWCU) • Timer read register C (TRCL: $016, TRCU: $017): Timer read register C (TRCL, TRCU) is a read-only register composed of a lower digit (TRCL) and an upper digit (TRCU) from which the value of the upper digit of timer C is read directly (figures 49 and 50). Timer read register C (TRCL, TRCU) operation is similar to that for timer read register B (TRBL, TRBU). Timer read register C (lower) (TRCL: $016) Bit 3 2 1 0 Read/Write R R R R Initial value on reset Bit name Undetermined Undetermined Undetermined Undetermined TRCL3 TRCL2 TRCL1 TRCL0 Figure 49 Timer Read Register C (Lower) (TRCL) Timer read register C (upper) (TRCU: $017) Bit 3 2 1 0 Read/Write R R R R Initial value on reset Bit name Undetermined Undetermined Undetermined Undetermined TRCU3 TRCU2 TRCU1 Figure 50 Timer Read Register C (Upper) (TRCU) 88 TRCU0 HD404374/HD404384/HD404389/HD404082 Series • Port mode register 3 (PMR3: $00B): Port mode register 3 (PMR3) is a write-only register used to set the function of the R20/TOC pin as shown in figure 51. Port mode register 3 (PMR3) is reset to $0 by an MCU reset. Port mode register 3 (PMR3: $00B) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 PMR33 PMR32 PMR31 PMR30 Bit name PMR30 R20/TOC pin mode selection 0 R20 1 TOC PMR31 R21/SCK pin mode selection 0 R21 1 SCK PMR33 PMR32 R22/SI/SO pin mode selection 0 ∗ R22 1 0 SI 1 SO ∗ : Don't care Figure 51 Port Mode Register 3 (PMR3) • Module standby register 1 (MSR1: $00D): Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the clock to timer C as shown in figure 43. Module standby register 1 (MSR1) is reset to $0 by an MCU reset. 89 HD404374/HD404384/HD404389/HD404082 Series Serial Interface The serial interface serially transfers and receives 8-bit data, and includes the following features. • Multiple transmit clock sources External clock Internal prescaler output clock System clock • Output level control in idle states Five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows. • • • • • • Serial data register (SRL: $026, SRU: $027) Serial mode register 1 (SMR1: $024) Serial mode register 2 (SMR2: $025) Port mode register 3 (PMR3: $00B) Octal counter (OC) Selector The block diagram of the serial interface is shown in figure 52. 90 HD404374/HD404384/HD404389/HD404082 Series Serial interrupt request flag (IFS) Octal counter (OC) Idle control logic SCK I/O control logic Serial data register (SRL/U) 1/2 Data bus Transfer control 2 1/2 Selector ÷2 ÷8 ÷32 ÷128 ÷512 ÷2048 Selector øPER PrescalerS (PSS) System clock Clock Internal data bus SI/SO 4 Serial mode register 1 (SMR1) Serial mode register 2 (SMR2) Clock line Signal line Figure 52 Serial Interface Block Diagram 91 HD404374/HD404384/HD404389/HD404082 Series Serial Interface Operation Selecting and changing serial interface operating mode: The operating modes that can be selected for the serial interface are shown in table 26. The combination of port mode register 3 (PMR3) values should be selected from this table. When the serial interface operating mode is changed, the serial interface internal state must be initialized by writing to serial mode register 1 (SMR1). Note : The serial interface is initialized by writing to serial mode register 1 (SMR1: $024). See figure 56 Serial Mode Register 1, for details. Table 26 Serial Interface Operating Modes PMR3 Bit3 Bit2 Bit1 Serial interface operating mode 0 * 1 Clock continuous output mode 1 0 1 Receive mode 1 1 1 Transmit mode Note : * Don't care Serial interface pin setting: The R2 1/SCK pin and R22/SI/SO pin are set by writing data to port mode register 3 (PMR3). See Serial Interface Registers, for details. Serial clock source setting: The serial clock is set by writing data to serial mode register 1 (SMR1). See Serial Interface Registers, for details. Serial data setting: Transmit serial data is set by writing data to the serial data register (SRL, SRU). Receive serial data is obtained by reading the serial data register (SRL, SRU). Serial data is shifted by means of the serial clock to perform input/output from/to an external device. The output level of the SO pin is undetermined until the first data is output after a reset by the MCU, or until high/low control is performed in the idle state. Transfer control: Serial interface operation is started by an STS instruction. The octal counter is reset to 000 by the STS instruction, and is incremented by 1 on each rise of the serial clock. When 8 serial clock pulses have been input, or if data transmission/reception is suspended midway, the octal counter is reset to 000, the serial interrupt request flag (IFS) is set, and transfer is terminated. The serial clock is selected by means of serial mode register 1 (SMR1). See figure 56. 92 HD404374/HD404384/HD404389/HD404082 Series Serial interface operating states: The serial interface has the operating states shown in figure 53 in external clock mode and internal clock mode. STS instruction wait state Serial clock wait state Transfer state Clock continuous output state (internal clock mode only) • STS instruction wait state Upon MCU reset ((00) and (10) in figure 53), the serial interface enters the STS instruction wait state. In the STS instruction wait state, the internal state of the serial interface is initialized. Even if the serial clock is input at this time, the serial interface will not operate. When the STS instruction is executed ((01), (11)), the serial interface enters the serial clock wait state. • Serial clock wait state The serial clock wait state is the interval from STS instruction execution until the first serial clock falling edge. When the serial clock is input in the serial clock wait state ((02), (12)), the octal counter begins counting, the contents of the serial data register (SRL, SRU) begin shifting, and the serial interface enters the transfer state. However, if clock continuous output mode is selected in internal clock mode, the serial interface enters the clock continuous output state ((17)) instead of the transfer state. If a write to serial mode register 1 (SMR1) is performed in the serial clock wait state, the serial interface enters the STS instruction wait state ((04), (14)). • Transfer state The transfer state is the interval from the first serial clock falling edge until the eighth serial clock rising edge. In the transfer state, if an STS instruction is executed or if eight serial clocks have been input, the octal counter is cleared to 000, and the serial interface makes a state transition. If an STS instruction is executed ((05), (15)), the serial interface enters the serial clock wait state. After eight serial clocks have been input, the serial interface enters the serial clock wait state ((03)) when in external clock mode, and enters the STS instruction wait state ((13)) when in internal clock mode. In internal clock mode, the serial clock stops after output of eight clocks. If a write to serial mode register 1 (SMR1) is performed in the transfer state ((06), (16)), the serial interface is initialized and enters the STS instruction wait state. When the serial interface switches from the transfer state to another state, the octal counter is reset to 000 and the serial interrupt request flag (IFS) is set. • Clock continuous output state (internal clock mode only) In the clock continuous output state, no receive or transmit operation is performed, and the serial clock is only output from the SCK pin. It is therefore effective in internal clock mode. If the serial clock is input ((17)) when bit 3 (PMR33) of port mode register 3 (PMR3) is cleared to 0 and the serial interface is in the serial clock wait state, a transition is made to the clock continuous output state. If a write to serial mode register 1 (SMR1) is performed in the clock continuous output state ((18)), the serial interface enters the STS instruction wait state. 93 HD404374/HD404384/HD404389/HD404082 Series STS instruction wait state MCU reset (00) (octal counter ="000", serial clock disabled) SMR1 write (04) SMR1 write (06) STS instruction (01) (IFS ← "1") Serial clock (02) Serial clock wait state Transfer state (octal counter ="000") (octal counter ≠"000") 8 serial clocks (03) STS instruction (05) (IFS ← "1") External clock mode STS instruction wait state MCU reset (10) (octal counter ="000", serial clock disabled) SMR1 write (18) 8 serial clocks (13) Clock continuous output state SMR1 write (16) (PMR33 ="0") (IFS←"1") SMR1 write (14) STS instruction (11) Serial clock (17) Serial clock (12) Transfer state Serial clock wait state (octal counter ≠"000") (octal counter ="000") STS instruction (15) (IFS←"1") Internal clock mode ( ) Refer to the text for details on the circled numbers in the figure. Figure 53 Serial Interface Operating States 94 HD404374/HD404384/HD404389/HD404082 Series Idle high/low control: When the serial interface is in the STS instruction wait state or the serial clock wait state (i.e. when idle), the output level of the SO pin can be set arbitrarily by software. Idle high/low control is performed by writing the output level to bit 1 (SMR21) of serial mode register 2 (SMR2). An example of idle high/low control is shown in figure 54. Idle high/low control cannot be performed in the transfer state. 95 HD404374/HD404384/HD404389/HD404082 Series Serial clock wait state Serial clock wait state State MCU reset PMR3 write Transfer state STS wait state STS wait state Port setting External clock setting SMR1 write Dummy write to cause state transition Idle H/L setting SMR2 write Idle H/L setting Transmit data write SRL, SRU write STS instruction SCK pin (input) SO pin Undefined Idle MSB LSB Idle IFS (Flag reset by transfer completion processing) (1) External clock mode Serial clock wait state State MCU reset PMR3 write STS wait state Transfer state STS wait state Port setting External clock setting SMR1 write Idle H/L setting SMR2 write Idle H/L setting Transmit data write SRL, SRU write STS instruction SCK pin (output) SO pin Undefined Idle LSB Idle MSB IFS (2) Internal clock mode (Flag reset by transfer completion processing) Figure 54 Examples of Serial Interface Operation Sequence 96 HD404374/HD404384/HD404389/HD404082 Series Serial clock error detection (external clock mode): The serial interface will operate incorrectly in the transfer state if external noise results in unnecessary pulses being added to the serial clock. Serial clock error detection in such cases is carried out as shown in figure 55. If more than eight serial clock pulses are input due to external noise while in the transfer state, at the eighth clock pulse (including any external noise pulses), the octal counter is cleared to 000 and the serial interrupt request flag (IFS) is set. At the same time, the serial interface exits the transfer state and enters the serial clock wait state, but returns to the transfer state at the next regular clock pulse falling edge. Meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial interrupt request flag is reset, and a dummy write is performed into serial mode register 1 (SMR1). The serial interface then returns to the STS wait state, and the serial interrupt request flag (IFS) is set again. It is therefore possible to detect a serial clock error by testing the serial interrupt request flag after the dummy write to serial mode register 1. Usage notes: • Initialization after register modification If a port mode register 3 (PMR3) write is performed in the serial clock wait state or transfer state, a serial mode register 1 (SMR1) write should be performed again to initialize the serial interface. • Serial interrupt request flag (IFS:$023, 2) setting If a serial mode register 1 (SMR1) write or STS instruction is executed during the first low-level interval of the serial clock in the transfer state, the serial interrupt request flag (IFS) will not be set. To ensure that the serial interrupt request flag (IFS) is properly set in this case, programming is required to make sure that the SCK pin is in the 1 state (by executing an input instruction for the R2 port) before executing a serial mode register 1 (SMR1) write or an STS instruction. 97 HD404374/HD404384/HD404389/HD404082 Series Transfer end (IFS←"1") Disable interrupts IFS←"0" SMR1 write Yes Serial clock error processing IFS=1? No Normal termination (1) Serial clock error detection flowchart Serial clock wait state Serial clock wait state Transfer state Transfer state State SCK pin (input) (Noise) 1 2 3 4 5 6 7 8 Because the serial interface returns to the transfer state, a write to SMR1 resets IFS. SMR1 write IFS Flag set by octal counter reaching 000 (2) Serial clock error detection sequence Figure 55 Example of Serial Clock Error Detection 98 Flag reset by transfer end processing HD404374/HD404384/HD404389/HD404082 Series Serial Interface Registers Serial interface operation setting and serial data reading/writing is controlled by the following registers. Serial mode register 1 (SMR1: $024) Serial mode register 2 (SMR2: $025) Serial data register (SRL: $026, SRU: $027) Port mode register 3 (PMR3: $00B) Module standby register 2 (MSR2: $00E) Serial mode register 1 (SMR1: $024): Serial mode register 1 (SMR1) has the following functions. See figure 56. • Serial clock selection • Prescaler division ratio selection • Serial interface initialization The serial mode register 1 (SMR1) is a 4-bit write-only register, and is reset to $0 by an MCU reset. A write to serial mode register 1 (SMR1) halts the supply of the serial clock to the serial data register (SRL, SRU) and the octal counter, and resets the octal counter to 000. Therefore, if serial mode register 1 (SMR1) is written to during serial interface operation, data transmission/reception will be suspended and the serial interrupt request flag (IFS) will be set. A modification of serial mode register 1 (SMR1) becomes effective after execution of two instructions following the serial mode register 1 (SMR1) write instruction. The program must therefore provide for the STS instruction to be executed two cycles after the instruction that writes to serial mode register 1 (SMR1). 99 HD404374/HD404384/HD404389/HD404082 Series Serial mode register 1 (SMR1: $024) Bit 3 2 1 0 Read/Write W W W W 0 0 0 0 Initial value on reset Bit name SMR13 SMR12 SMR11 SMR10 SMR13 SMR12 SMR11 SMR10 0 Output PSS (øPER/2048)÷2 4096 tcyc 1 Output PSS (øPER/512)÷2 1024 tcyc 0 Output PSS (øPER/128)÷2 256 tcyc 1 Output PSS (øPER/32)÷2 64 tcyc 0 Output PSS (øPER/8)÷2 16 tcyc 1 Output PSS (øPER/2)÷2 4 tcyc 0 Output System clock øPER 1 Input External clock 0 Output PSS (øPER/2048)÷4 8192 tcyc 1 Output PSS (øPER/512)÷4 2048 tcyc 0 Output PSS (øPER/128)÷4 512 tcyc 128 tcyc 0 0 1 0 0 1 1 0 0 1 1 0 1 1 Serial clock Serial clock SCK pin Serial clock source (PSS division ratio ÷ 2 or 4) cycle tcyc 1 Output PSS (øPER/32)÷4 0 Output PSS (øPER/8)÷4 32 tcyc 8 tcyc 1 Output PSS (øPER/2)÷4 0 Output System clock øPER 1 Input External clock tcyc Figure 56 Serial Mode Register 1 (SMR1) Serial mode register 2 (SMR2: $025): Serial mode register 2 (SMR2) has the following functions. See figure 57. • R2 2/SI/SO pin PMOS control • Idle high/low control Serial mode register 2 (SMR2) is a 2-bit write-only register. The register value cannot be modified in the transfer state. Bit 2 (SMR22) of serial mode register 2 (SMR2) controls the on/off status of the R22/SI/SO pin PMOS. The bit 2 (SMR22) only is reset to 0 by an MCU reset. 100 HD404374/HD404384/HD404389/HD404082 Series Bit 1 (SMR21) of serial mode register 2 (SMR2) performs SO pin high/low control in the idle state. The SO pin changes at the same time as the high/low write. Serial mode register 2 (SMR2: $025) Bit 3 2 1 0 Read/Write — W W — Initial value on reset — 0 undeternined — Bit name — SMR22 SMR21 SMR21 SMR22 Idle high/low control 0 SO pin set to low-level output in idle state 1 SO pin set to high-level output in idle state R22/SI/SO pin output buffer control 0 PMOS active 1 PMOS off (NMOS open-drain output) Figure 57 Serial Mode Register 2 (SMR2) Serial data register (SRL: $026, SRU: $027): The serial data register (SRL, SRU) has the following functions. See figures 58 and 59. • Transmit data write and shift operations • Receive data shift and read operations The data written to the serial data register (SRL, SRU) is output LSB-first from the SO pin in synchronization with the falling edge of the serial clock. External data input LSB-first from the SI pin is latched in synchronization with the rising edge of the serial clock. Figure 60 shows the serial clock and data input/output timing chart. Writing and reading of the serial data register (SRL, SRU) must be performed only after data transmission/reception is completed. The data contents are not guaranteed if a read or write is performed during data transmission or reception. 101 HD404374/HD404384/HD404389/HD404082 Series Serial data register (lower) (SRL: $026) Bit Read/Write 3 2 1 0 R/W R/W R/W R/W Initial value on reset Undetermined Undetermined Undetermined Undetermined SR3 Bit name SR2 SR1 SR0 Figure 58 Serial Data Register (SRL) Serial data register (upper) (SRU: $027) Bit Read/Write 3 2 1 0 R/W R/W R/W R/W Initial value on reset Undetermined Undetermined Undetermined Undetermined Bit name SR7 SR6 SR5 SR4 Figure 59 Serial Data Register (SRU) Serial clock 1 Serial output 2 3 4 5 6 7 LSB data Serial input data latch timing Figure 60 Serial Interface Input/Output Timing Chart 102 8 MSB HD404374/HD404384/HD404389/HD404082 Series Port mode register 3 (PMR3: $00B): Port mode register 3 (PMR3) has the following functions. See figure 61. • R2 1/SCK pin selection • R2 2/SI/SO pin selection Port mode register 3 (PMR3) is a 4-bit write-only register used to select serial interface pin settings as shown in figure 61. It is reset to $0 by an MCU reset. Port mode register 3 (PMR3: $00B) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 Bit name PMR33 PMR32 PMR31 PMR30 PMR30 R20/TOC pin mode selection 0 R20 1 TOC PMR31 R21/SCK pin mode selection 0 R21 1 SCK PMR33 PMR32 R22/SI/SO pin mode selection 0 1 ∗ R22 0 SI 1 SO ∗ : Don't care Figure 61 Port Mode Register 3 (PMR3) 103 HD404374/HD404384/HD404389/HD404082 Series Module standby register 2 (MSR2: $00E): Module standby register 2 (MSR2) is a write-only register used to designate supply or stopping of the clock to the serial interface as shown in figure 62. Module standby register 2 (MSR2) is reset to $0 by an MCU reset. Module standby register 2 (MSR2: $00E) Bit 3 2 1 0 Read/Write — — W W Initial value on reset — — 0 0 Bit name — — MSR21 MSR20 MSR20 Serial clock supply control 0 Supplied 1 Stopped MSR21 A/D clock supply control 0 Supplied 1 Stopped Figure 62 Module Standby Register 2 (MSR2) 104 HD404374/HD404384/HD404389/HD404082 Series A/D Converter (HD404374/HD404384/HD404389 Series) The MCU has a built-in successive approximation type A/D converter using a resistance ladder method, capable of digital conversion of four analog inputs with an 10-bit resolution. The A/D converter block diagram is shown in figure 63. The A/D converter comprises the following four registers. • • • • A/D mode register (AMR: $028) A/D start flag (ADSF: $020,2) A/D data register (ADRL: $029, ADRM: $02A, ADRU: $02B) Module standby register 2 (MSR2: $00E) Note : With the HD404374, HD404384, and HD404389 Series emulator, write 1 to bit 0 (ADRL0) of A/D data register-lower (ADRL). This bit need not be written in the mask ROM and ZTATTM versions in these series, although writing 1 will have no effect. Interrupt flag (IFAD) A/D data register (ADRU, ADRM, ADRL) Encoder A/D mode register (AMR) Selector R70/AN0 R71/AN1 R72/AN2 R73/AN3 *AN4 *AN5 + COMP Reference voltage – AVCC Reference voltage control A/D control logic Internal data bus 3 Conversion time control A/D start flag (ADSF) Operating mode signal (set to 1 in stop, watch, and subactive modes, and during module standby) AVSS D/A Note: * Applies to HD404389 Series. Figure 63 A/D Converter Block Diagram 105 HD404374/HD404384/HD404389/HD404082 Series A/D mode register (AMR: $028): The A/D mode register is a 4-bit write-only register that shows the A/D converter speed setting and information on the analog input pin specification. The A/D conversion time is selected by bit 0, and the channel by bits 1, 2, and 3 (figure 64). A/D start flag (ADSF: $020,2): A/D conversion is started by writing 1 to the A/D start flag. When conversion ends, the converted data is placed in the A/D data register and the A/D start flag is cleared at the same time. (figure 65). A/D mode register (AMR: $028) Bit 3 2 1 0 Read/Write W W W W Initial value on reset Bit name 0 0 0 0 AMR3 AMR2 AMR1 AMR0 AMR0 A/D conversion time 0 65 tcyc 1 125 tcyc AMR3 AMR2 AMR1 Analog input channel selection 0 0 1 0 1 1 — No selection 0 AN0 1 AN1 0 AN2 1 AN3 0 AN4* 1 AN5* Note: * Applies to the HD404389 series. This selection is not available on the HD 404374 and HD404384 series. Figure 64 A/D Mode Register (AMR) 106 HD404374/HD404384/HD404389/HD404082 Series A/D start flag (ADSF: $020,2) Bit Read/Write Initial value on reset Bit name 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 DTON ADSF WDON LSON LSON (see low-power mode section) WDON (see timer section) A/D start flag (ADSF) 1 A/D conversion starts 0 Indicates end of A/D conversion DTON (see low-power mode section) Figure 65 A/D Start Flag (ADSF) A/D data register (ADRL: $029, ADRM: $02A, ADRU: $02B): The A/D data register is a read-only register consisting of a middle 4 bits and lower 2 bits. This register is not cleared by a reset. Also, data read during A/D conversion is not guaranteed. At the end of A/D conversion, the resulting 10-bit data is stored in this register, and is held until the next conversion operation starts (figures 66, 67, 68, and 69). ADRU : $02B 3 2 1 ADRM : $02A 0 3 2 1 ADRL : $029 0 3 2 MSB LSB bit9 bit0 Figure 66 A/D Data Register 107 HD404374/HD404384/HD404389/HD404082 Series A/D data register-lower (ADRL: $029) Bit 3 2 1 0 Read/Write R R — — Initial value on reset 1 1 — —* ADRL3 ADRL2 Not used Not used Bit name Note: * Should be written with 1 with the emulator. Figure 67 A/D Data Register-Lower (ADRL) A/D data register-middle (ADRM: $02A) Bit 3 2 1 0 Read/Write R R R R Initial value on reset 1 1 1 1 ADRM3 ADRM2 ADRM1 ADRM0 Bit name Figure 68 A/D Data Register-Middle (ADRM) A/D data register-upper (ADRU: $02B) Bit 3 2 1 0 Read/Write R R R R Initial value on reset 0 1 1 1 ADRU2 ADRU1 ADRU0 Bit name ADRU3 Figure 69 A/D Data Register-Upper (ADRU) Module standby register 2 (MSR2: $00E): Writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the A/D module and cuts the current (IAD ) flowing in the ladder resistor. Usage notes: • Use the SEM or SEMD instruction to write to the A/D start flag (ADSF). • Do not write to the ADSF during A/D conversion. • Data in the A/D data register is undetermined during A/D conversion. 108 HD404374/HD404384/HD404389/HD404082 Series • As the A/D converter operates on a clock from OSC, it stops in stop mode, watch mode, and subactive mode. The current flowing in the A/D converter ladder resistor is also cut in these low-power modes to reduce power consumption. • When an analog input pin is selected by the A/D mode register, the pull-up MOS for that pin is disabled. • Use of bit 0 of A/D data register-lower (ADRL) is prohibited, but with the emulator it should be written with 1. This bit need not be written in the mask ROM and ZTATTM versions, although writing 1 will have no effect. 109 HD404374/HD404384/HD404389/HD404082 Series ZTATTM Microcomputer with Built-in Programmable ROM Precautions for use of ZTATTM microcomputer with built-in programmable ROM (1) Precautions for writing to programmable ROM built in ZTATTM microcomputer In the ZTAT TM microcomputer with built-in plastic mold one-time programmable ROM, incomplete electrical connection between the PROM writer and socket adapter causes writing errors and, makes the computer unoperatable. To enhance the writing efficiency, attention should be paid to the following points: (a) Make sure that the socket adapter is firmly fixed to the PROM writer and connected electrically with each other (neither opened nor shorted), before starting the writing process. (b) To secure the electrical connection between the contact pin and IC lead, make sure that there is no foreign substance on the contact pin of the socket adapter, which may cause improper electrical connection. (c) When inserting the IC, be careful to protect the IC lead from bending in order to secure the electrical connection between the contact pin and IC lead. If the lead is bent, correct the bending and insert it again. (d) If any trouble is noticed during a blank check to be performed to prevent erroneous writing due to improper electrical connection, carry out the writing process again according to above steps (a), (b), and (c). (e) During the writing process, do not touch the socket adapter and IC to prevent erroneous writing. (f) To write continuously in the IC, follow steps (a), (b), (c), (d) and (e). (g) If a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the PROM writer, socket adapter, etc. for defects. (h) If any problem is noticed in the written program or in the program after being left at a high temperature, consult our technical staff. (2) Precautions when new PROM writer, socket adapter or IC is used When a new PROM writer, socket adapter or IC is employed, breakdown of the IC may occur or its writing may become impossible because the noise, overshoot, timing or other electrical characteristics may be inconsistent with the assured IC writing characteristics. To avoid such troubles, check the following points before starting the writing process. (a) To ensure stable writing operation, check that the VCC of the power supplied to the PROM writer, power source current capacity of VPP, and current consumption at the time of writing to IC are provided with sufficient margin. (b) To prevent breakdown of the IC, check that the power source voltage between GND-V CC and GNDVPP, and overshoot or undershoot of the power source at the connecting terminal of the socket adapter are within the ratings. Particularly, if the overshoot or undershoot exceeds the maximum rating, the p-n connection may be damaged, leading to permanent breakdown. If overshoot or undershoot occurs, recheck the power source damping resistance of capacity. (c) To prevent breakdown of the IC and for stable writing and reading operation, insert the IC into the socket adapter and check the power noise between the GND-VCC and GND-VPP near the IC connecting 110 HD404374/HD404384/HD404389/HD404082 Series terminal. If power source noise is noticed, insert an appropriate capacitor between the GND power sources depending on the noise generated. In case of high frequency noise , insert a capacitor of low inductance. (d) For stable writing and reading operation, insert the IC into the socket adapter and check the input waveform, timing and noise near the R/W, CS, address and data terminals. Particularly, since recent ICs have increased in speed, caution should be exercised against the noise to the power source or address due to crosstalk from the output data terminal. To avoid these problems, inserting a low inductance capacitor between the GND and power source or inserting a damping resistance to the output data terminal is effective. (e) Particularly, when a multiple PROM writer is used, perform above items (a), (b), (c), and (d) assuming all ICs inserted into the socket adapter. (f) In the case of a multiple PROM writer, when an unacceptable result is noticed during a blank check performed to prevent erroneous writing due to improper electrical connection of the power source, etc., rewriting is impossible unless every writing process can be stopped. Therefore, the potential increases due to erroneous writing because of improper connection. Be sure to check the electrical connection between the PROM writer and socket adapter and IC. (g) If any abnormality is noticed while checking a written program, consult our technical staff. Programming of Built-in programmable ROM The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM. PROM mode is set up by setting the RESET and MO terminals to “Low” level and the TEST terminal to “Vpp” level. Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256. Using a socket adapter for specific use of each product, programming is possible with a general-purpose PROM writer. Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to write to a 16kword of built-in PROM writer with a general-purpose PROM, specify 32kbyte address ($0000-$7FFF). An example of PROM memory map is shown in figure 70. Notes: 1. When programming with a PROM writer, set up each ROM size to the address given in table 29. If it is programmed erroneously to an address given in table 29 or later, check of writing of PROM may become impossible. Particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. Set the data in unused addresses to $FF. 2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. Be sure to check that they are properly set to the writer before starting the writing process. 111 HD404374/HD404384/HD404389/HD404082 Series 3. Two levels of program voltages (VPP) are available for the PROM: 12.5V and 21V. Our product employs a V PP of 12.5V. If a voltage of 21V is applied, permanent breakdown of the product will result. The VPP of 12.5V is obtained for the PROM writer by setting it according to the Intel 27258 specifications. Table 27 Socket Adapters Package Model Name Manufacturer FP-30D Please ask Hitachi service section. DP-28S Please ask Hitachi service section. Writing/Verification Programming of the built-in program ROM employs a high speed programming method. With this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. A basic programming flow chart is shown in figure 71 and a timing chart in figure 72. For precautions for PROM writing procedure, refer to “Precautions for use of ZTATTM microcomputer with build-in programmable ROM”. Table 28 Selection of Mode Mode CE OE VPP O0 to O4 Writing “Low” “High” VPP Data input Verification “High” “Low” VPP Data output Prohibition of programming “High” “High” VPP High impedance Table 29 PROM Writer Program Address ROM size Address 2k $0000~$0FFF 4k $0000~$1FFF 8k $0000~$3FFF 16k $0000~$7FFF 112 HD404374/HD404384/HD404389/HD404082 Series Programmable ROM The HD407A4374/HD407C4374/HD407A4384/HD407C4384, HD407A4389/HD407C4389 are ZTATTM microcomputers with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description (1) HD407A4374/HD407C4374/HD407A4384/HD407C4384 Pin No. MCU Mode PROM Mode. FP-30D DP-28S Pin name I/O Pin name I/O 1 1 GND — GND — 2 2 VCC — VCC — 3 3 AVCC — VCC — 4 4 R7 0/AN0 I/O O0 I/O 5 5 R7 1/AN1 I/O O1 I/O 6 6 R7 2/AN2 I/O O2 I/O 7 7 R7 3/AN3 I/O O3 I/O 8 8 AVSS — GND — 9 9 OSC 1 I A0 I 10 10 OSC 2 O — — 11 11 TEST I VPP — 12 — X2 O — — 13 — X1 I GND — 14 12 RESET I RESET I 15 13 R0 0/WU0 I/O A1 I 16 14 R1 0/EVNB I/O A2 I 17 15 R1 3/TOB I/O O4 I/O 18 16 R2 0/TOC I/O CE I 19 17 R2 1/SCK I/O A2 I 20 18 R2 2/SI/SO I/O A3 I 21 19 D0/INT0 I/O MO I 22 20 D1 I/O A5 I 23 21 D2 I/O A6 I 24 22 D3 I/O A7 I 25 23 D4 I/O A8 I 26 24 D5 I/O A9 I 27 25 D6 I/O A10 I 28 26 D7 I/O A11 I 29 27 D8 I/O A12 I 30 28 D9 I/O OE I 113 HD404374/HD404384/HD404389/HD404082 Series (2) HD407A4389 /HD407C4389 Pin No. MCU Mode FP-30D Pin name I/O Pin name I/O 1 GND — GND — 2 VCC — VCC — 3 AVCC — VCC — 4 R7 0/AN0 I/O O0 I/O 5 R7 1/AN1 I/O O1 I/O 6 R7 2/AN2 I/O O2 I/O 7 R7 3/AN3 I/O O3 I/O 8 AN 4 I CE I 9 AN 5 I OE I 10 AVSS — GND 11 TEST I VPP — 12 OSC 1 I A0 I 13 OSC 2 O — — 14 RESET I RESET I 15 R0 0/WU0 I/O A1 I 16 R1 0/EVNB I/O A4 I 17 R1 3/TOB I/O O4 I/O 18 R2 0/TOC I/O A14 I 19 R2 1/SCK I/O A2 I 20 R2 2/SI/SO I/O A3 I 21 D0/INT0 I/O MO I 22 D1 I/O A5 I 23 D2 I/O A6 I 24 D3 I/O A7 I 25 D4 I/O A8 I 26 D5 I/O A9 I 27 D6 I/O A10 I 28 D7 I/O A11 I 29 D8 I/O A12 I D9 I/O A13 I 30 Note: 114 PROM Mode. I/O: I/O pin, I: Input-only pin, O: Output-only pin HD404374/HD404384/HD404389/HD404082 Series 1. Unused data pins (O 5 to O 7) on the PROM programmer side should be handled as shown below on the socket. VCC O5, O6, O7 2. Pin A 9 should be handled as shown below on the socket. VCC A9 HD407A4374 HD407C4374 HD407A4384 HD407C4384 HD407A4389 HD407C4389 Writer side 115 HD404374/HD404384/HD404389/HD404082 Series Pin Functions in PROM Mode VPP: Applies the on-chip PROM programming voltage (12.5 V ±0.3 V). CE: Inputs a control signal to set the on-chip PROM to the write/verify enabled state. OE: Inputs a data output control signal during verification. A0 to A14: On-chip PROM address input pins. O0 to O4: On-chip PROM data bus I/O pins. MO, RESET, TEST: PROM mode setting pins. PROM mode is set by driving the RESET, and MO pins low, and driving the TEST pin to the VPP level. Other pins: VCC and AVCC should be connected to VCC potential. GND, AVSS, and X1 should be connected to GND potential. Other pins should be left open. 116 HD404374/HD404384/HD404389/HD404082 Series $0000 $0001 . . . $001F $0020 . . . $007F $0080 . . . 1 1 1 1 1 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Lower 5 bits Upper 5 bits $0000 Vector address $000F $0010 JMPL instruction (jump to RESET routine) JMPL instruction (jump to WU0 routine) JMPL instruction (jump to INT0 routine) Zero-page subroutine (64 words) $003F $0040 Pattern (4,096 words) $07FF $0800 $1FFF $2000 JMPL instruction (jump to timer A routine) JMPL instruction (jump to timer B routine) JMPL instruction (jump to timer C routine) JMPL instruction (jump to A/D, serial routine) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F Program (16,384 words) $3FFF $7FFF Upper three bits are not to be used (fill them with 111) Figure 70 Memory Map in PROM Mode 117 HD404374/HD404384/HD404389/HD404082 Series Start Set Prog./Verify Mode VPP=12.5±0.3V, VCC=6.0±0.25V Address=0 n=0 Yes n+1→n No Program tPW = 1ms±5% n<S S=25 NoGo Verify Go Program tOPW = 3nms Last Address? No Yes Set Read Mode VCC=5.0±0.5V, VPP=VCC±0.6V NoGo Read All Address Go Fail End Figure 71 Flowchart of High-Speed Programming 118 Address + 1→Address HD404374/HD404384/HD404389/HD404082 Series Programming Electrical Characteristics DC Characteristics (V CC = 6V ±0.25V, VPP = 12.5V ±0.3V, V SS = 0V, T a = 25°C ±5°C, unless otherwise specified) Item Symbol Test Conditions min typ max Unit Input high voltage O0 to O 4,A 0 to A 14 , VIH OE, CE 2.2 — VCC+0.3 V Input low voltage O0 to O 4,A 0 to A 14 , VIL OE, CE –0.3 — 0.8 V Output high voltage O0 to O 4 VOH I OH=–200µA 2.4 — — V Output low voltage O0 to O 4 VOL I OL =1.6mA — — 0.4 V Vin=5.25V/0.5V — — 2 µA Input leakage current O0 to O 4,A 0 to A 14 , IIL OE, CE VCC current I CC — — 30 mA VPP current I PP — — 40 mA AC Characteristics (V CC = 6V ±0.25V, VPP = 12.5V ±0.3V, Ta = 25°C ±5°C, unless otherwise specified) Item Symbol Address setup time Test Conditions min typ max Unit t AS 2 — — µs OE setup time t OES 2 — — µs Data setup time t DS 2 — — µs Address hold time t AH 0 — — µs Data hold time t DH 2 — — µs Data output disable time t DF — — 130 ns VPP setup time t VPS 2 — — µs Program pulse width t PW 0.95 1.0 1.05 ms CE pulse width during overprogramming t OPW 2.85 — 78.75 ms VCC setup time t VCS 2 — — µs Data output delay time t OE 0 — 500 ns See figure 72 Notes: Input pulse level: 0.8 V to 2.2 V Input rise/fall times: ≤ 20ns Input timing reference levels: 1.0 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V 119 HD404374/HD404384/HD404389/HD404082 Series Write Verify Address tAH tAS Data Data In Stable tDS VPP VPP VCC VCC VCC GND Data Out Valid tDF tDH tVPS tVCS CE tPW OE tOES tOPW Figure 72 PROM Write/Verify Timing 120 tOE HD404374/HD404384/HD404389/HD404082 Series Notes on PROM Programming Principles of Programming/Erasure: A memory cell in a ZTAT™ microcomputer is the same as an EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an SiO 2 film. The change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 73). The charge in a memory cell may decrease with time. This decrease is usually due to one of the following causes: • Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure principle. • Heat excites trapped electrons, allowing them to escape. • High voltages between the control gate and drain may erase electrons. If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However, electron erasure does not often occur because defective devices are detected and removed at the testing stage. Control gate Control gate SiO2 SiO2 Floating gate Floating gate Drain Source N+ N+ Write (0) Drain Source N+ N+ Erasure (1) Figure 73 Cross-Sections of a PROM Cell PROM Programming: PROM memory cells must be programmed under specific voltage and timing conditions. The higher the programming voltage VPP and the longer the programming pulse t PW is applied, the more electrons are injected into the floating gates. However, if V PP exceeds specifications, the pn junctions may be permanently damaged. Pay particular attention to overshooting in the PROM programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. The ZTAT™ microcomputer is electrically connected to the PROM programmer by a socket adapter. Therefore, note the following points: • Check that the socket adapter is firmly mounted on the PROM programmer. • Do not touch the socket adapter or the LSI during the programming. Touching them may affect the quality of the contacts, which will cause programming errors. 121 HD404374/HD404384/HD404389/HD404082 Series PROM Reliability after Programming: In general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. These initial defects can be detected and rejected by screening. Baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure section.) ZTAT™ microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but Hitachi recommends that each device be exposed to 150°C at one atmosphere for at least 48 hours after it is programmed, to ensure its best performance. The recommended screening procedure is shown in figure 74. Note: If programming errors occur continuously during PROM programming, suspend programming and check for problems in the PROM programmer or socket adapter. If programming verification indicates errors in programming or after high-temperature exposure, please inform Hitachi. Programming, verification Exposure to high temperature, without power 150°C ± 10°C, 48 h +8 h * –0 h Program read check VCC = 4.5 V or 5.5 V Note: Exposure time is measured from when the temperature in the heater reaches 150°C. Figure 74 Recommended Screening Procedure Programming percentage: Programming percentage is guarenteed to more than 95%. 122 HD404374/HD404384/HD404389/HD404082 Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 75 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. W register W1 W0 RAM address X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Register Indirect Addressing 1st word of Instruction Opcode 2nd word of Instruction d RAM address 9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Direct Addressing Instruction Opcode 0 RAM address 0 0 1 m3 m2 0 m1 m0 0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Memory Register Addressing Figure 75 RAM Addressing Modes 123 HD404374/HD404384/HD404389/HD404082 Series ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 76 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13–PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 78. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross assembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000– $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight highorder bits (PC13–PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 77. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. Branch Destination of BR Instruction on Page Boundary: If a BR instruction is located on a page boundary (256n + 255), because of the hardware architecture the program counter contents will shift to the next page when that instruction is executed. When using a BR instruction on a page boundary, therefore, the branch destination must be set within the next page (see figure 78). The HMCS400-series cross assembler has an automatic paging feature for ROM pages, regardless of the model. 124 HD404374/HD404384/HD404389/HD404082 Series 1st word of instruction [JMPL] [BRL] [CALL] Opcode p3 Program counter 2nd word of instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Program counter Opcode b7 b6 b5 b4 b3 b2 b1 b0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 Program counter 0 0 0 d5 Opcode 0 0 0 d4 d3 d2 d1 d0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 0 Program counter B2 B1 Accumulator B0 A3 A2 A1 A0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 76 ROM Addressing Modes 125 HD404374/HD404384/HD404389/HD404082 Series Instruction [P] Opcode p3 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register B3 B2 B1 B0 A3 A 2 A1 A 0 If RO 8 = 1 Note: Designate RO9 as 0. Cannot assign pattern output to port R. Figure 77 P Instruction 256 (n – 1) + 255 BR AAA 256n AAA BBB 256n + 254 256n + 255 256 (n + 1) NOP BR BR BBB AAA NOP Figure 78 Branching when the Branch Destination is on a Page Boundary 126 HD404374/HD404384/HD404389/HD404082 Series Instruction Set The MCU Series has 101 instructions, classified into the following 10 groups: • • • • • • • • • • Immediate instructions Register-to-register instructions RAM addressing instructions RAM register instructions Arithmetic instructions Compare instructions RAM bit manipulation instructions ROM addressing instructions Input/output instructions Control instructions The functions of these instructions are listed in tables 30 to 39, and an opcode map is shown in table 40. Table 30 Immediate Instructions Status Words/ Cycles Operation Mnemonic Operation Code Function Load A from immediate LAI i 1 0 0 0 1 1 i3 i2 i1 i0 i→A 1/1 Load B from immediate LBI i 1 0 0 0 0 0 i3 i2 i1 i0 i→B 1/1 Load memory from immediate LMID i,d 0 1 1 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i→M 2/2 Load memory from immediate, increment Y LMIIY i 1 0 1 0 0 1 i3 i2 i1 i0 i → M, Y + 1 → Y NZ 1/1 127 HD404374/HD404384/HD404389/HD404082 Series Table 31 Register-Register Instructions Mnemonic Operation Code Function Load A from B LAB 0 0 0 1 0 0 1 0 0 0 B→A 1/1 Load B from A LBA 0 0 1 1 0 0 1 0 0 0 A→B 1/1 Load A from W LAW 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W→A 2/2* Load A from Y LAY 0 0 1 0 1 0 1 1 1 1 Y→A 1/1 Load A from SPX LASPX 0 0 0 1 1 0 1 0 0 0 SPX → A 1/1 Load A from SPY LASPY 0 0 0 1 0 1 1 0 0 0 SPY → A 1/1 Load A from MR LAMR m 1 0 0 1 1 1 m3 m2 m1 m0 MR (m) → A 1/1 Exchange MR and A XMRA m 1 0 1 1 1 1 m3 m2 m1 m0 MR (m) ↔ A 1/1 Note: Status Words/ Cycles Operation The assembler automatically provides an operand for the second word of the LAW instruction. Table 32 RAM Address Instructions Operation Mnemonic Operation Code Function Load W from immediate LWI i 0 0 1 1 1 1 0 0 i1 i0 i→W 1/1 Load X from immediate LXI i 1 0 0 0 1 0 i3 i2 i1 i0 i→X 1/1 Load Y from immediate LYI i 1 0 0 0 0 1 i3 i2 i1 i0 i→Y 1/1 Load W from A LWA* 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A→W 2/2* Load X from A LXA 0 0 1 1 1 0 1 0 0 0 A→X 1/1 Load Y from A LYA 0 0 1 1 0 1 1 0 0 0 A→Y 1/1 Increment Y IY 0 0 0 1 0 1 1 1 0 0 Y+1→Y NZ 1/1 Decrement Y DY 0 0 1 1 0 1 1 1 1 1 Y–1→Y NB 1/1 Add A to Y AYY 0 0 0 1 0 1 0 1 0 0 Y+A→Y OVF 1/1 Subtract A from Y SYY 0 0 1 1 0 1 0 1 0 0 Y–A→Y NB 1/1 Exchange X and SPX XSPX 0 0 0 0 0 0 0 0 0 1 X ↔ SPX 1/1 Exchange Y and SPY XSPY 0 0 0 0 0 0 0 0 1 0 Y ↔ SPY 1/1 Exchange X and SPX, Y and SPY XSPXY 0 0 0 0 0 0 0 0 1 1 X ↔ SPX,Y ↔ SPY 1/1 Status Words/ Cycles Note: * The assembler automatically provides an operand for the second word of the LAW and LWA instruction. 128 HD404374/HD404384/HD404389/HD404082 Series Table 33 RAM Register Instructions Mnemonic Operation Code Function Load A from memory LAM 0 0 1 0 0 1 0 0 0 0 M→A LAMX 0 0 1 0 0 1 0 0 0 1 M→A X ↔ SPX LAMY 0 0 1 0 0 1 0 0 1 0 M→A Y ↔ SPY LAMXY 0 0 1 0 0 1 0 0 1 1 M→A X ↔ SPX, Y ↔ SPY Load A from memory LAMD d 0 1 1 0 0 1 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M→A 2/2 Load B from memory LBM 0 0 0 1 0 0 0 0 0 0 M→B 1/1 LBMX 0 0 0 1 0 0 0 0 0 1 M→B X ↔ SPX LBMY 0 0 0 1 0 0 0 0 1 0 M→B Y ↔ SPY LBMXY 0 0 0 1 0 0 0 0 1 1 M→B X ↔ SPX, Y ↔ SPY LMA 0 0 1 0 0 1 0 1 0 0 A→M LMAX 0 0 1 0 0 1 0 1 0 1 A→M X ↔ SPX LMAY 0 0 1 0 0 1 0 1 1 0 A→M Y ↔ SPY LMAXY 0 0 1 0 0 1 0 1 1 1 A→M X ↔ SPX, Y ↔ SPY Load memory from A LMAD d 0 1 1 0 0 1 0 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A→M Load memory from A, increment Y LMAIY 0 0 0 1 0 1 0 0 0 0 A → M, Y + 1 → Y LMAIYX 0 0 0 1 0 1 0 0 0 1 A → M, Y + 1 → Y X ↔ SPX LMADY 0 0 1 1 0 1 0 0 0 0 A → M, Y – 1 → Y LMADYX 0 0 1 1 0 1 0 0 0 1 A → M, Y – 1 → Y X ↔ SPX Load memory from A Load memory from A, decrement Y Status Words/ Cycles Operation 1/1 1/1 2/2 NZ 1/1 NB 1/1 129 HD404374/HD404384/HD404389/HD404082 Series Table 33 RAM Register Instructions (cont) Mnemonic Operation Code Function Exchange memory and A XMA 0 0 1 0 0 0 0 0 0 0 M↔A XMAX 0 0 1 0 0 0 0 0 0 1 M↔A X ↔ SPX XMAY 0 0 1 0 0 0 0 0 1 0 M↔A Y ↔ SPY XMAXY 0 0 1 0 0 0 0 0 1 1 M↔A X ↔ SPX, Y ↔ SPY Exchange memory and A XMAD d 0 1 1 0 0 0 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M↔A 2/2 Exchange memory and B XMB 0 0 1 1 0 0 0 0 0 0 M↔B 1/1 XMBX 0 0 1 1 0 0 0 0 0 1 M↔B X ↔ SPX XMBY 0 0 1 1 0 0 0 0 1 0 M↔B Y ↔ SPY XMBXY 0 0 1 1 0 0 0 0 1 1 M↔B X ↔ SPX, Y ↔ SPY 130 Status Words/ Cycles Operation 1/1 HD404374/HD404384/HD404389/HD404082 Series Table 34 Arithmetic Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Add immediate to A AI i 1 0 1 0 0 0 i3 i2 i1 i0 A+i→A OVF 1/1 Increment B IB 0 0 0 1 0 0 1 1 0 0 B+1→B NZ 1/1 Decrement B DB 0 0 1 1 0 0 1 1 1 1 B–1→B NB 1/1 Decimal adjust for addition DAA 0 0 1 0 1 0 0 1 1 0 1/1 Decimal adjust for subtraction DAS 0 0 1 0 1 0 1 0 1 0 1/1 Negate A NEGA 0 0 0 1 1 0 0 0 0 0 A+1→A 1/1 Complement B COMB 0 1 0 1 0 0 0 0 0 0 B→ B 1/1 Rotate right A with carry ROTR 0 0 1 0 1 0 0 0 0 0 1/1 Rotate left A with carry ROTL 0 0 1 0 1 0 0 0 0 1 1/1 Set carry SEC 0 0 1 1 1 0 1 1 1 1 1 → CA 1/1 Reset carry REC 0 0 1 1 1 0 1 1 0 0 0 → CA 1/1 Test carry TC 0 0 0 1 1 0 1 1 1 1 Add A to memory AM 0 0 0 0 0 0 1 0 0 0 Add A to memory AMD d Add A to memory with carry CA 1/1 M+A→A OVF 1/1 0 1 0 0 0 0 1 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M+A→A OVF 2/2 AMC 0 0 0 0 0 1 1 0 0 0 M + A + CA → A OVF → CA OVF 1/1 Add A to memory with carry AMCD d 0 1 0 0 0 1 1 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M + A + CA → A OVF → CA OVF 2/2 Subtract A from memory with carry SMC 0 0 1 0 0 1 1 0 0 0 M – A – CA → A NB → CA NB 1/1 Subtract A from memory with carry SMCD d 0 1 1 0 0 1 1 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M – A – CA → A NB → CA NB 2/2 OR A and B OR 0 1 0 1 0 0 0 1 0 0 A∪B→A AND memory with A ANM 0 0 1 0 0 1 1 1 0 0 A∩M→A NZ 1/1 AND memory with A ANMD d 0 1 1 0 0 1 1 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A∩M→A NZ 2/2 OR memory with A ORM 0 0 0 0 0 0 1 1 0 0 A∪M→A NZ 1/1 OR memory with A ORMD d 0 1 0 0 0 0 1 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A∪M→A NZ 2/2 EOR memory with A EORM 0 0 0 0 0 1 1 1 0 0 A⊕M→A NZ 1/1 EOR memory with A EORMD d 0 1 0 0 0 1 1 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A⊕M→A NZ 2/2 1/1 131 HD404374/HD404384/HD404389/HD404082 Series Table 35 Compare Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Immediate not equal to memory INEM i 0 0 0 0 1 0 i3 i2 i1 i0 i≠M NZ 1/1 Immediate not equal to memory INEMD i,d 0 1 0 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i≠M NZ 2/2 A not equal to memory ANEM 0 0 0 0 0 0 0 1 0 0 A≠M NZ 1/1 A not equal to memory ANEMD d 0 1 0 0 0 0 0 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A≠M NZ 2/2 B not equal to memory BNEM 0 0 0 1 0 0 0 1 0 0 B≠M NZ 1/1 Y not equal to immediate YNEI i 0 0 0 1 1 1 i3 i2 i1 i0 Y≠i NZ 1/1 Immediate less than or equal to memory ILEM i 0 0 0 0 1 1 i3 i2 i1 i0 i≤M NB 1/1 Immediate less than or equal to memory ILEMD i,d 0 1 0 0 1 1 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i≤M NB 2/2 A less than or equal to memory ALEM 0 0 0 0 0 1 0 1 0 0 A≤M NB 1/1 A less than or equal to memory ALEMD d 0 1 0 0 0 1 0 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A≤M NB 2/2 B less than or equal to memory BLEM 0 0 1 1 0 0 0 1 0 0 B≤M NB 1/1 A less than or equal to immediate ALEI i 1 0 1 0 1 1 i3 i2 i1 i0 A≤i NB 1/1 Status Words/ Cycles Table 36 RAM Bit Manipulation Instructions Operation Mnemonic Operation Code Function Set memory bit SEM n 0 0 1 0 0 0 0 1 n1 n0 i → M (n) 1/1 Set memory bit SEMD n,d 0 1 1 0 0 0 0 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i → M (n) 2/2 Reset memory bit REM n 0 0 1 0 0 0 1 0 n1 n0 0 → M (n) 1/1 Reset memory bit REMD n,d 0 1 1 0 0 0 1 0 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 → M (n) 2/2 Test memory bit TM n 0 0 1 0 0 0 1 1 n1 n0 M (n) 1/1 Test memory bit TM n,d 0 1 1 0 0 0 1 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M (n) 2/2 132 HD404374/HD404384/HD404389/HD404082 Series Table 37 ROM Address Instructions Status Words/ Cycles 1 1 b7 b6 b5 b4 b3 b2 b1 b0 1 1/1 BRL u 0 1 0 1 1 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2/2 Long jump unconditionally JMPL u 0 1 0 1 0 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Subroutine jump on status 1 CAL a 0 1 1 1 a5 a4 a3 a2 a1 a0 1 1/2 Long subroutine jump on status 1 CALL u 0 1 0 1 1 0 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2/2 Table branch TBR p 0 0 1 0 1 1 p3 p2 p1 p0 1/1 Return from subroutine RTN 0 0 0 0 0 1 0 0 0 0 1/3 Return from interrupt RTNI 0 0 0 0 0 1 0 0 0 1 Operation Mnemonic Operation Code Branch on status 1 BR b Long branch on status 1 Table 38 Function 2/2 1 → IE, carry restored ST 1/3 Status Words/ Cycles Input/Output Instructions Operation Mnemonic Operation Code Function Set discrete I/O latch SED 0 0 1 1 1 0 0 1 0 0 1 → D (Y) 1/1 Set discrete I/O latch direct SEDD m 1 0 1 1 1 0 m3 m2 m1 m0 1 → D (m) 1/1 Reset discrete I/O latch RED 0 0 0 1 1 0 0 1 0 0 0 → D (Y) 1/1 Reset discrete I/O latch direct REDD m 1 0 0 1 1 0 m3 m2 m1 m0 0 → D (m) 1/1 Test discrete I/O latch TD 0 0 1 1 1 0 0 0 0 0 D (Y) 1/1 Test discrete I/O latch direct TDD m 1 0 1 0 1 0 m3 m2 m1 m0 D (m) 1/1 Load A from R-port register LAR m 1 0 0 1 0 1 m3 m2 m1 m0 R (m) → A 1/1 Load B from R-port register LBR m 1 0 0 1 0 0 m3 m2 m1 m0 R (m) → B 1/1 Load R-port register from A LRA m 1 0 1 1 0 1 m3 m2 m1 m0 A → R (m) 1/1 Load R-port register from B LRB m 1 0 1 1 0 0 m3 m2 m1 m0 B → R (m) 1/1 Pattern generation Pp 0 1 1 0 1 1 p3 p2 p1 p0 1/2 133 HD404374/HD404384/HD404389/HD404082 Series Table 39 Control Instructions Mnemonic Operation Code No operation NOP 0 0 0 0 0 0 0 0 0 0 1/1 Start serial STS 0 1 0 1 0 0 1 0 0 0 1/1 Standby mode/watch mode* SBY 0 1 0 1 0 0 1 1 0 0 1/1 Stop mode/watch mode STOP 0 1 0 1 0 0 1 1 0 1 1/1 Note: * Only after a transition from subactive mode. 134 Function Status Words/ Cycles Operation HD404374/HD404384/HD404389/HD404082 Series Table 40 Opcode Map 0 R8 L 0 1 2 3 4 R9 H 0 NOP XSPX XSPY XSPXY ANEM 1 RTN RTNI 5 6 ALEM 2 0 LBM(XY) LMAIY(X) NEGA BNEM B C ORM AMC EORM D E F IB AYY LASPY IY RED LASPX TC YNEI i(4) 8 9 XMA(XY) SEM n(2) LAM(XY) LMA(XY) ROTR ROTL REM n(2) SMC DAA B TM n(2) ANM DAS LAY TBR p(4) C BLEM LBA DB D LMADY(X) SYY LYA DY E TD SED LXA F 1 A LAB 7 A 9 ILEM i(4) 4 6 8 AM INEM i(4) 3 5 7 XMB(XY) REC SEC LWI i(2) 0 LBI i(4) 1 LYI i(4) 2 LXI i(4) 3 LAI i(4) 4 LBR m(4) 5 LAR m(4) 6 REDD m(4) 7 LAMR m(4) 8 AI i(4) 9 LMIIY i(4) A TDD m(4) B ALEI i(4) C D LRB m(4) E SEDD m(4) F XMRA m(4) LRA m(4) 1-word/2-cycle instruction 1-word/3-cycle instruction RAM direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction 135 HD404374/HD404384/HD404389/HD404082 Series Table 40 Opcode Map (cont) 1 R8 L 0 1 2 3 4 R9 H 0 LAW ANEMD 1 LWA ALEMD 5 6 2 0 8 9 A B C AMD ORMD AMCD EORMD D E F INEMD i(4) 3 4 7 ILEMD i(4) COMB OR STS 5 JMPL p(4) 6 CALL p(4) 7 SBY STOP BRL p(4) 8 XMAD 9 LAMD SEMD n(2) LMAD REMD n(2) SMCD A LMID i(4) B P p(4) TMD n(2) ANMD C D CAL a(6) E F 0 1 2 3 4 5 6 7 1 BR b(8) 8 9 A B C D E F 1-word/2-cycle instruction 136 1-word/3-cycle instruction RAM direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction HD404374/HD404384/HD404389/HD404082 Series Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +14.0 V Pin voltage VT –0.3 to VCC+0.3 V Allowable input current (total) ∑l0 100 mA 2 Allowable output current (total) –∑ l0 50 mA 3 Allowable input current (per pin) l0 4 mA 4,5 30 mA 4,6 4 mA 7,8 20 mA 7,9 –20 to +75 °C 10, 12 –40 to +85 °C 11, 12 –55 to +125 °C 13 Allowable output current (per pin) Operating temperature Storage temperature –l0 Topr Tstg Notes 1 Notes: Permanent damage may occur if these maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to the HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, and HD407C4389 TEST (V PP ) pin. 2. The allowable input current (total) is the sum of all currents flowing from I/O pins to ground at the same time. 3. The allowable output current (total) is the sum of all currents flowing from V CC to I/O pins. 4. The allowable input current (per pin) is the maximum current allowed to flow from any one I/O pin to ground. 5. Applies to pins D 0 to D3, D8, D9 and port R. 6. Applies to pins D 4 to D7. 7. The allowable output current (per pin) is the maximum current allowed to flow from VCC to any one I/O pin. 8. Applies to pins D 4 to D9 and port R. 9. Applies to pins D0 to D3. 10. Applies to Mask ROM 11. Applies to ZTAT TM. 12. The operating temperature indicates the temperature range in which power can be supplied to the LSI (voltage Vcc shown in the electrical characteristics tables can be applied). 13. In the case of chips, the storage specification differs from that of the package products. Please consult your Hitachi sales representative for details. 137 HD404374/HD404384/HD404389/HD404082 Series Electrical Characteristics DC Characteristics (HD404372, HD40A4372, HD40C4372, HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384, HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389, HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404082, HCD40C4082: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = +75°C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: VCC = 2.0 V to 5.5 V, GND = 0 V, Ta = –40°C to +85°C, unless otherwise specified) Item Symbol Pins min. typ. max. Unit Test conditions Notes RESET,SCK, 0.90V CC SI, INT0, WU0, EVNB — VCC+0.3 V OSC 1 — VCC+0.3 V RESET,SCK, –0.3 SI, INT0, WU0, EVNB — 0.10V CC V OSC 1 –0.3 — 0.3 V External clock operation VOH SCK,SO, TOB, TOC VCC–0.5 — — V –I OH=0.3mA Output low voltage VOL SCK,SO, TOB, TOC — — 0.4 V I OL =0.4mA I/O leakage current RESET,SCK, SI,INT0, WU0, EVNB, OSC1, TOB, TOC, SO — — 1 µA Vin=0V to VCC 1 VCC — 1.5 3.5 mA VCC=5V, fOSC=4MHz 2, 7 — 1.2 2.5 mA — 0.4 1.0 mA — 0.3 0.7 mA — 2.7 9.0 mA — 2.2 4.5 mA — 1.0 1.5 mA — 0.6 1.3 mA — 0.3 0.6 mA — 0.2 0.5 mA — 1.4 4.0 mA — 1.0 2.5 mA — 18 35 µA Input high voltage VIH Input low voltage Output high voltage VIL | IIL| Active mode lCC1 current dissipation lCC2 lCC3 Standby mode lSBY1 VCC current dissipation lSBY2 lSBY3 Subactive mode lSUB current dissipation 138 VCC VCC–0.3 External clock operation 2, 8 VCC=3V, fOSC=800kHz 2, 7 2, 8 VCC=5V, fOSC=8MHz 2, 9 2, 10 VCC=5V, fOSC=4MHz 3, 7 3, 8 VCC=3V, fOSC=800kHz 3, 7 3, 8 VCC=5V, fOSC=8MHz 3, 9 3, 10 VCC = 3V, 32 kHz oscillator used 4, 5 HD404374/HD404384/HD404389/HD404082 Series Item Symbol Pins min. typ. max. Unit Test Conditions Notes Watch mode lWTC current dissipation VCC — 6 10 µA VCC = 3 V, 32 kHz oscillator used 4, 5 Stop mode current lSTOP dissipation VCC — — 5 µA VCC = 3 V, no 32 kHz oscillator 4 1.5 — — V no 32 kHz oscillator 6 Stop mode retention voltage VSTOP VCC Notes: 1. Excludes output buffer current. 2. Power supply current when the MCU is in the reset state and there are no I/O currents. Test Conditions MCU State Pin States • Reset state • RESET, TEST: At ground 3. Power supply current when the on-chip timers are operating and there are no I/O currents. Test Conditions MCU State Pin States • I/O: Same as reset state • Standby mode • f cyc = fOSC/4 • RESET: At VCC • TEST: At ground • D port, R port: At VCC 4. Power supply current when there are no I/O currents. Test Conditions Pin States • RESET: At VCC • TEST: At ground • D port, R port: At VCC 5. 6. 7. 8. 9. Applies to HD404374 Series. Voltage needed to retain RAM data. Applies to HD404374, HD404384, and HD404389 Series. Applies to HD404082 Series. Applies to HD40A4374/2, HD407A4374, HD40A4384/2, HD407A4384, HD40A4389/8 and HD407A4389. 10. Applies to HD40A4082/1. 139 HD404374/HD404384/HD404389/HD404082 Series I/O Characteristics for Standard Pins DC Characteristics (HD404372, HD40A4372, HD40C4372, HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384, HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389, HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082: V CC = 1.8 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404082, HCD40C4082: V CC = 1.8 V to 5.5 V, GND = 0 V, T a = +75°C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: VCC = 2.0 V to 5.5 V, GND = 0 V, Ta = –40°C to +85°C, unless otherwise specified) Item Symbol Pins min. typ. max. Unit Input high voltage VIH R port, D8, D9 0.7VCC — VCC+0.3 V Input low voltage VIL R port, D8, D9 –0.3 — 0.3VCC V Output high voltage VOH R port, D8, D9 VCC–0.5 — — V –I OH=0.3mA Output low voltage VOL R port, D8, D9 — — 0.4 V IOL =0.4mA I/O leakage current | I IL | R port, D8, D9 — — 1 µA Vin=0V to VCC MOS pull-up current –I PU R port, D8, D9 10 50 150 µA VCC=3V, Vin=0V Note: Test conditions Notes 1 1. Excludes output buffer current. I/O Characteristics for High-Current Pins DC Characteristics (HD404372, HD40A4372, HD40C4372, HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384, HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389, HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404082, HCD40C4082: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = +75°C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: VCC = 2.0 V to 5.5 V, GND = 0 V, Ta = –40°C to +85°C, unless otherwise specified) Item Symbol Pins min. typ. max. Unit Input high voltage VIH D0 to D7 0.7VCC — VCC+0.3 V Input low voltage VIL D0 to D7 –0.3 — 0.3VCC V Output high voltage VOH D4 to D7 VCC–0.5 — — V –I OH=0.3mA D0 to D3 VCC–2.0 — — V –I OH=10mA, VCC=4.5 to 5.5V D0 to D3 — — 0.4 V IOL =0.4mA D4 to D7 — — 2.0 V IOL =15mA VCC=4.5V to 5.5V Output low voltage VOL Test conditions I/O leakage current | I IL | D0 to D7 — — 1 µA Vin =0V to VCC MOS pull-up current –I PU D0 to D7 10 50 150 µA VCC=3V, Vin=0V Note: 140 1. Excludes output buffer current. Notes 1 HD404374/HD404384/HD404389/HD404082 Series A/D Converter Characteristics (HD404374/HD404384/HD404389 Series) (Mask ROM: VCC = 1.8 V to 5.5 V, GND = 0 V, T a = –20°C to +75°C; ZTATTM : VCC = 2.0 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pins min. typ. max. Unit Analog power supply voltage AV CC AV CC VCC–0.3 VCC VCC+0.3 V Analog input voltage AV in AN0 to AN5 AV SS — AV CC V AV CC-AVSS current IAD — — 500 µA Analog input capacitance CAin — 15 — pF Resolution — 10 — bit Number of inputs 0 — 4 channel Absolute accuracy — — ±4.0 LSB AN0 to AN5 Conversion time Input impedance AN0 to AN5 Test conditions Notes 1 VCC=AVCC=5.0V VCC=AVCC=1.8V to 5.5V 2 VCC=AVCC=2.0V to 5.5V 3 2 125 — — tcyc VCC=AVCC=1.8V to 2.0V or less 65 — — tcyc VCC=AVCC=2.0V to 5.5V 1 — — MΩ Notes: 1. Connect to the VCC pin when the A/D converter is not used. The AVCC setting range is 1.8 V≤AVCC≤5.5V (Mask ROM), 2.0V ≤ AVCC ≤ 5.5V (ZTATTM). 2. Applies to Mask ROM. 3. Applies to ZTAT TM. 141 HD404374/HD404384/HD404389/HD404082 Series AC Characteristics DC Characteristics (HD404372, HD40A4372, HD40C4372, HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384, HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389, HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404082, HCD40C4082: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = +75°C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: VCC = 2.0 V to 5.5 V, GND = 0 V, Ta = –40°C to +85°C, unless otherwise specified) Item Symbol Pins min. typ. max. Unit Test conditions Notes Clock oscillation frequency fOSC OSC1, OSC2 0.4 — 4.5 MHz Division by 4 1 0.4 — 8.5 (ceramic oscillator, crystal oscillator) fx X1,X2 — 32.768 — kHz Clock oscillation frequency fOSC OSC1, OSC2 0.5 2.0 3.5 MHz 0.5 2.2 3.5 0.89 — 10 0.47 — 10 — 244.14 — µs 32 kHz oscillator used, 4 division by 8 — 122.07 — µs 32 kHz oscillator used, 4 division by 4 1.14 — 8.0 µs Division by 4 Rf=20 kΩ (Resistance oscillation) Instruction cycle time (external clock, ceramic oscillator, crystal oscillator) tcyc tsubcyc Instruction cycle time tcyc (Resistance oscillation) 1, 3 4 Division by 4 Rf=20 kΩ 2, 5 2, 13 µs Division by 4 3 5 Oscillation settling time tRC (external clock input) OSC1, OSC2 — — 7.5 ms Oscillation settling time tRC (ceramic oscillator) OSC1, OSC2 — — 7.5 ms VCC=2.0 to 5.5V 6 Oscillation settling time(crystal oscillator) OSC1, OSC2 — — 30 ms VCC=2.0 to 5.5V 6 X1,X2 — — 2 s Ta=–10 to +60°C, VCC=2.0 to 5.5V 4, 6 Oscillation setting time tRC (Resistance oscillation) OSC1, OSC2 — — 0.5 ms Rf=20 kΩ VCC=2.0 to 5.5V 5, 6 External clock highlevel width tCPH OSC1 105 — — ns fOSC=4MHz 7 fOSC=8MHz 3, 7 External clock lowlevel width tCPL fOSC=4MHz 7 fOSC=8MHz 3, 7 fOSC=4MHz 7 fOSC=8MHz 3, 7 fOSC=4MHz 7 fOSC=8MHz 3, 7 tRC 52.5 External clock rise time tCPr OSC1 105 — — ns 52.5 OSC1 — — 20 ns 10 External clock fall time tCPf OSC1 — — 20 10 142 ns 6 HD404374/HD404384/HD404389/HD404082 Series Item Symbol Pins min. typ. max. Unit INT0, EVNB, WU0, high-level width tIH INT0, EVNB, WU0 2 — — tcyc /tsubcyc 8 INT0, EVNB, WU0, low-level width tIL INT0, EVNB, WU0 2 — — tcyc /tsubcyc 8 RESET low-level width tRSTL RESET 2 — — tcyc 9 RESET rise time tRSTr RESET — — 20 ms 9 Input capacitance Cin All input pins except TEST — — 15 pF TEST — — 15 pF 10 TEST — — 40 pF 11 OSC1, OSC2 — — 1 pF 5 Capacitance between CRF OSC1 and OSC2 (Resistance oscillation) Test conditions Notes f=1MHz,Vin=0V Notes: 1. When the subsystem oscillator (32.768 kHz crystal oscillation) is used, use within the range 0.4 MHz≤fOSC≤1.0 MHz or 1.6 MHz≤fOSC≤8.5 MHz. The SSR1 bit of the system clock select register (SSR) should be set to 0 and 1, respectively. 2. The typ. value is the value when VCC = 3.5 V. 3. Applies to HD40A4372/4, HD40A4382/4, HD40A4388/9, HD40A4081/2, HD407A4374, HD407A4384 and HD407A4389 when V CC = 4.0 to 5.5 V. 4. Applies to HD404374 Series. 5. Applies to HD40C4372/4, HD407C4374, HD40C4382/4, HD407C4384, HD40C4388/9, HD407C4389, HD40C4081/2, HCD40C4082. 6. The oscillation settling time is defined as follows: (1) The time required for the oscillation to settle after V CC has reached standard minimum at power-on. (2) The time required for the oscillation to settle after RESET input has gone low when stop mode is cleared. To ensure enough time for the oscillation to settle at power-on hold the RESET input low for at least time t RC. The oscillation settling time will depend on the circuit constants and stray capacitance. The resonator should be determined in consultation with the resonator manufacturer. With regard to the system clock (OSC1, OSC 2), bits MIS1 and MIS0 in the miscellaneous register (MIS) should be set according to the oscillation settling time of the resonator used. 7. See figure 79. 8. See figure 80. 9. See figure 81. 10. Applies to Mask ROM. 11. Applies to ZTAT TM. 12. Applies to HD40C4081/2, HCD40C4082. 13. Applies to HD40C4372/4, HD407C4374, HD40C4382/4, HD40C4388/9, HD407C4389. 143 HD404374/HD404384/HD404389/HD404082 Series Serial interface timing characteristics DC Characteristics (HD404372, HD40A4372, HD40C4372, HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384, HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389, HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082: V CC = 1.8 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404082, HCD40C4082: V CC = 1.8 V to 5.5 V, GND = 0 V, T a = +75°C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: VCC = 2.0 V to 5.5 V, GND = 0 V, Ta = –40°C to +85°C, unless otherwise specified) Item Symbol Pins min. typ. max. Unit Test conditions Notes Serial clock cycle time tScyc SCK 1 — — tcyc See load in figure 83 1 Serial clock high-level width tSCKH SCK 0.4 — — tScyc See load in figure 83 1 Serial clock low-level width tSCKL SCK 0.4 — — tScyc See load in figure 83 1 Serial clock rise time tSC Kr SCK — — 100 ns See load in figure 83 1 Serial clock fall time tSCKf SCK — — 100 ns See load in figure 83 1 Serial output data delay time tDSO SO — — 300 ns See load in figure 83 1 Serial input data setup tSSI time SI 200 — — ns 1 Serial input data hold time SI 200 — — ns 1 144 tHSI HD404374/HD404384/HD404389/HD404082 Series During Serial Clock Input Item Symbol Pins min. typ. max. Unit Serial clock cycle time tScyc SCK 1 — — tcyc 1 Serial clock high-level width tSCKH SCK 0.4 — — tScyc 1 Serial clock low-level width tSCKL SCK 0.4 — — tScyc 1 Serial clock rise time tSC Kr SCK — — 100 ns 1 Serial clock fall time tSCKf SCK — — 100 ns 1 Serial output data delay time tDSO SO — — 300 ns Serial input data setup tSSI time SI 200 — — ns 1 Serial input data hold time SI 200 — — ns 1 Note: tHSI Test conditions See load in figure 83 Notes 1 1. See figure 82. OSC1 1/fCP VCC-0.3V tCPL 0.3V tCPH tCPr tCPf Figure 79 External Clock Input Waveform INT0 ,EVNB, WU0 0.9VCC tIH tIL 0.1VCC Figure 80 Interrupt Timing 145 HD404374/HD404384/HD404389/HD404082 Series RESET 0.9VCC tRSTL 0.1VCC tRSTr Figure 81 Reset Timing tScyc tSCKf SCK tSCKr tSCKL VCC–0.5V(0.9VCC)* tSCKH 0.4V(0.1VCC)* tDSO SO VCC–0.5V 0.4V tSSI SI tHSI 0.9VCC 0.1VCC Note : * VCC–0.5V and 0.4V are the voltages during serial clock output. 0.9 VCC and 0.1 VCC are the voltages during serial clock input. Figure 82 Serial Interface Timing 146 HD404374/HD404384/HD404389/HD404082 Series VCC R1=2.6kΩ Test point C=30pF R=12kΩ 1S2074(H) or equivalent Figure 83 Timing Load Circuit 147 HD404374/HD404384/HD404389/HD404082 Series 5.0 2.5 Ta=25°C fcyc=fosc/4 typ Ta=25°C Rf=20kW fcyc=fosc/4 typ 2.0 fosc=8MHz 3.0 ICC (mA) ICC (mA) 4.0 2.0 1.5 1.0 fosc=4MHz fosc=2MHz fosc=800kHz fosc=400kHz 1.0 0.5 0.0 0.0 1 2 3 4 5 6 1 2 VCC (V) 3 4 5 6 VCC (V) (a) ICC vs. VCC characteristic (ceramic oscillation, crystal oscillation) (b) ICC vs. VCC characteristic (resistance oscillation) 5.0 2.5 Ta=25°C Rf=20kΩ typ Ta=25°C typ 2.0 fosc (MHz) fosc (MHz) 4.0 3.0 2.0 1.5 VCC=5V VCC=3.5V VCC=2V 1.0 1.0 0.0 1 2 3 4 5 6 0 10 VCC (V) (c) fOSC vs. VCC characteristic (resistance oscillation) 40 50 (d) fOSC vs. Rf characteristic (resistance oscillation) 2.5 5.0 Ta=25°C typ Ta=25°C typ 2.0 4.0 VCC-VOH (V) VCC=4.5V VOL (V) 20 30 Rf (kΩ) VCC=5V VCC=5.5V 1.5 1.0 0.5 3.0 VCC=4.5V VCC=5V VCC=5.5V 2.0 1.0 0.0 0.0 0 10 20 30 IOL (mA) 40 (e) VOL vs. IOL characteristic (pins D4 to D7) 50 0 5 10 15 -IOH (mA) 20 25 (f) VCC - VOH vs. IOH characteristic (pins D0 to D3) Figure 84 HD404374, HD404384, and HD404389 Series Characteristic Curves (Reference Values) 148 HD404374/HD404384/HD404389/HD404082 Series 2.5 2.5 Ta=25°C fcyc=fosc/4 typ Ta=25°C Rf=20kΩ fcyc=fosc/4 typ fosc=8MHz 2.0 fosc=4MHz 1.5 ICC (mA) ICC (mA) 2.0 1.0 fosc=2MHz fosc=800kHz fosc=400kHz 0.5 1.5 1.0 0.5 0.0 0.0 1 2 3 4 5 6 1 2 3 VCC (V) (a) ICC vs. VCC characteristic (ceramic oscillation, crystal oscillation) 4 VCC (V) 5 6 (b) ICC vs. VCC characteristic (resistance oscillation) 2.5 5.0 Ta=25°C typ 4.0 fosc (MHz) fosc (MHz) 2.0 3.0 2.0 1.5 Ta=25°C Rf=20kΩ typ VCC=5V VCC=3.5V VCC=2V 1.0 1.0 0.0 1 2 3 4 VCC (V) 5 6 0 (c) fOSC vs. VCC characteristic (resistance oscillation) 10 20 30 Rf (kΩ) 40 50 (d) fOSC vs. Rf characteristic (resistance oscillation) 2.5 5.0 Ta=25°C typ Ta=25°C typ 2.0 4.0 VCC-VOH (V) VOL (V) VCC=4.5V VCC=5V VCC=5.5V 1.5 1.0 0.5 3.0 VCC=4.5V VCC=5V VCC=5.5V 2.0 1.0 0.0 0.0 0 10 20 30 40 50 IOL (mA) (e) VOL vs. IOL characteristic (pins D4 to D7) 0 5 10 15 20 25 -IOH (mA) (f) VCC - VOH vs. IOH characteristic (pins D0 to D3) Figure 85 HD404082 Series Characteristic Curves (Reference Values) 149 HD404374/HD404384/HD404389/HD404082 Series Package Dimensions Unit: mm 11.0 11.2 Max 16 1 15 8.0 30 0.65 *0.32 ± 0.08 0.30 ± 0.06 0.10 1.0 0° – 8° 0.10 ± 0.10 1.05 Max 10.0 ± 0.2 *0.17 ± 0.05 0.15 ± 0.04 2.00 Max 0.10 M 0.5 ± 0.1 Hitachi Code JEDEC EIAJ Weight (reference value) *Dimension including the plating thickness Base material dimension FP-30D — — — Unit: mm 27.1 27.9 Max 28 14 0.48 ± 0.10 0.51 Min 2.41 Max 1.78 ± 0.25 10.16 5.10 Max 1.0 2.54 Min 1 10.8 Max 8.8 15 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) 150 DP-28S — Conforms 1.9 g HD404374/HD404384/HD404389/HD404082 Series Unit: mm 24 48 13 M *Dimension including the plating thickness Base material dimension 0.10 ± 0.07 0.08 0.15 ± 0.04 0.08 1.40 0.20 ± 0.04 12 *0.17 ± 0.05 1 *0.22 ± 0.05 0.5 37 1.70 Max 9.0 ± 0.2 9.0 ± 0.2 7 36 25 1.0 0.75 0° – 8° 0.5 ± 0.1 Hitachi Code JEDEC EIAJ Weight (reference value) FP-48B — — 0.2 g 151 HD404374/HD404384/HD404389/HD404082 Series Note on ROM Ordering Please note the following when ordering HD404372, HD40A4372, HD40C4372, HD404382, HD40A4382 and HD40C4382 ROM. When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of data as for the 4-kwords version (HD404374, HD40A4374, HD40C4372, HD404384, HD40A4384, HD40C4384). The program that converts ROM data to mask drawing data is the same as that used for the 4-kwords version, and therefore the same amount of data is necessary. This applies both to orders using EPROM and orders using data transmission. 2-kword ROM version: HD404372, HD40A4372, HD40C4372, HD404382, HD40A4382, HD40C4382 Write all-1 data to addresses $0800 to $0FFF. $0000 Vector addresses $000F $0010 Zero page subroutine area (64 words) $003F $0040 Program and pattern area (2,048 words) $07FF $0800 Not used* $0FFF Note : Write all-1 data in not used area. 152 HD404374/HD404384/HD404389/HD404082 Series Please note the following when ordering HD404388, HD40A4388 and HD40C4388 ROM. When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of data as for the 16-kwords version (HD404389, HD40A4389, HD40C4389). The program that converts ROM data to mask drawing data is the same as that used for the 16-kwords version, and therefore the same amount of data is necessary. This applies both to orders using EPROM and orders using data transmission. 8-kword ROM version: HD404388, HD40A4388, HD40C4388 Write all-1 data to addresses $2000 to $3FFF. $0000 Vector addresses $000F $0010 Zero page subroutine area (64 words) $003F $0040 Program and pattern area (8,192 words) $1FFF $2000 Not used* $3FFF Note : Write all-1 data in not used area. 153 HD404374/HD404384/HD404389/HD404082 Series Please note the following when ordering HD404081, HD40A4081 and HD40C4081 ROM. When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of data as for the 2-kwords version (HD404082, HD40A4082, HD40C4082). The program that converts ROM data to mask drawing data is the same as that used for the 2-kwords version, and therefore the same amount of data is necessary. This applies both to orders using EPROM and orders using data transmission. 1-kword ROM version: HD404081, HD40A081, HD40C4081 Write all-1 data to addresses $0400 to $07FF. $0000 Vector addresses $000F $0010 Zero page subroutine area (64 words) $003F $0040 Program and pattern area (1,024 words) $03FF $0400 Not used* $07FF Note : Write all-1 data in not used area. 154 HD404374/HD404384/HD404389/HD404082 Series Option List HD404372, HD404374, HD40A4372, HD40A4374, HD40C4372, HD40C4374 Please check off the appropriate applications and enter the necessary information. Date of order Year Month Day Customer Department Name ROM code name LSI number (Hitachi entry) 1. ROM Size ❑ Standard operation version: HD404372 2 kwords ❑ High-speed operation version: HD40A4372 ❑ CR oscillation version: HD40C4372 ❑ Standard operation version: HD404374 4 kwords ❑ High-speed operation version: HD40A4374 ❑ CR oscillation version: HD40C4374 2. Function Options * ❑ 32 kHz CPU operation, realtime clock time base * ❑ No 32 kHz CPU operation, realtime clock time base ❑ No 32 kHz CPU operation, no realtime clock time base Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1 X2). 3. ROM Code Data Organization For a microcomputer with EPROM mounted (including a ZTAT™ microcomputer), specify the combined upper/lower type. ❑ Combined lower/upper type • Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU... ❑ Separate lower/upper type • The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively. 155 HD404374/HD404384/HD404389/HD404082 Series 4. System Oscillator (OSC1-OSC2) (Shading means selection is not available) HD404372/4, HD40A4372/4 ❑ Ceramic oscillator f= MHz ❑ Crystal oscillator f= MHz ❑ External clock f= MHz ❑ Resistance oscillator HD40C4372/4 5. Subsystem Oscillator (X1 X2) ❑ Not used — ❑ Crystal resonator f = 32.768 kHz 6. Stop Mode ❑ Yes (used) ❑ No (not used) 7. Package ❑ FP-30D ❑ FP-48B* Note: *The WS version will become available at the beginning of mass production. 156 HD404374/HD404384/HD404389/HD404082 Series Option List HD404382, HD404384, HD40A4382, HD40A4384, HD40C4382, HD40C4384 Please check off the appropriate applications and enter the necessary information. Date of order Year Month Day Customer Department Name ROM code name LSI number (Hitachi entry) 1. ROM Size ❑ Standard operation version: HD404382 2 kwords ❑ High-speed operation version: HD40A4382 ❑ CR oscillation version: HD40C4382 ❑ Standard operation version: HD404384 4 kwords ❑ High-speed operation version: HD40A4384 ❑ CR oscillation version: HD40C4384 2. ROM Code Data Organization For a microcomputer with EPROM mounted (including a ZTAT™ microcomputer), specify the combined upper/lower type. ❑ Combined lower/upper type • Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU... ❑ Separate lower/upper type • The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively. 3. System Oscillator (OSC1-OSC2) (Shading means selection is not available) HD404382/4, HD40A4382/4 ❑ Crystal oscillator f= MHz ❑ Ceramic oscillator f= MHz ❑ External clock f= MHz ❑ Resistance oscillator HD40C4382/4 f= 4. Stop Mode 5. Package ❑ Yes (used) ❑ FP-30D ❑ No (not used) ❑ DP-28S ❑ FP-48B* MHz Note: *The WS version will become available at the beginning of mass production. 157 HD404374/HD404384/HD404389/HD404082 Series Option List HD404388, HD404389, HD40A4388, HD40A4389, HD40C4388, HD40C4389 Please check off the appropriate applications and enter the necessary information. Date of order Year Month Day Customer Department Name ROM code name LSI number (Hitachi entry) 1. ROM Size ❑ Standard operation version: HD404388 8 kwords ❑ High-speed operation version: HD40A4388 ❑ CR oscillation version: HD40C4388 ❑ Standard operation version: HD404389 16 kwords ❑ High-speed operation version: HD40A4389 ❑ CR oscillation version: HD40C4389 2. ROM Code Data Organization For a microcomputer with EPROM mounted (including a ZTAT™ microcomputer), specify the combined upper/lower type. ❑ Combined lower/upper type • Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU... ❑ Separate lower/upper type • The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively. 3. System Oscillator (OSC1-OSC2) (Shading means selection is not available) HD404388/9, HD40A4388/9 ❑ Crystal oscillator f= MHz ❑ Ceramic oscillator f= MHz ❑ External clock f= MHz ❑ Resistance oscillator f= 4. Stop Mode 5. Package ❑ Yes (used) ❑ ❑ No (not used) 158 HD40C4388/9 FP-30D MHz HD404374/HD404384/HD404389/HD404082 Series Option List HD404081, HD404082, HCD404082, HD40A4081, HD40A4082, HD40C4081, HD40C4082, HCD40C4082 Please check off the appropriate applications and enter the necessary information. Date of order Year Month Day Customer Department Name ROM code name LSI number (Hitachi entry) 1. ROM Size ❑ Standard operation version: HD404081 1 kwords ❑ High-speed operation version: HD40A4081 ❑ CR oscillation version: HD40C4081 ❑ Standard operation version: HD404082 2 kwords ❑ Standard operation version: HCD404082 ❑ High-speed operation version: HD40A4082 ❑ CR oscillation version: HD40C4082 ❑ CR oscillation version: HCD40C4082 2. System Oscillator (OSC1-OSC2) (Shading means selection is not available) HD404381/2, HD40A4381/2 ❑ Crystal oscillator f= MHz ❑ Ceramic oscillator f= MHz ❑ External clock f= MHz ❑ Resistance oscillator HD40C4381/2 f= 3. Stop Mode 4. Package ❑ Yes (used) ❑ FP-30D ❑ No (not used) ❑ DP-28S ❑ Chip MHz Note: The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details. 159 HD404374/HD404384/HD404389/HD404082 Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 160