HITACHI HD40A4356H

HD404358 Series
Rev. 6.0
Sept. 1998
Description
The HD404358 Series is a 4-bit HMCS400-Series microcomputer designed to increase program
productivity and also incorporate large-capacity memory. Each microcomputer has an A/D converter, input
capture timer, and two low-power dissipation modes.
The HD404358 Series includes seven chips: the HD404354, HD40A4354 with 4-kword ROM; the
HD404356, HD40A4356 with 6-kword ROM; the HD404358, HD40A4358 with 8-kword ROM; the
HD407A4359 with 16-kword PROM.
The HD40A4354, HD40A4356, HA40A4358, and HD407A4359 are high speed versions (minimum
instruction cycle time: 0.47 µs)
The HD407A4359 is a PROM version (ZTATmicrocomputer). A program can be written to the PROM
by a PROM writer, which can dramatically shorten system development periods and smooth the process
from debugging to mass production. (The ZTAT version is 27256-compatible.)
ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
Features
• 34 I/O pins
 One input-only pin
 33 input/output pins: 4 pins are intermediate-voltage NMOS open drain with high-current pins (15
mA, max.)
• On-chip A/D converter (8-bit × 8-channel)
 Low power voltage 2.7 V to 6.0 V
• Three timers
 One event counter input
 One timer output
 One input capture timer
• Eight-bit clock-synchronous serial interface (1 channel)
• Alarm output
HD404358 Series
• Built-in oscillators
 Ceramic oscillator or crystal
 External clock drive is also possible
• Seven interrupt sources
 Two by external sources
 Three by timers
 One by A/D converter
 One by serial interface
• Two low-power dissipation modes
 Standby mode
 Stop mode
• Instruction cycle time
 0.47 µs (fOSC = 8.5 MHz, 1/4 division ratio):
HD40A4354, HD40A4356, HD40A4358,
HD407A4359
 0.8 µs (fOSC = 5 MHz, 1/4 division ratio):
HD404354, HD404356, HD404358
Ordering Information
Type
Instruction Cycle
Time
Mask ROM Standard versions
Product Name
Model Name
ROM
(Words)
RAM
(Digit)
Package
HD404354
HD404354S
4,096
384
DP-42S
(fOSC= 5 MHz)
HD404354H
HD404356
HD404356S
FP-44A
6,144
DP-42S
HD404356H
HD404358
HD404358S
FP-44A
8,192
DP-42S
HD404358H
High speed versions HD40A4354
HD40A4354S
(fOSC= 8.5 MHz)
HD40A4354H
HD40A4356
HD40A4356S
FP-44A
4,096
384
FP-44A
6,144
DP-42S
HD40A4356H
HD40A4358
HD40A4358S
FP-44A
8,192
DP-42S
HD40A4358H
ZTAT
(fOSC= 8.5 MHz)
HD407A4359
HD407A4359S
HD407A4359H
2
DP-42S
FP-44A
16,384
512
DP-42S
FP-44A
HD404358 Series
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
DP-42S
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
R23
R22
R21
R20
R13
R12
R11
R10
R83
R82
R81
R80
D8
D7
D6
D5
D4/STOPC
D3/BUZZ
D2/EVNB
D1/INT1
D0/INT0
44
43
42
41
40
39
38
37
36
35
34
NC
R03 /TOC
R02 /SO
R01 /SI
R00 /SCK
RA1
R23
R22
R21
R20
R13
RA 1
R00/SCK
R01/SI
R02/SO
R03/TOC
TEST
RESET
OSC1
OSC2
GND
AVSS
R30/AN0
R31/AN1
R32/AN2
R33/AN3
R40/AN4
R41/AN5
R42/AN6
R43/AN7
AV CC
V CC
FP-44A
33
32
31
30
29
28
27
26
25
24
23
R12
R11
R10
R83
R82
R81
R80
D8
D7
D6
D5
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
R41/AN5
R42/AN6
R43/AN7
AVCC
VCC
D0/INT0
D1/INT1
D2/EVNB
D3/BUZZ
D4/STOPC
NC
TEST
RESET
OSC1
OSC2
GND
AVSS
R30/AN0
R31/AN1
R32/AN2
R33/AN3
R40/AN4
3
HD404358 Series
Pin Description
Pin Number
Item
Symbol
DP-42S FP-44A I/O
Function
Power
supply
VCC
21
16
Applies power voltage
GND
10
5
Connected to ground
Test
TEST
6
1
I
Cannot be used in user applications. Connect this pin
to GND.
Reset
RESET
7
2
I
Resets the MCU
Oscillator
OSC 1
8
3
I
Input/output pin for the internal oscillator. Connect
these pins to the ceramic oscillator or crystal oscillator,
or OSC1 to an external oscillator circuit.
OSC 2
9
4
O
D0–D 8
22–30
17–21,
I/O
Input/output pins addressed individually by bits; D0–D 8
are all standard-voltage I/O pins.
Port
23–26
RA 1
1
39
I
One-bit standard-voltage input port pin
R0 0–R1 3,
2–5,
40–43,
I/O
R3 0–R4 3,
12–19,
7–14
Four-bit input/output pins consisting of standard-voltage
pins
R8 0–R8 3
31–38
27–34
R2 0–R2 3
39–42
35–38
I/O
Four-bit input/output pins consisting of intermediate
voltage pins
Interrupt
INT0, INT1
22, 23
17, 18
I
Input pins for external interrupts
Stop clear
STOPC
26
21
I
Input pin for transition from stop mode to active mode
Serial
Interface
SCK
2
40
I/O
Serial interface clock input/output pin
SI
3
41
I
Serial interface receive data input pin
SO
4
42
O
Serial interface transmit data output pin
TOC
5
43
O
Timer output pin
EVNB
24
19
I
Event count input pin
Alarm
BUZZ
25
20
O
Square waveform output pin
A/D
converter
AVCC
20
15
Power supply for the A/D converter. Connect this pin
as close as possible to the VCC pin and at the same
voltage as V CC. If the power supply voltage to be used
for the A/D converter is not equal to VCC, connect a 0.1µF bypass capacitor between the AVCC and AV SS pins.
(However, this is not necessary when the AV CC pin is
directly connected to the VCC pin.)
AVSS
11
6
Ground for the A/D converter. Connect this pin as
close as possible to GND at the same voltage as GND.
AN 0–AN 7
12–19
7–14
Timer
4
I
Analog input pins for the A/D converter
HD404358 Series
INT0
GND
VCC
OSC2
OSC1
STOPC
TEST
RESET
Block Diagram
System control
Interrupt
control
D0
RAM
(384 × 4 bits)
(512 × 4 bits)
D1
D2
D port
INT1
W
(2 bits)
Timer A
D5
D7
D8
R0 port
Timer B
D4
D6
X
(4 bits)
EVNB
D3
SPX
(4 bits)
R00
R01
R02
R03
SO
SCK
R1 port
SPY
(4 bits)
R11
R12
R20
R21
R22
R23
ALU
AVSS
•
•
•
A/D
converter
ST
(1 bit)
CA
(1 bit)
R3 port
R30
AN0
•
•
•
R10
R13
R2 port
Serial
interface
Internal data bus
SI
Internal data bus
Timer C
TOC
Internal address bus
Y
(4 bits)
R33
AN7
A
(4 bits)
R40
R4 port
AVCC
B
(4 bits)
BUZZ
R31
R32
R41
R42
R43
Buzzer
SP
(10 bits)
R80
Instruction
decoder
PC
(14 bits)
R8 port
Data bus
R81
R82
Directional
signal line
ROM
(4,096 × 10 bits) (6,144 × 10 bits)
(16,384 × 10 bits)(8,192 × 10 bits)
RA port
R83
Intermediate
voltage pin
RA1
5
HD404358 Series
Memory Map
ROM Memory Map
The ROM memory map is shown in figure 1 and described below.
Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.
Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.
Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.
Program Area ($0000-$0FFF (HD404354, HD40A4354), $0000–$17FF (HD404356, HD40A4356),
$0000–$1FFF (HD404358, HD40A4358), $0000–$3FFF (HD407A4359)): The entire ROM area can be
used for program coding.
$0000
$000F
Vector address
(16 words)
$0010
Zero-page subroutine
(64 words)
$003F
$0040
Pattern (4,096 words)
Program (4,096 words)
$0FFF
For HD404354, HD40A4354
$1000
Program
(6,144 words)
For HD404356, HD40A4356
$17FF
$1800
$1FFF
$2000
Program
(8,192 words)
$0000
JMPL instruction
$0001 (jump to RESET, STOPC routine)
JMPL instruction
$0002
(jump to INT 0 routine)
$0003
JMPL instruction
$0004
(jump to INT 1 routine)
$0005
JMPL instruction
$0006
(jump to timer A routine)
$0007
$0008
JMPL instruction
(jump to timer B routine)
$0009
$000A
JMPL instruction
(jump to timer C routine)
$000B
$000C
JMPL instruction
$000D (jump to A/D converter routine)
$000E
JMPL instruction
(jump to serial routine)
$000F
For HD404358, HD40A4358
Program
(16,384 words)
HD407A4359
$3FFF
Note: Since the ROM address areas between $0000–$0FFF overlap, the user can
determine how these areas are to be used.
Figure 1 ROM Memory Map
6
HD404358 Series
RAM Memory Map
The HD404354, HD40A4354, HD404356, HD40A4356, HD404358 and HD40A4358 MCUs contain 384digit × 4-bit RAM areas. The HD407A4359 MCU contain 512-digit × 4-bit RAM areas. Both of these
RAM areas consist of a memory register area, a data area, and a stack area. In addition, an interrupt control
bits area, special function register area, and register flag area are mapped onto the same RAM memory
space labeled as a RAM-mapped register area. The RAM memory map is shown in figure 2 and described
below.
RAM-Mapped Register Area ($000–$03F):
• Interrupt Control Bits Area ($000–$003)
This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/ SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.
• Special Function Register Area ($004–$01F, $024–$03F)
This area is used as mode registers and data registers for external interrupts, serial interface,
timer/counters, A/D converter, and as data control registers for I/O ports. The structure is shown in
figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and
read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.
• Register Flag Area ($020–$023)
This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).
These bits can be accessed only by RAM bit manipulation instructions (SEM/ SEMD, REM/REMD,
and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on
using the instructions are shown in figure 4.
Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.
Data Area ($050–$17F for HD404354/HD40A4354/HD404356/HD40A4356/HD404358/HD40A4358,
$050–$1FF for HD407A4359)
Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.
The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.
7
HD404358 Series
RAM Memory Map
Initial values
after reset
$000
RAM-mapped registers
$040
$050
Memory registers (MR)
HD404354, HD40A4354,
HD404356, HD40A4356,
HD404358, HD40A4358
Data (304 digits)
$180
HD407A4359
Data (432 digits)
$200
$000
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
Interrupt control bits area
Port mode register A
(PMRA)
Serial mode register
(SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A
(TMA)
Timer mode register B1 (TMB1)
Timer B
(TRBL/TWBL)
(TRBU/TWBU)
Miscellaneous register
(MIS)
Timer mode register C
(TMC)
Timer C
(TRCL/TWCL)
(TRCU/TWCU)
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
0000
0000
Undefined
Undefined
-000
0000
*2/0000
Undefined
00-0000
*2/0000
Undefined
Not used
Not used
$3C0
Stack (64 digits)
$016
$017
$018
$019
$01A
$3FF
A/D channel register
A/D data register lower
A/D data register upper
A/D mode register 1
A/D mode register 2
(ACR)
(ADRL)
(ADRU)
(AMR1)
(AMR2)
W
R
R
W
W
-000
0000
1000
0000
--00
W
W
W
0000
00-0
-000
W
(DCD2)
W
W
0000
0000
---0
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
W
W
W
W
W
0000
0000
0000
0000
0000
(DCR8)
W
0000
Not used
Notes: 1. Two registers are mapped
on the same area ($00A,
$00B, $00E, $00F).
2. Undefined.
R: Read only
W: Write only
R/W: Read/write
$020
Register flag area
$023
$024 Port mode register B
(PMRB)
$025 Port mode register C
(PMRC)
$026 Timer mode register B2
(TMB2)
Not used
$02C Port D0–D3 DCR
(DCD0)
$02D Port D4–D7 DCR
(DCD1)
$02E
$02F
Port D8 DCR
$030
$031
$032
$033
$034
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Not used
Not used
$038
$03F
Port R8 DCR
Not used
$00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W
$00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W
$00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W
$00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W
Figure 2 RAM Memory Map
8
*1
HD404358 Series
Bit 3
Bit 2
Bit 1
Bit 0
0
IM0
(IM of INT0)
IF0
(IF of INT0)
RSP
(Reset SP bit)
IE
(Interrupt
enable flag)
$000
1
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT1)
IF1
(IF of INT1)
$001
2
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
$002
3
IMS
(IM of serial)
IFS
(IF of serial)
IMAD
(IM of A/D)
IFAD
(IF of A/D)
$003
Interrupt control bits area
Bit 3
Bit 2
Bit 1
Bit 0
32
Not used
ADSF
(A/D start flag)
WDON
(Watchdog
on flag)
Not used
$020
33
RAME
(RAM enable
flag)
IAOF
(IAD off flag)
ICEF
(Input capture
error flag)
ICSF
(Input capture
status flag)
$021
$022
34
Not used
$023
35
IF:
IM:
IE:
SP:
Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer
Register flag area
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IE
IM
IAOF
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
Not used
SEM/SEMD
REM/REMD
TM/TMD
Allowed
Allowed
Allowed
Not executed
Allowed
Allowed
Not executed
Allowed
Allowed
Not executed
Allowed
Not executed
Inhibited
Not executed
Inhibited
Inhibited
Allowed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for ADSF during A/D conversion.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
9
HD404358 Series
Bit 3
Bit 2
Bit 0
Bit 1
$000
Interrupt control bits area
$003
PMRA $004
D3 /BUZZ
SMR $005
R00 /SCK
R03/TOC
R01/SI
SRL $006
Serial data register (lower digit)
SRU $007
Serial data register (upper digit)
TMA $008
Not used
TMB1 $009
*1
R02 /SO
Serial transmit clock speed selection
Clock source selection (timer A)
Clock source selection (timer B)
Timer B register (lower digit)
TRBL/TWBL $00A
Timer B register (upper digit)
TRBU/TWBU $00B
MIS $00C
*2
TMC $00D
*1
Not used
SO PMOS control
Clock source selection (timer C)
TRCL/TWCL $00E
Timer C register (lower digit)
TRCU/TWCU $00F
Timer C register (upper digit)
Not used
ACR $016
A/D data register (lower digit)
A/D data register (upper digit)
ADRU $018
AMR1$019
AMR2 $01A
Analog channel selection
Not used
ADRL $017
R33/AN3
R32/AN2
Not used
R31/AN1
R30/AN0
R4/AN4–AN7
*3
Not used
$020
Register flag area
$023
PMRB $024
PMRC $025
TMB2 $026
D4/STOPC
D2/EVNB
D1/INT1
D0/INT0
*4
*5
Buzzer output
Not used
EVNB detection edge selection
*6
Not used
DCD0 $02C
Port D3 DCD Port D2 DCD
Port D1 DCD Port D0 DCD
DCD1 $02D
Port D7 DCD Port D6 DCD
Port D5 DCD Port D4 DCD
DCD2 $02E
Not used
Port D8 DCD
Not used
DCR0 $030
DCR3 $033
Port R03 DCR Port R02 DCR Port R01 DCR Port R00 DCR
Port R13 DCR Port R12 DCR Port R11 DCR Port R10 DCR
Port R23 DCR Port R22 DCR Port R21 DCR Port R20 DCR
Port R33 DCR Port R32 DCR Port R31 DCR Port R30 DCR
DCR4 $034
Port R43 DCR Port R42 DCR Port R41 DCR Port R40 DCR
DCR1 $031
DCR2 $032
Not used
DCR8 $038
Port R83 DCR Port R82 DCR Port R81 DCR Port R80 DCR
Not used
$03F
Notes: 1.
2.
3.
4.
5.
6.
Auto-reload on/off
Pull-up MOS control
A/D conversion time
SO output level control in idle states
Serial clock source selection
Input capture selection
Figure 5 Special Function Register Area
10
HD404358 Series
Memory registers
MR(0) $040
64
MR(1) $041
65
MR(2) $042
66
MR(3) $043
67
MR(4)
$044
68
MR(5)
$045
69
MR(6)
$046
70
MR(7)
$047
71
MR(8)
$048
72
MR(9)
$049
73
MR(10) $04A
74
MR(11) $04B
75
MR(12) $04C
76
MR(13) $04D
77
MR(14) $04E
78
MR(15) $04F
79
Stack area
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
1023 Level 1
960
$3C0
$3FF
Bit 3
Bit 2
Bit 1
Bit 0
1020
ST
PC13
PC 12
PC11
$3FC
1021
PC 10
PC9
PC 8
PC7
$3FD
1022
CA
PC6
PC 5
PC4
$3FE
1023
PC 3
PC2
PC 1
PC0
$3FF
PC13 –PC0 : Program counter
ST: Status flag
CA: Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
11
HD404358 Series
Functional Description
Registers and Flags
The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described
below.
3
Accumulator
0
(A)
Initial value: Undefined, R/W
3
B register
Initial value: Undefined, R/W
W register
Initial value: Undefined, R/W
0
(B)
1
0
(W)
3
X register
Initial value: Undefined, R/W
0
(X)
3
Y register
0
(Y)
Initial value: Undefined, R/W
3
SPX register
Initial value: Undefined, R/W
SPY register
Initial value: Undefined, R/W
Carry
Initial value: Undefined, R/W
Status
Initial value: 1, no R/W
0
(SPX)
3
0
(SPY)
0
(CA)
0
(ST)
13
Program counter
Initial value: 0,
no R/W
0
(PC)
9
Stack pointer
Initial value: $3FF, no R/W
1
5
1
1
1
0
(SP)
Figure 7 Registers and Flags
Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.
W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.
12
HD404358 Series
SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.
Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an
interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.
Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction,
not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL,
CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or
bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read,
regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack
during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.
Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being
executed.
Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and
incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a
stack can be used up to 16 levels.
The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.
Reset
The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is
cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation,
RESET must be high for at least two instruction cycles.
Initial values after MCU reset are listed in table 1.
Interrupts
The MCU has 7 interrupt sources: two external signals (INT 0 and INT1), three timer/counters (timers A, B,
and C), serial interface, and A/D converter.
An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.
Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 in RAM are reserved for the
interrupt control bits which can be accessed by RAM bit manipulation instructions.
The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE)
and the IF to 0 and the interrupt mask (IM) to 1.
A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 7 interrupt sources are listed in
table 3.
13
HD404358 Series
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.
The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in
figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.
Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.
14
HD404358 Series
Table 1
Initial Values After MCU Reset
Item
Abbr.
Initial Value
Contents
Program counter
(PC)
$0000
Indicates program execution point
from start address of ROM area
Status flag
(ST)
1
Enables conditional branching
Stack pointer
(SP)
$3FF
Stack level 0
Interrupt enable flag
(IE)
0
Inhibits all interrupts
Interrupt request flag
(IF)
0
Indicates there is no interrupt
request
Interrupt mask
(IM)
1
Prevents (masks) interrupt requests
Port data register
(PDR)
All bits 1
Enables output at level 1
Data control register
(DCD0 –
DCD1)
All bits 0
Turns output buffer off (to high
impedance)
(DCD2)
---0
(DCR0 –
DCR4,
DCR8)
All bits 0
Port mode register A
(PMRA)
0000
Refer to description of port mode
register A
Port mode register B bits
2–0
(PMRB2 –
PMRB0)
000
Refer to description of port mode
register B
Port mode register C
(PMRC)
00 - 0
Refer to description of port mode
register C
Timer mode register A
(TMA)
- 000
Refer to description of timer mode
register A
Timer mode register B1
(TMB1)
0000
Refer to description of timer mode
register B1
Timer mode register B2
(TMB2)
- 000
Refer to description of timer mode
register B2
Timer mode register C
(TMC)
0000
Refer to description of timer mode
register C
Serial mode register
(SMR)
0000
Refer to description of serial mode
register
Prescaler S
(PSS)
$000
—
Timer counter A
(TCA)
$00
—
Timer counter B
(TCB)
$00
—
Timer counter C
(TCC)
$00
—
Timer write register B
(TWBU,
TWBL)
$X0
—
Timer write register C
(TWCU,
TWCL)
$X0
—
000
—
Interrupt
flags/mask
I/O
Timer/
counters,
serial
interface
Octal counter
15
HD404358 Series
Abbr.
Initial
Value Contents
A/D mode register 1
(AMR1)
0000
A/D mode register 2
(AMR2)
- - 00
A/D channel register
(ACR)
- 000
Refer to description of A/D channel register
A/D data register
(ADRL)
0000
Refer to description of A/D data register
(ADRU)
1000
Watchdog timer on flag
(WDON)
0
Refer to description of timer C
A/D start flag
(ADSF)
0
Refer to description of A/D converter
I AD off flag
(IAOF)
0
Refer to the description of A/D converter
Input capture status flag
(ICSF)
0
Refer to description of timer B
Input capture error flag
(ICEF)
0
Refer to description of timer B
Miscellaneous register
(MIS)
00 - -
Refer to description of operating modes, I/O,
and serial interface
Item
A/D
Bit registers
Others
Refer to description of A/D mode register
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.
2. X indicates invalid value. – indicates that the bit does not exist.
Item
Abbr.
Carry flag
(CA)
Accumulator
(A)
B register
(B)
W register
(W)
X/SPX register
(X/SPX)
Y/SPY register
(Y/SPY)
Serial data register
(SRL, SRU)
RAM
Status After Cancellation of
Stop Mode by STOPC Input
Status After all Other Types of
Reset
Pre-stop-mode values are not
guaranteed; values must be
initialized by program
Pre-MCU-reset values are not
guaranteed; values must be
initialized by program
Pre-stop-mode values are
retained
RAM enable flag
(RAME)
1
0
Port mode register
B bit 3
(PMRB3)
Pre-stop-mode values are
retained
0
16
HD404358 Series
Table 2
Vector Addresses and Interrupt Priorities
Reset/Interrupt
Priority
Vector Address
RESET, STOPC*
—
$0000
INT0
1
$0002
INT1
2
$0004
Timer A
3
$0006
Timer B
4
$0008
Timer C
5
$000A
A/D
6
$000C
Serial
7
$000E
Note: * The STOPC interrupt request is valid only in stop mode.
17
HD404358 Series
$ 000,0
IE
INT0 interrupt
Sequence control
• Push PC/CA/ST
• Reset IE
• Jump to vector
address
$ 000,2
IFO
$ 000,3
IMO
Vector
address
Priority control logic
INT1 interrupt
$ 001,0
IF1
$ 001,1
IM1
Timer A interrupt
$ 001,2
IFTA
$ 001,3
IMTA
Timer B interrupt
$ 002,0
IFTB
$ 002,1
IMTB
Timer C interrupt
$ 002,2
IFTC
$ 002,3
IMTC
A/D interrupt
$ 003,0
IFAD
$ 003,1
IMAD
Serial interrupt
$ 003,2
IFS
$ 003,3
IMS
Note: $m,n is RAM address $m, bit number n.
Figure 8 Interrupt Control Circuit
18
HD404358 Series
Table 3
Interrupt Processing and Activation Conditions
Interrupt Source
INT0
INT1
Timer A
Timer B
Timer C
A/D
Serial
IE
1
1
1
1
1
1
1
IF0 · IM0
1
0
0
0
0
0
0
IF1 · IM1
*
1
0
0
0
0
0
IFTA · IMTA
*
*
1
0
0
0
0
IFTB · IMTB
*
*
*
1
0
0
0
IFTC · IMTC
*
*
*
*
1
0
0
IFAD · IMAD
*
*
*
*
*
1
0
IFS · IMS
*
*
*
*
*
*
1
Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Execution of
instruction at
start address
of interrupt
routine
Figure 9 Interrupt Processing Sequence
19
HD404358 Series
Power on
RESET = 0?
Yes
No
Interrupt
request?
No
Yes
No
IE = 1?
Yes
Reset MCU
Accept interrupt
Execute instruction
IE ← 0
Stack ← (PC)
Stack ← (CA)
Stack ← (ST)
PC ←(PC) + 1
PC← $0002
Yes
INT0
interrupt?
No
PC← $0004
Yes
INT1
interrupt?
No
PC← $0006
Yes
Timer-A
interrupt?
No
PC← $0008
Yes
Timer-B
interrupt?
No
PC ← $000A
Yes
Timer-C
interrupt?
No
PC ← $000C
Yes
A/D
interrupt?
No
PC ← $000E
(serial interrupt)
Figure 10 Interrupt Processing Flowchart
20
HD404358 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.
Table 4
Interrupt Enable Flag (IE: $000, Bit 0)
IE
Interrupt Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (INT0, INT1): Two external interrupt signals.
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): IF0 and IF1 are set at the rising
edge of signals input to INT 0 and INT1, as listed in table 5.
Table 5
External Interrupt Request Flags (IF0: $000, Bit2; IF1: $001, Bit 0)
IF0, IF1
Interrupt Request
0
No
1
Yes
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as listed in table 6.
Table 6
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1)
IM0, IM1
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.
Table 7
Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
IFTA
Interrupt Request
0
No
1
Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer
A interrupt request flag, as listed in table 8.
21
HD404358 Series
Table 8
Timer A Interrupt Mask (IMTA: $001, Bit 3)
IMTA
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in
table 9.
Table 9
Timer B Interrupt Request Flag (IFTB: $002, Bit 0)
IFTB
Interrupt Request
0
No
1
Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer
B interrupt request flag, as listed in table 10.
Table 10
Timer B Interrupt Mask (IMTB: $002, Bit 1)
IMTB
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 11.
Table 11
Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
IFTC
Interrupt Request
0
No
1
Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer
C interrupt request flag, as listed in table 12.
Table 12
Timer C Interrupt Mask (IMTC: $002, Bit 3)
IMTC
Interrupt Request
0
Enabled
1
Disabled (masked)
22
HD404358 Series
Serial Interrupt Request Flag (IFS: $003, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 13.
Table 13
Serial Interrupt Request Flag (IFS: $003, Bit 2)
IFS
Interrupt Request
0
No
1
Yes
Serial Interrupt Mask (IMS: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial
interrupt request flag, as listed in table 14.
Table 14
Serial Interrupt Mask (IMS: $003, Bit 3)
Mask IMS
Interrupt Request
0
Enabled
1
Disabled (masked)
A/D Interrupt Request Flag (IFAD: $003, Bit 0): Set at the completion of A/D conversion, as listed in
table 15.
Table 15
A/D Interrupt Request Flag (IFAD: $003, Bit 0)
IFAD
Interrupt Request
0
No
1
Yes
A/D Interrupt Mask (IMAD: $003, Bit 1): Prevents (masks) an interrupt request caused by the A/D
interrupt request flag, as listed in table 16.
Table 16
A/D Interrupt Mask (IMAD: $003, Bit 1)
IMAD
Interrupt Request
0
Enabled
1
Disabled (masked)
23
HD404358 Series
Operating Modes
The MCU has three operating modes as shown in table 17. The operations in each mode are listed in tables
18 and 19. Transitions between operating modes are shown in figure 11.
Table 17
Operating Modes and Clock Status
Mode Name
Active
Standby
Stop
Activation method
RESET cancellation,
SBY instruction
interrupt request, STOPC
cancellation in stop mode
STOP instruction
Status
OP
Stopped
System
oscillator
OP
RESET input, STOP/ SBY RESET input, interrupt
instruction
request
Cancellation
method
RESET input, STOPC
input in stop mode
Note: OP implies in operation
Table 18
Operations in Low-Power Dissipation Modes
Function
Stop Mode
Standby Mode
CPU
Reset
Retained
RAM
Retained
Retained
Timer A
Reset
OP
Timer B
Reset
OP
Timer C
Reset
OP
Serial
Reset
OP
A/D
Reset
OP
I/O
Reset
Retained
Note: OP implies in operation
Table 19
I/O Status in Low-Power Dissipation Modes
Output
Input
Standby Mode
Stop Mode
Active Mode
RA 1
—
—
Input enabled
R0–D 8, R0–R4,
Retained or output of
peripheral functions
High impedance
Input enabled
R8,
24
HD404358 Series
Reset by
RESET input or
by watchdog timer
RAME = 0
RESET 1
øCPU: Stop
RESET 2
Active
mode
Standby mode
fOSC: Oscillate
RAME = 1
SBY
instruction
Interrupt
øPER: fcyc
fOSC: Oscillate
øCPU: fcyc
STOPC
Stop mode
STOP
instruction
øPER: fcyc
fOSC: Stop
øCPU: Stop
øPER: Stop
fOSC: Main oscillation frequency
fcyc:
fOSC/4
øCPU: System clock
øPER: Clock for other peripheral
functions
Figure 11 MCU Status Transitions
Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC 1
and OSC2.
Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.
The MCU enters standby mode when the SBY instruction is executed in active mode.
Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation
in standby mode is shown in figure 12.
25
HD404358 Series
Stop
Standby
Oscillator: Stop
Peripheral clocks: Stop
All other clocks: Stop
Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop
No
RESET = 0?
Yes
No
RESET = 0?
Yes
IF0 • IMO = 1?
No
No
STOPC = 0?
Yes
IF1 • IM1 = 1?
No
Yes
Yes
IFTA • IMTA
= 1?
Yes
RAME = 1
RAME = 0
No
IFTB •
IMTB = 1?
Yes
No
IFTC •
IMTC = 1?
Yes
No
IFAD •
IMAD = 1?
Yes
No
IFS •
IMS = 1?
No
Yes
Restart
processor clocks
Restart
processor clocks
Execute
next instruction
No
Reset MCU
IF = 1,
IM = 0, and
IE = 1?
Execute
next instruction
Yes
Accept interrupt
Figure 12 MCU Operation Flowchart
Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops.
Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC
must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When
the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,
but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.
26
,
HD404358 Series
Stop mode
Oscillator
Internal
clock
RESET
or STOPC
tres
tres ≥ tRC (stabilization period)
STOP instruction execution
Figure 13 Timing of Stop Mode Cancellation
Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by inputting STOPC
as well as by R ESET. In either case, the MCU starts instruction execution from the starting address
(address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs
between cancellation by STOPC and by RESET. When stop mode is cancelled by R ESET, RAME = 0;
when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop
mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop
mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is
used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the
beginning of the program.
MCU Operation Sequence: The MCU operates in the sequence shown in figure 15. It is reset by an
asynchronous RESET input, regardless of its status.
The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.
Power on
RESET = 0 ?
No
Yes
RAME = 0
MCU
operation
cycle
Reset MCU
Figure 14 MCU Operating Sequence (Power On)
27
HD404358 Series
MCU operation
cycle
IF = 1?
No
Instruction
execution
Yes
SBY/STOP
instruction?
Yes
No
IM = 0 and
IE = 1?
Yes
IE ← 0
Stack ← (PC),
(CA),
(ST)
No
Low-power mode
operation cycle
IF:
IM:
IE:
PC:
CA:
ST:
PC ← Next
location
PC ← Vector
address
Interrupt request flag
Interrupt mask
Interrupt enable flag
Program counter
Carry flag
Status flag
Figure 15 MCU Operating Sequence (MCU Operation Cycle)
28
HD404358 Series
Low-power mode
operation cycle
IF = 1 and
IM = 0?
No
Yes
Stop mode
Standby mode
No
IF = 1 and
IM = 0?
Yes
No
STOPC = 0?
Yes
Hardware NOP
execution
Hardware NOP
execution
RAME = 1
PC ← Next
Iocation
PC ← Next
Iocation
Reset MCU
Instruction
execution
MCU operation
cycle
For IF and IM operation, refer to figure 12.
Figure 16 MCU Operating Sequence (Low-Power Mode Operation)
29
HD404358 Series
Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 17. As shown in table 20, a ceramic
oscillator or crystal oscillator can be connected to OSC1 and OSC2. The system oscillator can also be
operated by an external clock. See figure 18 for the layout of crystal and ceramic oscillator.
OSC2
1/4
System fOSC
division
oscillator
circuit
fcyc
tcyc
Timing
generator
circuit
øCPU
CPU with ROM,
RAM, registers,
flags, and I/O
øPER
Peripheral
function
interrupt
OSC1
Figure 17 Clock Generation Circuit
TEST
RESET
OSC1
OSC2
GND
AVSS
Figure 18 Typical Layout of Crystal and Ceramic Oscillator
30
HD404358 Series
Table 20
Oscillator Circuit Examples
Circuit Configuration
External clock
operation
Ceramic oscillator
(OSC1, OSC 2)
Circuit Constants
External
oscillator
OSC 1
Open
OSC 2
Ceramic oscillator:
C1
CSA4.00MG
OSC1
Ceramic
(Murata)
Rf
Rf = 1 MΩ ±20%
C1 = C2 = 30 pF ±20%
OSC2
C2
GND
Crystal oscillator
(OSC1, OSC 2)
Rf = 1 MΩ ±20%
C1
C1 = C2 = 10 to 22 pF ±20%
OSC1
Crystal
Crystal: Equivalent to circuit
shown below
Rf
C0 = 7 pF max.
OSC2
RS = 100 Ω max.
C2
GND
L
CS
OSC1
RS
OSC2
CO
Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray
capacitance of the board, the user should consult with the crystal or ceramic oscillator
manufacturer to determine the circuit parameters.
2. Wiring among OSC1, OSC 2, and elements should be as short as possible, and must not cross
other wiring (see figure 18).
31
HD404358 Series
Input/Output
The MCU has 33 input/output pins (D0–D8, R0–R4, R8) and an input pin (RA1). The features are described
below.
• Four pins (R2 0–R2 3) are high-current (15 mA max) input/output with intermediate voltage NMOS open
drain pins.
• The D0–D4, R0, R3–R4 input/output pins are multiplexed with peripheral function pins such as for the
timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port
setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output
selection are automatically switched according to the setting.
• Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.
• Peripheral function output pins are CMOS output pins. Only the R02/SO pin can be set to NMOS opendrain output by software.
• In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output
pins are in high-impedance state.
• Each input/output pin except for R2 has a built-in pull-up MOS, which can be individually turned on or
off by software.
I/O buffer configuration is shown in figure 19, programmable I/O circuits are listed in table 21, and I/O pin
circuit types are shown in table 22.
Table 21
Programmable I/O Circuits
MIS3 (bit 3 of MIS)
0
DCD, DCR
0
PDR
0
1
0
1
0
1
0
1
PMOS
—
—
—
On
—
—
—
On
NMOS
—
—
On
—
—
—
On
—
—
—
—
—
—
On
—
On
CMOS buffer
Pull-up MOS
Note: — indicates off status.
32
1
1
0
1
HD404358 Series
HLT
Pull-up control signal
VCC
MIS3
VCC
Pull-up
MOS
Buffer control signal
DCD, DCR
Output data
PDR
Input data
Input control signal
Figure 19 I/O Buffer Configuration
33
HD404358 Series
Table 22
Circuit Configurations of I/O Pins
I/O Pin Type
Input/output
pins
Circuit
Pins
VCC
Pull-up control signal
Buffer control
signal
VCC
HLT
D0–D 8,
MIS3
R0 0, R0 1, R0 3
R1 0–R1 3,
DCR, DCD
Output data
PDR
R3 0–R3 3,
R4 0–R4 3,
R8 0–R8 3
Input data
Input control signal
HLT
VCC
VCC
Pull-up control signal
Buffer control
signal
Output data
R0 2
MIS3
DCR
MIS2
PDR
Input data
Input control signal
HLT
R2 0–R2 3
DCR
Output data
PDR
Input data
Input control signal
Input pins
RA 1
Input data
Input control signal
Peripheral
Input/output
function pins pins
VCC
HLT
VCC
Pull-up control signal
Output data
Input data
Notes on next page.
34
SCK
MIS3
SCK
SCK
HD404358 Series
I/O Pin Type
Peripheral
function pins
Circuit
Pins
Output pins
VCC
HLT
VCC
Pull-up control signal
MIS3
PMOS control
signal
Output data
VCC
VCC
Output data
Input pins
MIS2
SO
HLT
Pull-up control signal
SO
TOC, BUZZ
MIS3
TOC, BUZZ
SI,
VCC
HLT
INT0, INT1,
MIS3
PDR
EVNB, STOPC
Input data
VCC
AN 0–AN 7
HLT
MIS3
PDR
A/D input
Input control signal
Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT
signal goes low, and input/output pins enter the high-impedance state.
2. The HLT signal is 1 in active and standby modes.
35
HD404358 Series
Evaluation Chip Set and ZTAT/Mask ROM Product Differences
As shown in figure 20, the NMOS intermediate breakdown voltage open drain pin circuit in the evaluation
chip set differs from that used in the ZTAT microcomputer and built-in mask ROM microcomputer
products.
Please note that although these outputs in the ZTAT microcomputer and built-in mask ROM
microcomputer products can be set to high impedance by the combinations shown in table 23, these outputs
cannot be set to high impedance in the evaluation chip set.
Table 23
Program Control of High Impedance States
Register
Set Value
DCR
0
1
PDR
*
1
Notes: * An asterisk indicates that the value may be either 0 or 1 and has no influence on circuit operation.
This applies to the ZTAT and built-in mask ROM microcomputer NMOS open drain pins.
HLT
VCC
MIS3
VCC
DCR
PDR
CPU input
Input control signal
Evaluation Chip Set Circuit Structure
HLT
DCR
PDR
CPU input
Input control signal
ZTAT and Built-in Mask ROM Microcomputer Circuit Structure
Figure 20 NMOS Intermediate Breakdown Voltage Open Drain Pin Circuits
36
HD404358 Series
D Port (D 0–D8): Consist of 9 input/output pins addressed by one bit.
Pins D0–D 8 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.
Output data is stored in the port data register (PDR) for each pin. All pins D0–D8 are tested by the TD and
TDD instructions.
The on/off statuses of the output buffers are controlled by D-port data control registers (DC D0–DC D2: $02C–
$02E) that are mapped to memory addresses (figure 21).
Pins D0–D2, D4 are multiplexed with peripheral function pins INT0, INT1, EVNB, and STOPC,
respectively. The peripheral function modes of these pins are selected by bits 0–3 (PMRB0–PMRB3) of
port mode register B (PMRB: $024) (figure 22).
Pin D3 is multiplexed with peripheral function pin BUZZ. The peripheral function mode of this pin is
selected by bit 3 (PMRA3) of port mode register A (PMRA: $004) (figure 23).
R Ports (R0 0–R43, R8): 24 input/output pins addressed in 4-bit units. Data is input to these ports by the
LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored
in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are
controlled by R-port data control registers (DCR0–DCR4: $030–$034, DCR8: $038) that are mapped to
memory addresses (figure 21).
Pin R0 0 is multiplexed with peripheral function pin SCK. The peripheral function mode of this pin is
selected by bit 3 (SMR3) of serial mode register (SMR: $005) (figure 24).
Pins R01–R0 3 are multiplexed with peripheral pins SI, SO and TOC, respectively. The peripheral function
modes of these pins are selected by bits 0–2 (PMRA0–PMRA2) of port mode register A (PMRA: $004), as
shown in figures 23.
Port R3 is multiplexed with peripheral function pins AN 0–AN 3, respectively. The peripheral function
modes of these pins can be selected by individual pins, by setting A/D mode register 1 (AMR1: $019)
(figure 25).
Ports R4 is multiplexed with peripheral function pins AN4–AN 7, respectively. The peripheral function
modes of these pins can be selected in 4-pin units by setting bit 1 (AMR21) of A/D mode register 2
(AMR2: $01A) (figure 26).
Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each
input/output pin. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous
register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data
register (PDR) of the corresponding pin—enabling on/off control of that pin alone (table 21 and figure 27).
The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to V CC by
their pull-up MOS transistors or by resistors of about 100 kΩ.
37
HD404358 Series
Data control register
(DCD0 to 2: $02C to $02E)
(DCR0 to 4: $030 to $034, DCR8: $038)
DCD0, DCD2, DCR0 to DCR4, DCR8
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
DCD03,
DCD13,
DCR03–
DCR43,
DCR83
DCD02,
DCD12,
DCR02–
DCR42,
DCR82
DCD01,
DCD11,
DCR01–
DCR41,
DCR81
DCD00–
DCD20,
DCR00–
DCR40,
DCR80
Bit name
Bits 0 to 3
CMOS Buffer On/Off Selection
0
Off (high-impedance)
1
On
Correspondence between ports and DCD/DCR bits
Register Name
Bit 3
Bit 2
Bit 1
Bit 0
DCD0
D3
D2
D1
D0
DCD1
D7
D6
D5
D4
DCD2
Not used
Not used
Not used
D8
DCR0
R03
R02
R01
R00
DCR1
R13
R12
R11
R10
DCR2
R23
R22
R21
R20
DCR3
R33
R32
R31
R30
DCR4
R43
R42
R41
R40
DCR8
R83
R82
R81
R80
Figure 21 Data Control Registers (DCD, DCR)
38
HD404358 Series
Port mode register B (PMRB: $024)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
PMRB3* PMRB2 PMRB1 PMRB0
PMRB0
PMRB2 D2/EVNB Mode Selection
0
D2
1
EVNB
0
D4
1
STOPC
0
D0
1
INT0
PMRB1
PMRB3 D4/STOPC Mode Selection
D0/INT0 Mode Selection
D1/INT1 Mode Selection
0
D1
1
INT1
Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not
reset but retains its value.
Figure 22 Port Mode Register B (PMRB)
Port mode register A (PMRA: $004)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
PMRA3
PMRA2 PMRA1 PMRA0
PMRA0
PMRA2
R03/TOC Mode Selection
0
R03
1
TOC
PMRA3
0
D3
1
BUZZ
0
R02
1
SO
PMRA1
D3/BUZZ Mode Selection
R02/SO Mode Selection
R01/SI Mode Selection
0
R01
1
SI
Figure 23 Port Mode Register A (PMRA)
39
HD404358 Series
Serial mode register (SMR: $005)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
SMR3
SMR2
SMR1
SMR0
Bit name
R00/SCK
Mode Selection
SMR3
0
R00
1
SCK
SMR2
SMR1
SMR0
Transmit clock selection.
Refer to figure 55 in the
serial interface section.
Figure 24 Serial Mode Register (SMR)
A/D mode register 1 (AMR1: $019)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
AMR13
AMR12
AMR11
AMR10
Bit name
AMR10
AMR12
R32/AN2 Mode Selection
0
R32
1
AN2
AMR13
0
R33
1
AN3
0
R30
1
AN0
AMR11
R33/AN3 Mode Selection
R31/AN1 Mode Selection
0
R31
1
AN1
Figure 25 A/D Mode Register 1 (AMR1)
40
R30/AN0 Mode Selection
HD404358 Series
A/D mode register 2 (AMR2: $01A)
Bit
3
2
Initial value
—
—
0
0
Read/Write
—
—
W
W
Bit name
0
1
Not used Not used AMR21
AMR20
AMR20
Conversion Time
0
34tcyc
1
67tcyc
AMR21
R4/AN4–AN7 Pin Selection
0
R4
1
AN4–AN7
Figure 26 A/D Mode Register 2 (AMR2)
Miscellaneous register (MIS: $00C)
Bit
3
2
1
0
Initial value
0
0
—
—
—
—
Read/Write
Bit name
W
W
MIS3
MIS2
MIS3
Pull-Up MOS
On/Off Selection
0
Pull-up MOS off
1
Pull-up MOS on
(refer to table 21)
Not used Not used
MIS2
CMOS Buffer
On/Off Selection
for Pin R02/SO
0
PMOS active
1
PMOS off
Figure 27 Miscellaneous Register (MIS)
41
HD404358 Series
Prescalers
The MCU has a built-in prescaler labeled as prescaler S (PSS).
The prescalers operating conditions are listed in table 24, and the prescalers output supply is shown in
figure 28. The timers A–C input clocks except external events, the serial transmit clock except the external
clock are selected from the prescaler outputs, depending on corresponding mode registers.
Prescaler Operation
Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset,
prescaler S divides the system clock.
Table 24
Prescaler Operating Conditions
Prescaler
Input Clock
Reset Conditions
Stop Conditions
Prescaler S
System clock
MCU reset
MCU reset, stop mode
Timer A
Timer B
System
clock
Clock
selector
Prescaler S
Timer C
Serial
Alarm output
circuit
Figure 28 Prescaler Output Supply
42
HD404358 Series
Timers
The MCU has four timer/counters (A to C).
• Timer A: Free-running timer
• Timer B: Multifunction timer
• Timer C: Multifunction timer
Timer A is an 8-bit free-running timer. Timers B and C are 8-bit multifunction timers, whose functions are
listed in table 25. The operating modes are selected by software.
Table 25
Timer Functions
Functions
Clock source
Timer functions
Timer output
Timer A
Timer B
Timer C
Prescaler S
Available
Available
Available
External event
—
Available
—
Free-running
Available
Available
Available
Event counter
—
Available
—
Reload
—
Available
Available
Watchdog
—
—
Available
Input capture
—
Available
—
PWM
—
—
Available
Note: — implies not available.
43
HD404358 Series
Timer A
Timer A Functions: Timer A has the following functions.
• Free-running timer
The block diagram of timer A is shown in figure 29.
Timer
counter A
(TCA) Overflow
Clock
System
clock
øPER
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
÷ 2048
Selector
Prescaler S (PSS)
Internal data bus
Timer A interrupt
request flag
(IFTA)
3
Timer mode
register A
(TMA)
Figure 29 Timer A Block Diagram
Timer A Operations:
• Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:
$008).
Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied
to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow
sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after
reset to $00, and therefore it generates regular interrupts every 256 clocks.
Registers for Timer A Operation: Timer A operating modes are set by the following registers.
• Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode
and input clock source as shown in figure 30.
44
HD404358 Series
Timer mode register A (TMA: $008)
Bit
3
2
1
0
Initial value
—
0
0
0
Read/Write
Bit name
—
W
W
W
Not used
TMA2
TMA1
TMA0
Source
Input Clock
TMA2 TMA1 TMA0 Prescaler Frequency
0
0
1
1
0
1
0
PSS
2048tcyc
1
PSS
1024tcyc
0
PSS
512tcyc
1
PSS
128tcyc
0
PSS
32tcyc
1
PSS
8tcyc
0
PSS
4tcyc
1
PSS
2tcyc
Figure 30 Timer Mode Register A (TMA)
45
HD404358 Series
Timer B
Timer B Functions: Timer B has the following functions.
• Free-running/reload timer
• External event counter
• Input capture timer
The block diagram for each operation mode of timer B is shown in figures 31 and 32.
Interrupt request
flag of timer B
(IFTB)
Timer read
register B upper
(TRBU)
Timer read
register B lower
(TRBL)
Free-running
timer control
signal
Timer write
register B lower
(TWBL)
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
Edge
detector
ø PER
2
Overflow
Timer write
register B upper
(TWBU)
Selector
EVNB
System
clock
Timer counter B
(TCB)
3
Prescaler S (PSS)
Timer mode
register B1
(TMB1)
Edge detection control signal
Timer mode
register B2
(TMB2)
Figure 31 Timer B Free-Running and Reload Operation Block Diagram
46
Internal data bus
Clock
HD404358 Series
Input capture
status flag
(ICSF)
Interrupt request
flag of timer B
(IFTB)
Input capture
error flag
(ICEF)
Error
controller
Timer read
register B upper
(TRBU)
Timer read
register B lower
(TRBL)
Read
signal
Edge
detector
Clock
Timer counter B
(TCB)
Overflow
Input capture
timer control
signal
Selector
3
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
System
clock
ø PER
2
Internal data bus
EVNB
Timer mode
register B1
(TMB1)
Prescaler S (PSS)
Edge detection control signal
Timer mode
register B2
(TMB2)
Figure 32 Timer B Input Capture Operation Block Diagram
47
HD404358 Series
Timer B Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register B1 (TMB1: $009).
Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by
software and incremented by one at each clock input. If an input clock is applied to timer B after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is
initialized to its initial value set in timer write register B; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• External event counter operation: Timer B is used as an external event counter by selecting the external
event input as an input clock source. In this case, pin D2/EVNB must be set to EVNB by port mode
register B (PMRB: $024).
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by timer mode register 2 (TMB2: $026). When both rising and falling
edges detection is selected, the time between the falling edge and rising edge of input signals must be
2tcyc or longer.
Timer B is incremented by one at each detection edge selected by timer mode register 2 (TMB2: $026).
The other operation is basically the same as the free-running/reload timer operation.
• Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVNB.
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by timer mode register 2 (TMB2: $026).
When a trigger edge is input to EVNB, the count of timer B is written to timer read register B (TRBL:
$00A, TRBU: $00B), and the timer B interrupt request flag (IFTB: $002, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer B is reset to $00, and then incremented again. While ICSF
is set, if a trigger input edge is applied to timer B, or if timer B generates an overflow, the input capture
error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0.
Registers for Timer B Operation: By using the following registers, timer B operation modes are selected
and the timer B count is read and written.
Timer mode register B1 (TMB1: $009)
Timer mode register B2 (TMB2: $026)
Timer write register B (TWBL: $00A, TWBU: $00B)
Timer read register B (TRBL: $00A, TRBU: $00B)
Port mode register B (PMRB: $024)
• Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in figure 33. It is reset to $0
by MCU reset.
48
HD404358 Series
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register B1 write instruction. Setting timer B’s initialization by writing to timer
write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.
When selecting the input capture timer operation, select the internal clock as the input clock source.
Timer mode register B1 (TMB1: $009)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TMB13
TMB12
TMB11
TMB10
Bit name
TMB13
Free-Running/Reload
Timer Selection
0
Free-running timer
1
Reload timer
Input Clock Period and Input
Clock Source
TMB12
TMB11
TMB10
0
0
0
2048tcyc
1
512tcyc
0
128tcyc
1
32tcyc
0
8tcyc
1
4tcyc
0
2tcyc
1
D2/EVNB (external event input)
1
1
0
1
Figure 33 Timer Mode Register B1 (TMB1)
49
HD404358 Series
• Timer mode register B2 (TMB2: $026): Three-bit write-only register that selects the detection edge of
signals input to pin EVNB and input capture operation as shown in figure 34. It is reset to $0 by MCU
reset.
Timer mode register B2 (TMB2: $026)
Bit
3
2
1
0
Initial value
—
0
0
0
—
W
Read/Write
Bit name
Not used TMB22
W
W
TMB21
TMB20
TMB21
TMB20
0
0
No detection
1
Falling edge detection
0
Rising edge detection
1
Rising and falling edge detection
1
EVNB Edge Detection Selection
Free-Running/Reload and Input Capture Selection
TMB22
0
Free-running/reload
1
Input capture
Figure 34 Timer Mode Register B2 (TMB2)
• Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit
(TWBL) and the upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit
value is invalid (figures 35 and 36).
Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case,
the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the
timer B value. Timer B is initialized to the value in timer write register B at the same time the upper
digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value
needs no change, writing only to the upper digit initializes timer B.
Timer write register B (lower digit) (TWBL: $00A)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TWBL3
TWBL2
TWBL1
TWBL0
Bit name
Figure 35 Timer Write Register B Lower Digit (TWBL)
50
HD404358 Series
Timer write register B (upper digit) (TWBU: $00B)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
W
W
W
W
TWBU3
TWBU2
TWBU1
TWBU0
Figure 36 Timer Write Register B Upper Digit (TWBU)
• Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit
(TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 37 and 38).
The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained,
and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading
TRBL, the count of timer B when TRBU is read can be obtained.
When the input capture timer operation is selected and if the count of timer B is read after a trigger is
input, either the lower or upper digit can be read first.
Timer read register B (lower digit) (TRBL: $00A)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRBL3
TRBL2
TRBL1
TRBL0
Figure 37 Timer Read Register B Lower Digit (TRBL)
Timer read register B (upper digit) (TRBU: $00B)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRBU3
TRBU2
TRBU1
TRBU0
Figure 38 Timer Read Register B Upper Digit (TRBU)
51
HD404358 Series
• Port mode register B (PMRB: $024): Write-only register that selects D2/EVNB pin function as shown in
figure 39. It is reset to $0 by MCU reset.
Port mode register B (PMRB: $024)
Bit
3
2
1
0
Initial value
0
0
0
0
W
W
W
W
Read/Write
Bit name
PMRB3* PMRB2 PMRB1 PMRB0
PMRB0
PMRB2 D2/EVNB Mode Selection
0
D2
1
EVNB
0
D4
1
STOPC
0
D0
1
INT0
PMRB1
PMRB3 D4/STOPC Mode Selection
D0/INT0 Mode Selection
D1/INT1 Mode Selection
0
D1
1
INT1
Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not
reset but retains its value.
Figure 39 Port Mode Register B (PMRB)
52
HD404358 Series
Timer C
Timer C Functions: Timer C has the following functions.
• Free-running/reload timer
• Watchdog timer
• Timer output operation (PWM output)
The block diagram of timer C is shown in figure 40.
System reset signal
Watchdog on
flag (WDON)
Interrupt request
flag of timer C
(IFTC)
Watchdog timer
controller
Timer read register C upper (TRCU)
TOC
Timer output
control logic
Timer read
register C lower
(TRCL)
Clock
Timer
output
control
signal
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
÷ 2048
Selector
System ø PER
clock
Overflow
Internal data bus
Timer counter C
(TCC)
Timer write
register C upper
(TWCU)
Free-running
timer control
signal
Timer write
register C lower
(TWCL)
3
Prescaler S (PSS)
Timer mode
register C (TMC)
Port mode
register A (PMRA)
Figure 40 Timer C Block Diagram
53
HD404358 Series
Timer C Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C (TMC: $00D).
Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. The watchdog timer operation flowchart is
shown in figure 41. Program run can be controlled by initializing timer C by software before it reaches
$FF.
$FF + 1
Overflow
Timer C
count value
$00
CPU
operation
Time
Normal
operation
Timer C
clear
Normal
operation
Timer C
clear
Program
runaway
Reset
Normal
operation
Figure 41 Watchdog Timer Operation Flowchart
• Timer output operation: The PWM output modes can be selected for timer C by setting port mode
register A (PMRA: $004).
By selecting the timer output mode, pin R03/TOC is set to TOC. The output from TOC is reset low by
MCU reset.
PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output
function. The output waveform differs depending on the contents of timer mode register C (TMC:
$00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in
figure 42.
54
HD404358 Series
T × (N + 1)
TMC3 = 0
(free-running
timer)
T
T × 256
TMC3 = 1
(reload timer)
T × (256 – N)
Notes:
T: Input clock period supplied to counter. (The clock source and system clock division
ratio are determined by timer mode register C.)
N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.)
Figure 42 PWM Output Waveform
Notes on Use
When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 26. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.
In this case, the lower digit (TWCL) must be written to first, bit writing only to the lower digit does not
change the timer C value. Timer C is changed to the value in timer write register B at the same time the
upper digit (TWCU) is written to.
Table 26
PWM Output Following Update of Timer Write Register
PWM Output
Mode
Timer Write Register is Updated
during High PWM Output
Reload
Timer write
register
updated to
value N
T
Timer Write Register is Updated
during Low PWM Output
Interrupt
request
T × (255 – N)
T
Timer write
register
updated to
value N
Interrupt
request
T
T × (255 – N)
T
55
HD404358 Series
Registers for Timer C Operation: By using the following registers, timer C operation modes are selected
and the timer C count is read and written.
Timer mode register C (TMC: $00D)
Port mode register A (PMRA: $004)
Timer write register C (TWCL: $00E, TWCU: $00F)
Timer read register C (TRCL: $00E, TRCU: $00F)
• Timer mode register C (TMC: $00D): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in figure 43. It is reset to $0
by MCU reset.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C write instruction. Setting timer C’s initialization by writing to timer
write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.
Timer mode register C (TMC: $00D)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TMC3
TMC2
TMC1
TMC0
Bit name
TMC3
Free-Running/Reload
Timer Selection
0
Free-running timer
1
Reload timer
TMC2
TMC1
TMC0
0
0
0
2048tcyc
1
1024tcyc
0
512tcyc
1
128tcyc
0
32tcyc
1
8tcyc
0
4tcyc
1
2tcyc
1
1
0
1
Input Clock Period
Figure 43 Timer Mode Register C (TMC)
56
HD404358 Series
• Port mode register A (PMRA: $004): Write-only register that selects R03/TOC pin function as shown in
figure 44. It is reset to $0 by MCU reset.
Port mode register A (PMRA: $004)
Bit
3
2
1
0
Initial value
0
0
0
0
W
W
W
Read/Write
W
Bit name
PMRA3
PMRA2 PMRA1 PMRA0
PMRA0
PMRA2
R03/TOC Mode Selection
0
R03
1
TOC
PMRA3
D3
1
BUZZ
0
R02
1
SO
PMRA1
D3/BUZZ Mode Selection
0
R02/SO Mode Selection
R01/SI Mode Selection
0
R01
1
SI
Figure 44 Port Mode Register A (PMRA)
• Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of the lower digit
(TWCL) and the upper digit (TWCU) as shown in figures 45 and 46. The operation of timer write
register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).
Timer write register C (lower digit) (TWCL: $00E)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
W
W
W
W
TWCL3
TWCL2
TWCL1
TWCL0
Figure 45 Timer Write Register C Lower Digit (TWCL)
Timer write register C (upper digit) (TWCU: $00F)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
W
W
W
W
TWCU3
TWCU2
TWCU1
TWCU0
Figure 46 Timer Write Register C Upper Digit (TWCU)
57
HD404358 Series
• Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of the lower digit
(TRCL) and the upper digit (TRCU) that holds the count of the timer C upper digit (figures 47 and 48).
The operation of timer read register C is basically the same as that of timer read register B (TRBL:
$00A, TRBU: $00B).
Timer read register C (lower digit) (TRCL: $00E)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRCL3
TRCL2
TRCL1
TRCL0
Figure 47 Timer Read Register C Lower Digit (TRCL)
Timer read register C (upper digit) (TRCU: $00F)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRCU3
TRCU2
TRCU1
TRCU0
Figure 48 Timer Read Register C Upper Digit (TRCU)
58
HD404358 Series
Alarm Output Function
BUZZ
Alarm output
control signal
Alarm output
controller
System ø PER
clock
2
Port mode
register C
(PMRC)
÷ 2048
÷ 1024
÷ 512
÷ 256
Selector
Port mode
register A
(PMRA)
Internal data bus
The MCU has a built-in pulse output function called BUZZ. The pulse frequency can be selected from the
prescaler S’s outputs, and the output frequency depends on the state of port mode register C (PMRC: $025).
The duty cycle of the pulse output is fixed at 50%.
Prescaler S (PSS)
Figure 49 Alarm Output Function Block Diagram
Port Mode Register C (PMRC: $025): Four-bit write-only register that selects the alarm frequencies as
shown in figure 50. It is reset to $0 by MCU reset.
Port mode register C (PMRC: $025)
Bit
3
0
0
0
Undefined
0
Read/Write
W
W
W
W
PMRC3
PMRC2
PMRC1
PMRC0
PMRC3
1
1
Initial value
Bit name
0
2
PMRC2
System Clock Divisor
PMRC0
Serial Clock Division Ratio
0
÷2048
0
Prescaler output divided by 2
1
÷1024
1
Prescaler output divided by 4
0
÷512
1
÷256
PMRC1
Output Level Control in Idle States
0
Low level
1
High level
Figure 50 Port Mode Register C (PMRC)
59
HD404358 Series
Port Mode Register A (PMRA: $004): Four-bit write-only register that selects D3/BUZZ pin function as
shown in figure 44. It is reset to $0 by MCU reset.
Serial Interface
The serial interface serially transfers and receives 8-bit data, and includes the following features.
• Multiple transmit clock sources
 External clock
 Internal prescaler output clock
 System clock
• Output level control in idle states
Five registers, an octal counter, and a selector are also configured for the serial interface as follows.
Serial data register (SRL: $006, SRU: $007)
Serial mode register (SMR: $005)
Port mode register A (PMRA: $004)
Port mode register C (PMRC: $025)
Miscellaneous register (MIS: $00C)
Octal counter (OC)
Selector
The block diagram of the serial interface is shown in figure 51.
60
HD404358 Series
Octal
counter (OC)
SO
Serial interrupt
request flag
(IFS)
Idle
controller
SCK
I/O
controller
SI
Clock
1/2
Selector
1/2
Transfer
control
signal
Internal data bus
Serial data
register (SR)
Selector
÷2
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
3
ø PER
System
clock
Prescaler S (PSS)
Serial mode
register
(SMR)
Port mode
register C
(PMRC)
Figure 51 Serial Interface Block Diagram
Serial Interface Operation
Selecting and Changing the Operating Mode: Table 27 lists the serial interface’s operating modes. To
select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and the
serial mode register (SMR: $005) settings; to change the operating mode, always initialize the serial
interface internally by writing data to the serial mode register. Note that the serial interface is initialized by
writing data to the serial mode register. Refer to the following Serial Mode Register section for details.
Table 27
Serial Interface Operating Modes
SMR
PMRA
Bit 3
Bit 1
Bit 0
Operating Mode
1
0
0
Continuous clock output mode
1
Transmit mode
0
Receive mode
1
Transmit/receive mode
1
61
HD404358 Series
Pin Setting: The R00/SCK pin is controlled by writing data to the serial mode register (SMR: $005). The
R0 1/SI and R0 2/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the
following Registers for Serial Interface section for details.
Transmit Clock Source Setting: The transmit clock source is set by writing data to the serial mode
register (SMR: $005) and port mode register C (PMRC: $025). Refer to the following Registers for Serial
Interface section for details.
Data Setting: Transmit data is set by writing data to the serial data register (SRL: $006, SRU, $007).
Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the
transmit clock and is input from or output to an external system.
The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output
level control in idle states is performed.
Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000
by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit
clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000,
the serial interrupt request flag (IFS: $003, bit 2) is set, and the transfer stops.
When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4tcyc
to 8192tcyc by setting bits 0 to 2 (SMR0– SMR2) of serial mode register (SMR: $005) and bit 0 (PMRC0)
of port mode register C (PMRC: $025) as listed in table 28.
Table 28
Serial Transmit Clock (Prescaler Output)
PMRC
SMR
Bit 0
Bit 2
Bit 1
Bit 0
Prescaler Division Ratio
Transmit Clock Frequency
0
0
0
0
÷ 2048
4096t cyc
1
÷ 512
1024t cyc
0
÷ 128
256t cyc
1
÷ 32
64t cyc
0
÷8
16t cyc
1
÷2
4t cyc
0
÷ 4096
8192t cyc
1
÷ 1024
2048t cyc
0
÷ 256
512t cyc
1
÷ 64
128t cyc
0
÷ 16
32t cyc
1
÷4
8t cyc
1
1
1
0
0
0
1
1
62
0
HD404358 Series
Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 52.
STS wait state
Transmit clock wait state
Transfer state
Continuous clock output state (only in internal clock mode)
• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 59). In STS
wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is
then executed (01, 11), the serial interface enters transmit clock wait state.
• Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge
of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments
the octal counter, shifts the serial data register, and enters the serial interface in transfer state. However,
note that if continuous clock output mode is selected in internal clock mode, the serial interface does not
enter transfer state but enters continuous clock output state (17).
The serial interface enters STS wait state by writing data to the serial mode register (SMR: $005) (04,
14) in transmit clock wait state.
• Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the
eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the
octal counter to 000, and the serial interface enters another state. When the STS instruction is executed
(05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is
entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.
In transfer state, writing data to the serial mode register (SMR: $005) (06, 16) initializes the serial
interface, and STS wait state is entered.
If the state changes from transfer to another state, the serial interrupt request flag (IFS: $003, bit 2) is set
by the octal counter that is reset to 000.
• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the SCK pin.
When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If the serial mode register (SMR: $005) is written to in continuous clock output mode (18), STS wait
state is entered.
63
HD404358 Series
External clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
SMR write
04
00
06
01
MCU reset
SMR write (IFS ← 1)
STS instruction
02 Transmit clock
Transmit clock wait state
(Octal counter = 000)
03
8 transmit clocks
Transfer state
(Octal counter = 000)
05
STS instruction (IFS ← 1)
Internal clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
SMR write
18
Continuous clock output state
(PMRA 0, 1 = 0, 0)
10
13
SMR write
14
11
STS instruction
MCU reset
8 transmit clocks
16 SMR write (IFS← 1)
Transmit clock 17
12 Transmit clock
Transmit clock wait state
(Octal counter = 000)
Transfer state
(Octal counter = 000)
15
STS instruction (IFS ← 1)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 52 Serial Interface State Transitions
Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state,
the output level of the SO pin can be controlled by setting bit 1 (PMRC1) of port mode register C (PMRC:
$025) to 0 or 1. The output level control example is shown in figure 53. Note that the output level cannot be
controlled in transfer state.
64
,
HD404358 Series
Transmit clock
wait state
State
STS wait state
Transmit clock
wait state
Transfer state
STS wait state
MCU reset
Port selection
PMRA write
External clock selection
SMR write
Output level control in
idle states
Dummy write for
state transition
Output level control in
idle states
PMRC write
Data write for transmission
SRL, SRU write
STS instruction
SCK pin (input)
SO pin
Undefined
LSB
MSB
IFS
External clock mode
Flag reset at transfer completion
Transmit clock
wait state
State
STS wait state
Transfer state
STS wait state
MCU reset
Port selection
PMRA write
Internal clock selection
SMR write
Output level control in
idle states
PMRC write
Output level control in
idle states
Data write for transmission
SRL, SRU write
STS instruction
SCK pin (output)
SO pin
Undefined
LSB
MSB
IFS
Internal clock mode
Flag reset at transfer completion
Figure 53 Example of Serial Interface Operation Sequence
65
HD404358 Series
Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 54.
Transfer completion
(IFS ← 1)
Interrupts inhibited
IFS ← 0
SMR write
IFS = 1
Yes
Transmit clock
error processing
No
Normal
termination
Transmit clock error detection flowchart
Transmit clock
wait state
Transmit clock wait state
Transfer state
State
Transfer state
SCK pin (input)
Noise
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit clock
error. When SMR is written,
IFS is set.
SMR write
IFS
Flag set because octal
counter reaches 000
Transmit clock error detection procedure
Figure 54 Transmit Clock Error Detection
66
Flag reset at
transfer completion
HD404358 Series
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer completion processing is performed and IFS is reset, writing to the serial mode
register (SMR: $005) changes the state from transfer to STS wait. At this time IFS is set again, and
therefore the error can be detected.
Notes on Use:
• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to the serial mode
register (SMR: $005) again.
• Serial interrupt request flag (IFS: $003, bit 2) set: If the state is changed from transfer to another by
writing to the serial mode register (SMR: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request
flag, serial mode register write or STS instruction execution must be programmed to be executed after
confirming that the SCK pin is at 1, that is, after executing the input instruction to port R0.
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written by the following registers.
Serial Mode Register (SMR: $005)
Serial Data Register (SRL: $006, SRU: $007)
Port Mode Register A (PMRA: $004)
Port Mode Register C (PMRC: $025)
Miscellaneous Register (MIS: $00C)
Serial Mode Register (SMR: $005): This register has the following functions (figure 55).
• R0 0/SCK pin function selection
• Transmit clock selection
• Prescaler division ratio selection
• Serial interface initialization
Serial mode register (SMR: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.
A write signal input to serial mode register (SMR: $005) discontinues the input of the transmit clock to the
serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed
during data transfer, the serial interrupt request flag (IFS: $003, bit 2) is set.
Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.
67
HD404358 Series
Serial mode register (SMR: $005)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
SMR3
SMR2
SMR1
SMR0
Bit name
SMR3
R00/SCK
Mode Selection
0
R00
1
SCK
Clock Source
Output
Prescaler
Refer to
table 28
0
Output
System clock
—
1
Input
External clock
—
SMR1
SMR0
0
0
0
1
1
Prescaler
Division Ratio
SCK
SMR2
0
1
1
0
0
1
1
Figure 55 Serial Mode Register (SMR)
Port Mode Register C (PMRC: $025): This register has the following functions (figure 56).
• Prescaler division ratio selection
• Output level control in idle states
Port mode register C (PMRC: $025) is a 4-bit write-only register. It cannot be written during data transfer.
By setting bit 0 (PMRC0) of this register, the prescaler division ratio is selected. Bit 0 (PMRC0) can be
reset to 0 by MCU reset. By setting bit 1 (PMRC1), the output level of the SO pin is controlled in idle
states. The output level changes at the same time that PMRC1 is written to.
68
HD404358 Series
Port mode register C (PMRC: $025)
Bit
3
2
1
0
Initial value
0
0
Undefined
0
Read/Write
W
W
W
W
PMRC2
PMRC1
PMRC0
Bit name
PMRC3
PMRC0
Alarm output function.
Refer to figure 50.
Serial Clock Division Ratio
0
Prescaler output divided by 2
1
Prescaler output divided by 4
PMRC1
Output Level Control in Idle States
0
Low level
1
High level
Figure 56 Port Mode Register C (PMRC)
Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 57 and
58).
• Transmission data write and shift
• Receive data shift and read
Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the
transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 59.
Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.
Serial data register (lower digit) (SRL: $006)
Bit
3
Initial value
2
1
0
Undefined Undefined Undefined Undefined
Read/Write
R/W
R/W
R/W
R/W
Bit name
SR3
SR2
SR1
SR0
Figure 57 Serial Data Register (SRL)
69
HD404358 Series
Serial data register (upper digit) (SRU: $007)
Bit
Initial value
1
2
3
0
Undefined Undefined Undefined Undefined
Read/Write
R/W
R/W
R/W
R/W
Bit name
SR7
SR6
SR5
SR4
Figure 58 Serial Data Register (SRU)
Transmit clock
1
Serial output
data
2
3
4
5
6
LSB
7
8
MSB
Serial input data
latch timing
Figure 59 Serial Interface Output Timing
Port Mode Register A (PMRA: $004): This register has the following functions (figure 60).
• R0 1/SI pin function selection
• R0 2/SO pin function selection
Port mode register A (PMRA: $004) is a 4-bit write-only register, and is reset to $0 by MCU reset.
70
HD404358 Series
Port mode register A (PMRA: $004)
Bit
3
2
0
1
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
PMRA3
PMRA2 PMRA1 PMRA0
PMRA0
PMRA2
R03/TOC Mode Selection
0
R03
1
TOC
PMRA3
0
D3
1
BUZZ
0
R02
1
SO
PMRA1
D3/BUZZ Mode Selection
R02/SO Mode Selection
R01/SI Mode Selection
0
R01
1
SI
Figure 60 Port Mode Register A (PMRA)
Miscellaneous Register (MIS: $00C): This register has the following functions (figure 61).
• R0 2/SO pin PMOS control
Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.
Miscellaneous register (MIS: $00C)
Bit
3
2
1
0
Initial value
0
0
—
—
Read/Write
W
W
—
—
MIS3
MIS2
Bit name
MIS3
Pull-Up MOS
On/Off Selection
0
Pull-up MOS off
1
Pull-up MOS on
(refer to table 21)
Not used Not used
MIS2
CMOS Buffer
On/Off Selection
for Pin R02/SO
0
PMOS active
1
PMOS off
Figure 61 Miscellaneous Register (MIS)
71
HD404358 Series
A/D Converter
The MCU has a built-in A/D converter that uses a sequential comparison method with a resistor ladder. It
can measure eight analog inputs with 8-bit resolution. The block diagram of the A/D converter is shown in
figure 62.
4
A/D mode
register 1
(AMR1)
3
Selector
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Encoder
+
Comp
–
AVCC
AVSS
D/A
A/D
controller
Control signal
for conversion
time
A/D start flag
(ADSF)
Operating mode signal
(1 in stop mode)
Figure 62 A/D Converter Block Diagram
72
A/D mode
register 2
(AMR2)
A/D data
register
(ADRU, L)
A/D channel
register (ACR)
IAD off flag
(IAOF)
Internal data bus
A/D interrupt
request flag
(IFAD)
HD404358 Series
Registers for A/D Converter Operation
A/D Mode Register 1 (AMR1: $019): Four-bit write-only register which selects digital or analog ports, as
shown in figure 63.
A/D mode register 1 (AMR1: $019)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
AMR13
AMR12
AMR11
AMR10
Bit name
AMR10
AMR12
R32/AN2 Mode Selection
0
R32
1
AN2
AMR13
0
R33
1
AN3
0
R30
1
AN0
AMR11
R33/AN3 Mode Selection
R30/AN0 Mode Selection
R31/AN1 Mode Selection
0
R31
1
AN1
Figure 63 A/D Mode Register 1 (AMR1)
A/D Mode register 2 (AMR2: $01A): Two-bit write-only register which is used to set the A/D conversion
period and to select digital or analog ports. Bit 0 of the A/D mode register selects the A/D conversion
period, and bit 1 selects port R4 as pins AN4–AN7 in 4-pin units (figure 64).
A/D mode register 2 (AMR2: $01A)
Bit
3
2
1
0
Initial value
—
—
0
0
Read/Write
—
—
W
W
Bit name
AMR21
Not used Not used AMR21
R4/AN4–AN7 Pin Selection
AMR20
AMR20
Conversion Time
0
R4
0
34tcyc
1
AN4–AN7
1
67tcyc
Figure 64 A/D Mode Register 2 (AMR2)
73
HD404358 Series
A/D Channel Register (ACR: $016): Three-bit write-only register which indicates analog input pin
information, as shown in figure 65.
A/D channel register (ACR: $016)
Bit
3
2
1
0
Initial value
—
0
0
0
Read/Write
—
W
W
W
Not used
ACR2
ACR1
ACR0
Bit name
ACR2 ACR1 ACR0
0
0
1
1
0
1
Analog Input Selection
0
AN0
1
AN1
0
AN2
1
AN3
0
AN4
1
AN5
0
AN6
1
AN7
Figure 65 A/D Channel Register (ACR)
A/D Start Flag (ADSF: $02C, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the
completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is
cleared. Refer to figure 66.
A/D start flag (ADSF: $020, bit 2)
Bit
3
2
1
0
Initial value
—
0
0
—
Read/Write
—
R/W
W
—
Not used
ADSF
Bit name
WDON Not used
WDON
A/D Start Flag (ADSF)
0
A/D conversion completed
1
A/D conversion started
Refer to the description of timers
Figure 66 A/D Start Flag (ADSF)
74
HD404358 Series
IAD Off Flag (IAOF: $021, Bit 2): By setting the IA D off flag to 1, the current flowing through the
resistance ladder can be cut off even while operating in standby or active mode, as shown in figure 67.
IAD off flag (IAOF: $021, bit 2)
Bit
3
2
0
1
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
RAME
IAOF
ICEF
ICSF
Bit name
ICSF
IAD Off Flag (IAOF)
0
IAD current flows
1
IAD current is cut off
Refer to the description of timers
ICEF
RAME
Refer to the description of timers
Refer to the description of operating
modes
Figure 67 IAD Off Flag (IAOF)
A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower
digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion, the
resultant eight-bit data is held in this register until the start of the next conversion (figures 68, 69, and 70).
ADRU: $018
3
2
1
ADRL: $017
0
3
2
1
0
MSB
LSB
Bit 7
Bit 0
Figure 68 A/D Data Registers (ADRU, ADRL)
75
HD404358 Series
A/D data register (lower digit) (ADRL: $017)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
R
R
R
R
ADRL3
ADRL2
ADRL1
ADRL0
Bit name
Figure 69 A/D Data Register Lower Digit (ADRL)
A/D data register (upper digit) (ADRU: $018)
Bit
3
2
1
0
Initial value
1
0
0
0
Read/Write
R
R
R
R
ADRU3
ADRU2
Bit name
ADRU1 ADRU0
Figure 70 A/D Data Register Upper Digit (ADRU)
Notes on Usage
• Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF)
• Do not write to the A/D start flag during A/D conversion
• Data in the A/D data register during A/D conversion is undefined
• Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop mode. In addition, to save power while in these modes, all current
flowing through the converter’s resistance ladder is cut off.
• If the power supply for the A/D converter is to be different from VCC, connect a 0.1-µF bypass capacitor
between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly
connected to the VCC pin.)
• The contents of the A/D data register are not guaranteed during A/D conversion. To ensure that the A/D
converter oparates stably, do not execute port output instructions during A/D convention.
• The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a
shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by A/D mode register 1 or 2 (AMR1 or AMR2) as an analog
pin will remain pulled up (figure 71).
76
HD404358 Series
HLT
VCC
MIS3
VCC
AMR
A/D mode register value
DCR
PDR
CPU input
Input control signal
A/D input
ACR
A/D channel register value
Figure 71 R Port/Analog Multiplexed Pin Circuit
77
HD404358 Series
Pin Description in PROM Mode
The HD4074359 is a PROM version of a ZTAT microcomputer. In PROM mode, the MCU stops
operating, thus allowing the user to program the on-chip PROM.
Pin Number
MCU Mode
PROM Mode
DP-42S
FP-44A
Pin
I/O
Pin
I/O
1
39
RA 1
I
O0
I/O
2
40
R0 0/SCK
I/O
VCC
3
41
R0 1/SI
I/O
VCC
4
42
R0 2/SO
I/O
O1
I/O
5
43
R0 3/TOC
I/O
O2
I/O
6
1
TEST
I
VPP
7
2
RESET
I
RESET
8
3
OSC 1
I
VCC
9
4
OSC 2
O
10
5
GND
GND
11
6
AVSS
GND
12
7
R3 0/AN0
I/O
O0
I/O
13
8
R3 1/AN1
I/O
O1
I/O
14
9
R3 2/AN2
I/O
O2
I/O
15
10
R3 3/AN3
I/O
O3
I/O
16
11
R4 0/AN4
I/O
O4
I/O
17
12
R4 1/AN5
I/O
M0
I
18
13
R4 2/AN6
I/O
M1
I
19
14
R4 3/AN7
I/O
20
15
AVCC
VCC
21
16
VCC
VCC
22
17
D0/INT0
I/O
O3
I/O
23
18
D1/INT1
I/O
O4
I/O
24
19
D2/EVNB
I/O
A1
I
25
20
D3/BUZZ
I/O
A2
I
26
21
D4/STOPC
I/O
27
23
D5
I/O
A3
I
28
24
D6
I/O
A4
I
29
25
D7
I/O
A9
I
30
26
D8
I/O
VCC
78
I
HD404358 Series
Pin Number
MCU Mode
PROM Mode
DP-42S
FP-44A
Pin
I/O
Pin
I/O
31
27
R8 0
I/O
CE
I
32
28
R8 1
I/O
OE
I
33
29
R8 2
I/O
A13
I
34
30
R8 3
I/O
A14
I
35
31
R1 0
I/O
A5
I
36
32
R1 1
I/O
A6
I
37
33
R1 2
I/O
A7
I
38
34
R1 3
I/O
A8
I
39
35
R2 0
I/O
A0
I
40
36
R2 1
I/O
A10
I
41
37
R2 2
I/O
A11
I
42
38
R2 3
I/O
A12
I
Notes: 1. I/O: Input/output pin; I: Input pin; O: Output pin
2. O0 to O 4 consist of two pins each. The each pair together before using them.
79
HD404358 Series
Programming the Built-In PROM
The MCU’s built-in PROM is programmed in PROM mode. PROM mode is set by pulling RESET, M0,
and M1 low, as shown in figure 72. In PROM mode, the MCU does not operate, but it can be programmed
in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and a
100-to-28-pin socket adapter. Recommended PROM programmers and socket adapters are listed in table
29.
Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into
five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if,
for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer,
a 32-kbyte address space ($0000–$7FFF) must be specified.
Table 29
Recommended PROM Programmers and Socket Adapters
PROM Programmer
Socket Adapter
Manufacture
Model Name
Package
Manufacture
Model Name
DATA I/O corp
121 B
DP-42S
Hitachi
HS4359ESS01H
FP-44A
AVAL corp
PKW-1000
HS4359ESH01H
DP-42S
Hitachi
HS4359ESS01H
FP-44A
HS4359ESH01H
CE, OE
Control signals
A14–A0
Address bus
O7
O6
O4–O0
O5
O4–O0
O7–O0
Data bus
M0
M1
RESET
VCC
GND
VPP
HD407A4359
PROM mode pins
VCC
GND
VPP
Socket adapter
Figure 72 PROM Mode Connections
80
PROM programmer
HD404358 Series
Warnings
1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address
$8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.
Note that the plastic-package version cannot be erased and reprogrammed.
2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1
positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure
that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.
3. PROM programmers have two voltages (VPP ): 12.5 V and 21 V. Remember that ZTAT devices
require a VPP of 12.5 V—the 21-V setting will damage them. 12.5 V is the Intel 27256 setting.
Programming and Verification
The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage
to data reliability.
Programming and verification modes are selected as listed in table 30.
For details of PROM programming, refer to the following Notes on PROM Programming section.
Table 30
PROM Mode Selection
Pin
Mode
CE
OE
VPP
O0–O4
Programming
Low
High
VPP
Data input
Verification
High
Low
VPP
Data output
Programming inhibited
High
High
VPP
High impedance
81
HD404358 Series
Addressing Modes
RAM Addressing Modes
The MCU has three RAM addressing modes, as shown in figure 73 and described below.
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from
$040 to $04F, are accessed with the LAMR and XMRA instructions.
W register
W1 W0
RAM address
X register
X3
X2
X1
Y register
X0
Y3
Y2
Y1
Y0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register Direct Addressing
1st word of Instruction
Opcode
2nd word of Instruction
d
RAM address
9
d8
d7
d6
d5
d4
d3
d2
d1
d0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct Addressing
Instruction
Opcode
0
RAM address
0
0
1
0
m1
m0
0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory Register Addressing
Figure 73 RAM Addressing Modes
82
m3 m2
HD404358 Series
ROM Addressing Modes and the P Instruction
The MCU has four ROM addressing modes, as shown in figure 74 and described below.
Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC 13–PC0) with 14-bit immediate data.
Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction
is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 76. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.
Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.
Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000–
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight highorder bits (PC13–PC6).
Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.
P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 75. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If
both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.
The P instruction has no effect on the program counter
83
HD404358 Series
1st word of instruction
[JMPL]
[BRL]
[CALL]
Opcode
p3
Program counter
2nd word of instruction
p2
p1
p0
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Direct Addressing
Instruction
[BR]
Program counter
Opcode
b7
b6
b5
b4
b3
b2
b1
b0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Current Page Addressing
Instruction
[CAL]
0
Program counter
0
0
0
a5
Opcode
0
0
0
a4
a3
a2
a1
a0
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Zero Page Addressing
Instruction
[TBR]
Opcode
p3
p2
p1
p0
B register
B3
0
Program counter
B0
A3
A2
A1
A0
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table Data Addressing
Figure 74 ROM Addressing Modes
84
B2 B1
Accumulator
HD404358 Series
Instruction
[P]
Opcode
p3
p2
p1
p0
B register
B3
0
B2 B1
Accumulator
B0
A3
A2
A1
A0
0
Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0
Address Designation
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
ROM data
B3
B2
B1
B0
A3 A
2
A1
A
0
If RO 8 = 1
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
R23 R22 R21 R20 R13 R12 R11 R10
If RO 9 = 1
Pattern Output
Figure 75 P Instruction
85
HD404358 Series
256 (n – 1) + 255
BR
AAA
256n
AAA
BBB
256n + 254
256n + 255
256 (n + 1)
NOP
BR
BR
BBB
AAA
NOP
Figure 76 Branching when the Branch Destination is on a Page Boundary
86
HD404358 Series
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Notes
Supply voltage
VCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +14.0
V
1
Pin voltage
VT
–0.3 to VCC + 0.3 V
2
–0.3 to +15.0
V
3
Total permissible input current
∑IO
105
mA
4
Total permissible output current
–∑IO
50
mA
5
Maximum input current
IO
4
mA
6, 7
30
mA
6, 8
7, 9
Maximum output current
–I O
4
mA
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.
1. Applies to pin TEST (VPP ) of HD407A4359.
2. Applies to all standard voltage pins.
3. Applies to intermediate-voltage pins.
4. The total permissible input current is the total of input currents simultaneously flowing in from all
the I/O pins to GND.
5. The total permissible output current is the total of output currents simultaneously flowing out from
VCC to all I/O pins.
6. The maximum input current is the maximum current flowing from each I/O pin to GND.
7. Applies to ports D0 to D8, R0, R1, R3, R4, and R8.
8. Applies to port R2.
9. The maximum output current is the maximum current flowing from V CC to each I/O pin.
87
HD404358 Series
Electrical Characteristics
DC Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C; HD404354/
HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20
to +75°C, unless otherwise specified)
Item
Symbol Pins
Min
Typ
Max
Input high
voltage
VIH
0.8V CC
—
VCC + 0.3 V
SI
0.7 VCC
—
VCC + 0.3 V
OSC 1
VCC – 0.5
—
VCC + 0.3 V
RESET, SCK,
–0.3
—
0.2V CC
V
SI
–0.3
—
0.3V CC
V
OSC 1
–0.3
—
0.5
V
RESET, SCK,
Unit
Test Condition Notes
INT0, INT1,
STOPC, EVNB
Input low
voltage
VIL
INT0, INT1,
STOPC, EVNB
Output high
voltage
VOH
SCK, SO, TOC
VCC – 0.5
—
—
V
–I OH = 0.5 mA
Output low
voltage
VOL
SCK, SO, TOC
—
—
0.4
V
I OL = 0.4 mA
I/O leakage
current
|IIL|
RESET, SCK, SI, —
—
1
µA
Vin = 0 V to VCC 1
—
5.0
mA
VCC = 5 V,
SO,TOC,OSC 1,
INT0, INT1,
STOPC, EVNB
Current
dissipation in
active mode
I CC
VCC
—
Current
dissipation in
standby mode
I SBY
Current
dissipation in
stop mode
I STOP
VCC
—
—
10
µA
Stop mode
retaining
voltage
VSTOP
VCC
2
—
—
V
f OSC = 4 MHz
VCC
—
—
2.0
mA
VCC = 5 V,
3
f OSC = 4 MHz
VCC = 5 V
Notes: 1. Excludes current flowing through pull-up MOS and output buffers.
2. I CC is the source current when no I/O current is flowing while the MCU is in reset state.
Test conditions:
MCU:
Reset
Pins:
RESET, TEST at GND
88
2
4
HD404358 Series
3. I SBY is the source current when no I/O current is flowing while the MCU timer is operating.
Test conditions:
MCU: I/O reset
Standby mode
Pins:
RESET at V CC
TEST at GND
D0–D 8, R0–R4, R8, RA1 at V CC
4. This is the source current when no I/O current is flowing.
Test conditions: Pins:
RESET at V CC
TEST at GND
D0–D 8, R0–R4, R8, RA1 at V CC
I/O Characteristics for Standard Pins (HD407A4359: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to
+75°C; HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V,
GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item
Symbol Pins
Input high
voltage
VIH
D0–D 8,
Min
Typ
Max
Unit
Test Condition
0.7V CC
—
VCC + 0.3
V
–0.3
—
0.3V CC
V
VCC – 0.5
—
—
V
–I OH = 0.5 mA
—
—
0.4
V
I OL = 1.6 mA
—
—
1
µA
Vin = 0 V to VCC
30
150
300
µA
VCC = 5 V,
Note
R0, R1, R3,
R4, R8, RA 1
Input low
voltage
VIL
D0–D 8,
R0, R1, R3,
R4, R8, RA 1
Output high
voltage
VOH
D0–D 8,
R0, R1, R3,
R4, R8
Output low
voltage
VOL
D0–D 8,
R0, R1, R3,
R4, R8
Input leakage
current
|IIL|
D0–D 8,
1
R0, R1, R3,
R4, R8, RA 1
Pull-up MOS
current
–I PU
D0–D 8,
R0, R1, R3,
Vin = 0 V
R4, R8
Note:
1. Output buffer current is excluded.
89
HD404358 Series
I/O Characteristics for Intermediate-Voltage Pins (HD407A4359: V CC = 2.7 to 5.5 V, GND = 0 V, Ta =
–20 to +75°C;HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD 40A4358: VCC = 2.7 to
6.0 V, GND = 0 V, T a = –20 to +75°C, unless otherwise specified)
Item
Symbol
Pins
Min
Typ
Max
Unit
Test Condition
Input high
voltage
VIH
R2
0.7V CC
—
12
V
Input low
voltage
VIL
R2
–0.3
—
0.3V CC
V
Output high
voltage
VOH
R2
11.5
—
—
V
500 kΩ at 12 V
Output low
voltage
VOL
R2
—
—
0.4
V
I OL = 0.4 mA
—
—
2.0
V
I OL = 15 mA,
Note
VCC = 4.5 to 5.5 V
I/O leakage
current
Note:
90
|IIL|
R2
—
1. Excludes output buffer current.
—
20
µA
Vin = 0 V to 12 V
1
HD404358 Series
A/D Converter Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, T a = –20 to +75°C;
HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V, GND = 0
V, Ta = –20 to +75°C, unless otherwise specified)
Item
Symbol
Pins
Min
Analog supply
voltage
AVCC
AVCC
VCC – 0.3 VCC
Analog input
voltage
AVin
AN 0–AN 7 AVSS
Current flowing I AD
between AV CC
and AV SS
Analog input
capacitance
CA in
Typ
Max
Unit
VCC + 0.3 V
—
AVCC
V
—
—
200
µA
AN 0–AN 7 —
—
30
pF
Resolution
8
8
8
Bit
Number of input
channels
0
—
8
Channel
Absolute
accuracy
—
—
±2.0
LSB
Conversion
time
34
—
67
t cyc
—
—
MΩ
Input
impedance
Note:
AN 0–AN 7 1
Test Condition
Note
1
VCC = AVCC = 5.0
V
1. Connect this to V CC if the A/D converter is not used.
91
HD404358 Series
Standard f OSC = 5.0 MHz Version AC Characteristics (HD404354/HD404356/HD404358: V CC = 2.7 to
6.0 V, GND = 0 V, T a = –20 to +75°C)
Item
Symbol Pins
Clock oscillation
frequency
f OSC
Instruction cycle time
t cyc
OSC 1, OSC 2
Min
Typ
Max
Unit Test Condition
0.4
4
5.0
MHz 1/4 system clock
division ratio
0.8
1
10
µs
Note
Oscillation stabilization t RC
time (ceramic oscillator)
OSC 1, OSC 2
—
—
7.5
ms
1
Oscillation stabilization
time (crystal oscillator)
t RC
OSC 1, OSC 2
—
—
40
ms
1
External clock high
width
t CPH
OSC 1
80
—
—
ns
2
External clock low width t CPL
OSC 1
80
—
—
ns
2
External clock rise time t CPr
OSC 1
—
—
20
ns
2
External clock fall time
t CPf
OSC 1
—
—
20
ns
2
INT0, INT1, EVNB high
widths
t IH
INT0, INT1,
EVNB
2
—
—
t cyc
3
INT0, INT1, EVNB low
widths
t IL
INT0, INT1,
EVNB
2
—
—
t cyc
3
RESET low width
t RSTL
RESET
2
—
—
t cyc
4
STOPC low width
t STPL
STOPC
1
—
—
t RC
5
RESET rise time
t RSTr
RESET
—
—
20
ms
4
STOPC rise time
t STPr
STOPC
—
—
20
ms
5
Input capacitance
Cin
All input pins
—
except and R2
—
15
pF
f = 1 MHz, Vin = 0 V
R2
—
30
pF
f = 1 MHz, Vin = 0 V
—
Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the
following situations:
a.
After V CC reaches 2.7 V at power-on.
b.
After RESET input goes low when stop mode is cancelled.
c.
After STOPC input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET
or STOPC must be input for at least a duration of t RC.
When using a crystal or ceramic oscillator, consult with the manufacturer to determine what
stabilization time is required, since it will depend on the circuit constants and stray capacitance.
2. Refer to figure 77.
3. Refer to figure 78.
4. Refer to figure 79.
5. Refer to figure 80.
92
HD404358 Series
High-Speed fOSC = 8.5 MHz Version AC Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0
V, Ta = –20 to +75°C; HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20
to +75°C)
Item
Symbol Pins
Clock oscillation
frequency
f OSC
Instruction cycle time
OSC 1, OSC 2
t cyc
Min
Typ
Max
Unit
Test Condition
0.4
4
5.0
MHz 1/4 system clock
division ratio
0.4
4
8.5
MHz 1/4 system clock
division ratio,
VCC = 4.5 to 5.5 V
0.8
1
10
µs
0.47
1
10
µs
Note
VCC = 4.5 to 5.5 V
Oscillation
stabilization time
(ceramic oscillator)
t RC
OSC 1, OSC 2
—
—
7.5
ms
1
Oscillation
stabilization time
(crystal oscillator)
t RC
OSC 1, OSC 2
—
—
40
ms
1
External clock high
width
t CPH
OSC 1
80
—
—
ns
2
47
—
—
ns
80
—
—
ns
47
—
—
ns
—
—
20
ns
—
—
15
ns
—
—
20
ns
—
—
15
ns
External clock low
width
External clock rise
time
t CPL
t CPr
External clock fall time t CPf
OSC 1
OSC 1
OSC 1
VCC = 4.5 to 5.5 V
2
2
VCC = 4.5 to 5.5 V
2
2
VCC = 4.5 to 5.5 V
2
2
VCC = 4.5 to 5.5 V
2
INT0, INT1, EVNB high t IH
widths
INT0, INT1, EVNB
2
—
—
t cyc
3
INT0, INT1, EVNB low
widths
t IL
INT0, INT1, EVNB
2
—
—
t cyc
3
RESET low width
t RSTL
RESET
2
—
—
t cyc
4
STOPC low width
t STPL
STOPC
1
—
—
t RC
5
RESET rise time
t RSTr
RESET
—
—
20
ms
4
STOPC rise time
t STPr
STOPC
—
—
20
ms
5
Input capacitance
Cin
All input pins
except TEST and
R2
—
—
15
pF
f = 1 MHz, Vin = 0 V
TEST
—
—
15
pF
f = 1 MHz, Vin = 0 V 6
—
—
180
pF
f = 1 MHz, Vin = 0 V 7
R2
—
—
30
pF
f = 1 MHz, Vin = 0 V
93
HD404358 Series
Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the
following situations:
a. After V CC reaches 2.7 V at power-on.
b. After RESET input goes low when stop mode is cancelled.
c. After STOPC input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET
or STOPC must be input for at least a duration of t RC.
When using a crystal or ceramic oscillator, consult with the manufacturer to determine what
stabilization time is required, since it will depend on the circuit constants and stray capacitance.
2. Refer to figure 77.
3. Refer to figure 78.
4. Refer to figure 79.
5. Refer to figure 80.
6. Applies to the HD40A4354, HD40A4356, HD40A4358.
7. Applies to the HD407A4359.
94
HD404358 Series
Serial Interface Timing Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to
+75°C; HD404354/HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358: V CC = 2.7 to 6.0 V,
GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
During Transmit Clock Output
Item
Symbol
Pins
Min
Typ
Max
Unit
Test Condition
Note
Transmit clock cycle
time
t Scyc
SCK
1
—
—
t cyc
Load shown in figure 82
1
Transmit clock high
width
t SCKH
SCK
0.4
—
—
t Scyc
Load shown in figure 82
1
Transmit clock low
width
t SCKL
SCK
0.4
—
—
t Scyc
Load shown in figure 82
1
Transmit clock rise time t SCKr
SCK
—
—
80
ns
Load shown in figure 82
1
Transmit clock fall time
SCK
—
—
80
ns
Load shown in figure 82
1
Serial output data delay t DSO
time
SO
—
—
300
ns
Load shown in figure 82
1
Serial input data setup
time
t SSI
SI
100
—
—
ns
1
Serial input data hold
time
t HSI
SI
200
—
—
ns
1
t SCKf
During Transmit Clock Input
Item
Symbol
Pins
Min
Typ
Max
Unit
Transmit clock cycle
time
t Scyc
SCK
1
—
—
t cyc
1
Transmit clock high
width
t SCKH
SCK
0.4
—
—
t Scyc
1
Transmit clock low
width
t SCKL
SCK
0.4
—
—
t Scyc
1
Transmit clock rise time t SCKr
SCK
—
—
80
ns
1
Transmit clock fall time
SCK
—
—
80
ns
1
Serial output data delay t DSO
time
SO
—
—
300
ns
Serial input data setup
time
t SSI
SI
100
—
—
ns
1
Serial input data hold
time
t HSI
SI
200
—
—
ns
1
Note:
t SCKf
Test Condition
Load shown in figure 82
Note
1
1. Refer to figure 81.
95
HD404358 Series
OSC1
1/fCP
VCC – 0.5 V
tCPL
tCPH
0.5 V
tCPr
tCPf
Figure 77 External Clock Timing
INT0, INT1, EVNB
0.8VCC
tIL
tIH
0.2VCC
Figure 78 Interrupt Timing
RESET
0.8VCC
tRSTL
0.2VCC
tRSTr
Figure 79 RESET Timing
STOPC
0.8VCC
tSTPL
0.2VCC
tSTPr
Figure 80 STOPC Timing
96
HD404358 Series
t Scyc
t SCKf
SCK
VCC – 0.5 V (0.8VCC )*
0.4 V (0.2VCC)*
t SCKr
t SCKL
t SCKH
t DSO
VCC – 0.5 V
0.4 V
SO
t SSI
t HSI
0.7V CC
0.3VCC
SI
Note: *VCC – 0.5 V and 0.4 V are the threshold voltages for transmit clock output, and
0.8VCC and 0.2VCC are the threshold voltages for transmit clock input.
Figure 81 Serial Interface Timing
VCC
RL = 2.6 kΩ
Test
point
C=
30 pF
R=
12 kΩ
Hitachi
1S2074
or equivalent
Figure 82 Timing Load Circuit
97
HD404358 Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out.
On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404354,
HD40A4354, HD404356 and HD40A4356 as an 8-kword version (HD404358, HD40A4358). The 8-kword
and 16-kword data sizes are required to change ROM data to mask manu facturing data since the program
used is for an 8-k or 16-kword version.
This limitation applies when using an EPROM or a data base.
ROM 4-kword version:
HD404354, HD40A4354
$0000
ROM 6-kword version:
HD404356, HD40A4356
$0000
Vector address
$000F
$0010
Vector address
$000F
$0010
Zero-page subroutine
(64 words)
$003F
$0040
Zero-page subroutine
(64 words)
$003F
$0040
Pattern & program
(4,096 words)
$0FFF
$1000
Pattern & program
(6,144 words)
$17FF
$1800
Not used
$1FFF
$1FFF
Fill this area with 1s
98
Not used
HD404358 Series
HD404354/HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358
Please check off the appropriate applications and enter the necessary information.
1. ROM size
5 MHz operation
HD404354
4-kword
8.5 MHz operation HD40A4354
5 MHz operation
HD404356
Customer
6-kword
8.5 MHz operation HD40A4356
5 MHz operation
HD404358
Date of order
Department
Name
8-kword
8.5 MHz operation HD40A4358
ROM code name
LSI number
2. ROM code media
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
3. System Oscillator (OSC1, OSC2)
Ceramic oscillator
f=
MHz
Crystal oscillator
f=
MHz
External clock
f=
MHz
4. Stop mode
Used
Not used
5. Package
DP-42S
FP-44A
99
HD404358 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
: http:semiconductor.hitachi.com/
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Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Hitachi Europe GmbH
Electronic components Group
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D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
Electronic Components Group.
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Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
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Fax: 535-1533
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Taipei Branch Office
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Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
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Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
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Kowloon, Hong Kong
Tel: <852> (2) 735 9218
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Telex: 40815 HITEC HX
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
100