HOLTEK HT46R343

HT46R343
A/D Type 8-Bit OTP MCU with OPA and 8´8 LED Driver
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0075E MCU Reset and Oscillator Circuits Application Note
- HA0114E Calibrating the OPA Input Voltage Offset on the HT46R32/322/34/342, HT45R32/34 and HT45RM03
Features
· Operating voltage:
· Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
at VDD=5V
· 6-level subroutine nesting
· 37 bidirectional I/O lines (max.)
· 16 channel 12-bit resolution A/D converter
· support 8´8 LED driver
· Integrated single operational amplifier or comparator
· Single interrupt input shared with an I/O line
selectable via configuration option
· Two 8-bit programmable timer/event counter with
· Peripheral clock output - PCK
overflow interrupt
· Dual 8-bit PWM outputs shared with I/O lines
· Integrated crystal and RC oscillator
· Bit manipulation instruction
· Watchdog Timer
· Full table read instruction
· 4096´15 Program Memory capacity
· 63 powerful instructions
· 192´8 Data Memory capacity
· All instructions executed in one or two machine
· Integrated PFD function for sound generation
cycles
· Low voltage reset function
· Power-down and wake-up functions reduce power
· 44-pin QFP package
consumption
General Description
With the comprehensive features of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, multi-channel
A/D Converter, OP/Comparator, Pulse Width Modulation function, LED driver, Power-down and wake-up
functions etc, the application scope of these devices is
broad and encompasses areas such as sensor signal
processing, motor driving, industrial control, consumer
products, subsystem controllers, etc.
The HT46R343 is 8-bit, high performance, RISC architecture microcontroller devices. With their fully integrated A/D converter they are especially suitable for
applications which interface to analog signals, such as
those from sensors. The addition of an internal operational amplifier/comparator and PWM modulation functions further adds to the analog capability of these
devices.
Rev. 1.00
1
October 11, 2007
HT46R343
Block Diagram
M
T M R 0 C
P D 6 /IN T
P r e s c a le r
U
Y S
fS
Y S
P D 5 /T M R 0
X
T M R 0
fS
P F D 0
In te rru p t
C ir c u it
P ro g ra m
R O M
M
T M R 1 C
S T A C K
P ro g ra m
C o u n te r
IN T C
T M R 1
P F D 1
In s tr u c tio n
R e g is te r
M
M P
U
X
P E C
P o rt E
P E
M U X
In s tr u c tio n
D e c o d e r
S T A T U S
A L U
P D
P A 3 , P A 5
P C C
O S C 2
O S
R E
V D
V S
S
S
P o rt D
S h ifte r
C 1
A C C
/4
P A 4 /T M R 1
X
P A 4
fS
U
Y S
/4
W D T O S C
X
P E 0 ~ P E 7
P W M
P D C
T im in g
G e n e ra to r
P r e s c a le r
M
W D T
D A T A
M e m o ry
U
P o rt C
P C
L V R
P D
P D
P D
P D
P D
0 /P
1 /P
2 /P
5 /T
6 /IN
W M 0
W M 1
C K
M R 0
T
P C 0 /A N 8 ~ P C 7 /A N 1 5
1 6 -C h a n n e l
A /D C o n v e rte r
D
P B C
P o rt B
P B
A P N
P B 0 /A N 0 ~ P B 7 /A N 7
A P P
P A C
A P O
L o w O ffs e t O P -a m p
Rev. 1.00
P A
2
P o rt A
P A
P A
P A
P A
0 ~
3 /P
4 /T
5 ~
P A
F
M
P A
D
2
R 1
7
October 11, 2007
HT46R343
Pin Assignment
P C
P C
P C
P C
7 /A
6 /A
5 /A
4 /A
P E
P E
P E
P E
P E
P E
P E
N 1
N 1
N 1
N 1
2
3
4
5
7
6
5
4
3
2
1
P C 3
P C 2
P C
P C
P B
P B
P B
P B
P B
P B
P B
/A N
/A N
1 /A
0 /A
7 /A
6 /A
5 /A
4 /A
3 /A
2 /A
1 /A
4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
1 1
1 0
N 9
N 8
N 7
N 6
N 5
N 4
N 3
N 2
N 1
1
3 2
3
3 1
4
3 0
5
H T 4 6 R 3 4 3
4 4 Q F P -A
6
7
2 9
2 8
2 7
8
2 6
9
2 5
1 0
1 1
P E
P A
P A
P A
P A
P A
P A
P A
P A
3 3
2
1
2
6
0
4 /T R M 1
3 /P F D
O S C 2
O S C 1
2 4
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
0
5
7
2 3
V D D
R E S
P D 0
P D 1
P D 2
P D 5
P D 6
V S S
A P P
A P N
P B 0
/P
/P
/P
/T
/IN
W M 0
W M 1
C K
M R 0
T
/A N 0 /A P O
Pin Description
Pin Name
I/O
Options
Description
I/O
Pull-high
Wake-up
PA3 or PFD
Timer 0 or
Timer 1 (PFD
Clock Source)
Bidirectional 8-bit input/output port. Each pin can be configured as wake-up
input by configuration options. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Configuration options determine which
pins on the port have pull-high resistors. The PFD and TMR1 pins are
pin-shared with PA3 and PA4.
PA0~PA7 can be used as LED driver (source end).
I/O
Pull-high
16 lines AD inut pun-shared with PB and PC.
Bidirectional 8-bit input/output port. Software instructions determine if the
pin is a CMOS output or Schmitt trigger input. Configuration options determine
which pins on the port have pull-high resistors. Pins PB, PC are pin-shared
with the A/D input pins. The A/D inputs are selected via software instructions.
Once selected as an A/D input, the I/O function and pull-high resistor are disabled automatically.
About PB0/AN0/APO: If the pin is PB0 (setting by ADCS.PCR3~0=00), ADC
and OP amp should be power off automatically.
If the pin is AN0 (setting by ADCS.PCR3~0), APO is connected with AN0 pin
together and OP amp on/off is controlled by OPAC.OPAEN.
I/O
Pull-high
PD0 or PWM0
PD1 or PWM1
PD2 or PCK
Bi-directional 4-bit input/output port. Software instructions determine if the
pin is a CMOS output or Schmitt trigger input. Configuration options determine
which pins on this port have pull-high resistors. PD0/PD1 are pin-shared with
the PWM0/PWM1 outputs selected via configuration option.
PD0, PD1, PD2, PD5, PD6 are pin-shared with the PWM0, PWM1, PCK,
TMR0, INT output selected via configuration option.
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if the
pin is a CMOS output or Schmitt trigger input. A configuration option determines if all pins on the port have pull-high resistors.
PE0~PE7 can be used as LED driver (sink end).
APN
APP
I
I
¾
APN and APP are the internal operational amplifier, negative input pin and
positive input pin respectively .
RES
I
¾
Schmitt trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground.
PA0~PA2
PA3/PFD
PA4/TMR1
PA5~PA7
PB0/AN0/APO,
PB1/AN1~
PB7/AN7,
PC0/AN8~
PC7/AN15
PD0/PWM0
PD1/PWM1
PD2/PCK
PD5/TMR0
PD6/INT
PE0~PE7
Rev. 1.00
3
October 11, 2007
HT46R343
Pin Name
OSC1
OSC2
I/O
Options
Description
I
O
Crystal
or RC
OSC1, OSC2 are connected to an external RC network or external crystal,
determined by configuration option, for the internal system clock. If the RC
system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Operating Temperature: 40°C~+85°C, Ta=25°C
Test Conditions
Symbol
Parameter
VDD
IDD1
IDD2
Min.
Typ.
Max.
Unit
Conditions
VDD
¾
fSYS=4MHz
2.2
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
Operating Current
(Crystal OSC)
3V
No load, fSYS=4MHz
ADC disable
¾
0.6
1.5
mA
¾
2
4
mA
Operating Current
(RC OSC)
3V
¾
0.8
1.5
mA
¾
2.5
4
mA
¾
3
5
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
Operating Voltage
IDD3
Operating Current
(Crystal OSC, RC OSC)
ISTB1
Standby Current
(WDT Enabled)
5V
5V
5V
3V
5V
3V
No load, fSYS=4MHz
ADC disable
No load, fSYS=8MHz
ADC disable
No load,
system HALT
Standby Current
(WDT Disabled)
5V
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
¾
2.7
3.0
3.3
V
IOL1
I/O Port Sink Current
(PA, PB, PC, PD)
3V
VOL=0.1VDD
4
8
¾
mA
5V
VOL=0.1VDD
10
20
¾
mA
3V
VOH=0.9VDD
-2
-4
¾
mA
5V
VOH=0.9VDD
-5
-10
¾
mA
3V
VOL=0.1VDD
8
16
¾
mA
5V
VOL=0.1VDD
20
40
¾
mA
ISTB2
IOH1
IOL2
Rev. 1.00
I/O Port Source Current
(PB, PC, PD, PE)
PE Ports Sink Current for LED
Driver
No load,
system HALT
4
October 11, 2007
HT46R343
Test Conditions
Symbol
Parameter
IOH2
RPH
PA Ports Source Current for LED
Driver
Min.
Typ.
Max.
Unit
Conditions
VDD
3V
VOH=0.9VDD
-4
-8
¾
mA
5V
VOH=0.9VDD
-10
-20
¾
mA
100
kW
3V
¾
20
60
5V
¾
10
30
50
kW
¾
0
¾
VDD
V
¾
0.5
1
mA
¾
1.5
3
mA
Pull-high Resistance
VAD
A/D Input Voltage
¾
IADC
Additional Power Consumption
if A/D Converter is Used
3V
DNL
ADC Differential Non-Linearity
5V
tAD=1ms
¾
¾
±2
mA
INL
ADC Integral Non-Linearity
5V
tAD=1ms
¾
±2.5
4
mA
¾
¾
12
Bits
¾
5V
¾
RESOLU Resolution
¾
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
fSYS
fTIMER
tWDTOSC
System Clock
(Crystal OSC, RC OSC)
Timer I/P Frequency
(TMR)
Min.
Typ.
Max.
Unit
Conditions
VDD
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
Watchdog Oscillator Period
tWDT1
Watchdog Time-out Period
(WDT OSC)
¾
¾
215
¾
216
tWDTOSC
tWDT2
Watchdog Time-out Period
(System Clock)
¾
¾
217
¾
218
tSYS
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Wake-up from HALT
¾
1024
¾
*tSYS
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
80
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
Note: *tSYS=1/fSYS
Rev. 1.00
5
October 11, 2007
HT46R343
OP Amplifier Electrical Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
D.C. Electrical Characteristic
VDD
Operating Voltage
¾
¾
3
¾
5.5
V
VOPOS1
Input Offset Voltage
5V
¾
-10
¾
10
mV
VOPOS2
Input Offset Voltage
5V
By Calibration
-2
¾
2
mV
VCM
Common Mode Voltage Range
¾
¾
VSS
¾
VDD1.4V
V
PSRR
Power Supply Rejection Ratio
¾
¾
60
80
¾
dB
CMRR
Common Mode Rejection Ratio
5V
VCM=0~VDD-1.4V
60
80
¾
dB
tRES
Response Time (Comparator)
¾
Input overdrive=±10mV
¾
¾
2
ms
¾
60
80
¾
dB
A.C. Electrical Characteristic
VOPOS1
Open Loop Gain
¾
SR
Slew Rate +, Slew Rate -
¾
No load
¾
0.1
¾
V/ms
GBW
Gain Band Width
¾
RL=1M, CL=100p
¾
¾
100
kHz
Rev. 1.00
6
October 11, 2007
HT46R343
Functional Description
incremented by one. The program counter then points to
the memory word containing the next instruction code.
Execution Flow
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter, PCL, is a readable and writeable register. Moving data into the PCL
performs a short jump. The destination will be within 256
locations.
Program Counter - PC
The program counter controls the sequence in which the
instructions stored in program memory are executed and
whose contents specify full range of program memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event 0 Counter Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event 1 Counter Overflow
0
0
0
0
0
0
0
0
1
1
0
0
A/D Converter Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
*11
*10
*9
*8
@7
@3
@2
@1
@0
Skip
Program Counter+2
Loading PCL
@6
@5
@4
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
PC11~PC8: Current Program Counter bits
#11~#0: Instruction Code bits
Rev. 1.00
S11~S0: Stack register bits
@7~@0: PCL bits
7
October 11, 2007
HT46R343
Program Memory - ROM
the table, the location must be placed in TBLP. The
TBLH register is read only and cannot be restored. If
the main routine and the ISR, Interrupt Service Routine, both employ the table read instruction, the contents of the TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR.
In such a case errors can occur. Therefore, using the
table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table
read instruction has to be used in both the main routine
and the ISR, the interrupt is should be disabled prior to
the table read instruction. It should not be re-enabled
until the TBLH has been backed up. All table related instructions require two cycles to complete their operation. These areas may function as normal program
memory depending upon requirements.
The program memory is used to store the program instructions which are to be executed as well as table data
and interrupt entries. It is structured into 4K´15 bits device, which can be addressed by both the program
counter and table pointer.
Certain locations in the program memory are reserved
for use by the reset and by the interrupt vectors.
· Location 000H
This vector is reserved for program initialisation. After
a device reset is initiated, the program will jump to this
location and begin execution.
· Location 004H
This vector is used by the external interrupt INT. If the
external interrupt pin on the device receives a low going edge, the program will jump to this location and begin execution if the external interrupt is enabled and
the stack is not full.
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 40 H
0 0 84 H
· Location 008H
This vector is used by the Timer/Event Counter 0. If a
timer overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled
and the stack is not full.
0 0 C H
0 1 0 H
E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
A /D
P ro g ra m
M e m o ry
C o n v e r te r In te r r u p t S u b r o u tin e
· Location 00CH
This vector is used by the Timer/Event Counter 1. If a
timer overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled
and the stack is not full.
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
· Location 010H
7 0 0 H
This vector is used by the A/D converter. When an A/D
cycle conversion is complete, the program will jump to
this location and begin execution if the A/D interrupt is
enabled and the stack is not full.
L o o k - u p T a b le ( 2 5 6 w o r d s )
7 F F H
1 4 b its
Program Memory
· Table location
Stack Register - STACK
Any location in the Program Memory space can be
used as a look-up table. The instructions ²TABRDC
[m]² (the current page, 1 page=256 words) and
²TABRDL [m]² (the last page) transfer the contents of
the lower-order byte to the specified data memory, and
the higher-order byte to TBLH. Only the destination of
the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, and the remaining bits are read as ²0².
The Table Higher-order byte register (TBLH) is read
only. The table pointer (TBLP) is a read/write register,
which indicates the table location. Before accessing
Instruction
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 6 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer, known as stack pointer, and is also neither
readable nor writeable. At a subroutine call or interrupt
acknowledgment, the contents of the program counter
are pushed onto the stack. At the end of a subroutine or
an interrupt routine, signaled by a return instruction,
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*11~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.00
P11~P8: Current program counter bits
8
October 11, 2007
HT46R343
Arithmetic and Logic Unit - ALU
RET or RETI, the program counter is restored to its previous value from the stack. After a device reset, the
stack pointer will point to the top of the stack.
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented, using a RET or RETI instruction, the interrupt will be serviced. This feature prevents
a stack overflow allowing the programmer to use the
structure more easily. In a similar case, if the stack is full
and a ²CALL² is subsequently executed, stack overflow
occurs and the first entry will be lost. Only the most recent 6 return addresses are stored.
· Arithmetic operations - ADD, ADC, SUB, SBC, DAA
· Logic operations - AND, OR, XOR, CPL
· Rotation - RL, RR, RLC, RRC
· Increment and Decrement - INC, DEC
· Branch decision - SZ, SNZ, SIZ, SDZ ....
The ALU not only saves the results of a data operation but
also changes the status register.
Data Memory - RAM
0 0 H
In d ir e c t A d d r e s s in g R e g is te r
0 1 H
M P
The data memory is divided into two functional groups:
special function registers and general purpose data
memory. The general purpose memory has a structure
of 192´8 bits. Most locations are read/write, but some
are read only.
0 2 H
The remaining space between the end of the Special
Purpose Data Memory and the beginning of the General
Purpose Data Memory is reserved for future expanded
usage, reading these locations will obtain a result of
²00H². The general purpose data memory, addressed
from 40H to FFH, is used for user data and control information under instruction commands. All of the data
memory areas can handle arithmetic, logic, increment,
decrement and rotate operations directly. Except for
some dedicated bits, each bit in the data memory can
be set and reset by the ²SET [m].i² and ²CLR [m].i² instructions. They are also indirectly accessible through
memory pointer register, MP.
0 3 H
0 4 H
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation on
[00H] accesses data memory pointed to by the MP
register. Reading location 00H itself indirectly will return
the result 00H. Writing indirectly results in no operation.
1 0 H
T M R 1
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
1 B H
P E E
P E
1 C H
P W M 0
1 D H
P W M 1
1 E H
Accumulator
IN T C 1
1 F H
O P A C
The accumulator is closely related to ALU operations
and can carry out immediate data operations. Any data
movement between two data memory locations must
pass through the accumulator.
2 0 H
A D R L
2 1 H
A D R H
2 2 H
2 3 H
2 4 H
A D C R
The memory pointer register, MP, is a 8-bit register.
3 9 H
4 0 H
F F H
S p e c ia l P u r p o s e
D a ta M e m o ry
A C S R
: U n u s e d
R e a d a s "0 0 "
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
RAM Mapping
Rev. 1.00
9
October 11, 2007
HT46R343
Status Register - STATUS
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO). It
also records the status information and controls the operation sequence.
Interrupt
The devices provide an external interrupt, an internal
timer/event counter interrupt and an A/D converter interrupt. The Interrupt Control Register, INTC, contains the
interrupt control bits to set the enable or disable and the
interrupt request flags.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or a
system power-up.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked by clearing the EMI bit. This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit in INTC0/INTC1 may
be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction, otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
is set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
Status (0AH) Register
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enabled; 0=disabled)
1
EEI
Controls the external interrupt (1=enabled; 0=disabled)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
4
EIF
External interrupt request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
¾
Unused bit, read as ²0²
INTC (0BH) Register
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October 11, 2007
HT46R343
Bit No.
Label
0
EADI
1~3
¾
4
ADF
5~7
¾
Function
Control the A/D converter interrupt (1=enabled; 0=disabled)
Unused bit, read as ²0²
A/D converter request flag (1=active; 0=inactive)
Unused bit, read as ²0²
INTC1 (1EH) Register
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
All interrupts have a wake-up capability. As an interrupt
is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a
subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack.
If the contents of the register or status register are altered by the interrupt service program which corrupts
the desired control sequence, the contents should be
saved in advance.
Interrupt Source
External interrupts are triggered by a high to low transition on the INT pin, which will set the related interrupt request flag, EIF, which is bit 4 of INTC0. When the
interrupt is enabled, the stack is not full and the external
interrupt is active, a subroutine call to location 04H will
occur. The interrupt request flag, EIF, and EMI bits will
be cleared to disable other interrupts.
Vector
External Interrupt
1
004H
Timer/Event Counter 0 Overflow
2
008H
Timer/Event Counter 1 Overflow
3
00CH
A/D Converter Interrupt
4
010H
Once the interrupt request flags, T0F/T1F, EIF, ADF, are
set, they will remain in the INTC0/INTC1 register until
the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use
the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
The internal timer/event counter 0 interrupt is initialised
by setting the timer/event counter interrupt request flag,
T0F, which is bit 5 of INTC0, caused by a timer overflow.
When the interrupt is enabled, the stack is not full and
the T0F bit is set, a subroutine call to location 008H will
occur. The related interrupt request flag, T0F, will be reset and the EMI bit cleared to disable further interrupts.
The internal timer/event counter 1 interrupt is initialised
by setting the timer/event counter interrupt request flag,
T1F, which is bit 6 of INTC1, caused by a timer overflow.
When the interrupt is enabled, the stack is not full and
the T1F bit is set, a subroutine call to location 00CH will
occur. The related interrupt request flag, T1F, will be reset and the EMI bit cleared to disable further interrupts.
Oscillator Configuration
There are two oscillator circuits in the microcontroller,
namely an RC oscillator and a crystal oscillator, the
choice of which is determined by a configuration option.
When the system enters the Power-down mode the system oscillator stops and ignores external signals to conserve power.
The A/D converter interrupt is initialised by setting the
A/D converter request flag, ADF, which is bit 4 of INTC1,
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF bit is set, a
subroutine call to location 010H will occur. The related
interrupt request flag, ADF, will be reset and the EMI bit
cleared to disable further interrupts.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required whose resistance value
must range from 24kW to 1MW. The system clock, divided by 4, can be monitored on pin OSC2 if a pull-high
resistor is connected. This signal can be used to synchronise external logic. The RC oscillator provides the
most cost effective solution, however the frequency of
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related
interrupt control bit are set to 1. Of course, the stack
must not be full. To return from the interrupt subroutine,
a RET or RETI instruction may be executed. A RETI instruction will set the EMI bit to enable an interrupt service, but a RET instruction will not.
Rev. 1.00
Priority
V
O S C 1
D D
4 7 0 p F
fS
O S C 2
Y S
O S C 1
O S C 2
/4
C r y s ta l O s c illa to r
R C
O s c illa to r
System Oscillator
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HT46R343
Power-down mode, the overflow will initialisze a ²warm
reset², and only the program counter and SP are reset
to zero. To clear the contents of the WDT, three methods are adopted; external reset (a low level on the RES
pin), a software instruction and a HALT instruction. The
software instruction include ²CLR WDT² and the other
set - ²CLR WDT1² and ²CLR WDT2². Of these two
types of instruction, only one can be active depending
on the configuration option - ²CLR WDT times selection
option². If the ²CLR WDT² is selected (i.e. CLR WDT
times equal one), any execution of the ²CLR WDT² instruction will clear the WDT. In the case that ²CLR
WDT1² and ²CLR WDT2² are chosen (i.e. CLR WDT
times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
oscillation may vary with VDD, temperature and the
process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator
frequency is desired.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator; no other external components are required. Instead of a crystal, a resonator can
also be connected between OSC1 and OSC2 to get a
frequency reference, but two external capacitors in
OSC1 and OSC2 are required, If the oscillating frequency is less than 1MHz.
The WDT oscillator is a free running on-chip RC oscillator, and requires no external components. Even if the
system enters the power down mode, the system clock
is stopped, but the WDT oscillator keeps running with a
period of approximately 65ms at 5V. The WDT oscillator
can be disabled by a configuration option to conserve
power.
Power Down Operation - HALT
The HALT mode is initialised by the ²HALT² instruction
and results in the following...
Watchdog Timer - WDT
· The system oscillator will be turned off but the WDT
The WDT clock source comes from either its own integrated RC oscillator, known as the WDT oscillator, or the
instruction clock, which is the system clock divided by 4.
The choice of which one is used is decided by a
configuration option. This timer is designed to prevent a
software malfunction or sequence from jumping to an
unknown location with unpredictable results. The
Watchdog Timer can be disabled by a configuration option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation.
oscillator keeps running (if the WDT oscillator is selected).
· The contents of the on chip Data Memory and regis-
ters remain unchanged.
· WDT will be cleared and start counting again (if the
WDT clock is from the WDT oscillator).
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialisation and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the reason for the chip reset can be determined. The PDF flag is cleared by a system power-up or
executing the ²CLR WDT² instruction and is set when
executing the ²HALT² instruction. The TO flag is set if
the WDT time-out occurs, and causes a wake-up that
only resets the program counter and Stack Pointer; the
others keep their original status.
Once the internal WDT oscillator (RC oscillator with a
period of 65ms at 5V nominal) is selected, it is divided by
32768~65536 to get a time-out period of approximately
2.1s~4.3s. This time-out period may vary with temperatures, VDD and process variations. If the WDT oscillator
is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except
that in the Power-down state the WDT may stop counting and lose its protecting purpose. In this situation the
logic can only be restarted by external logic.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT instruction will stop the system
clock.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two
The WDT overflow under normal operation will initialise
a ²chip reset² and set the status bit ²TO². But in the
S y s te m
C lo c k /4
O p tio n
S e le c t
fS
8 - b it C o u n te r
7 - b it C o u n te r
W D T
O S C
T
T
W D T T im e - o u t
1 5
1 6
fS /2 ~ fS /2
C L R
W D T
Watchdog Timer
Rev. 1.00
12
October 11, 2007
HT46R343
sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
The functional unit chip reset status are shown below.
Program Counter
000H
Interrupt
Disable
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter Off
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
V D D
R E S
To minimise power consumption, all the I/O pins should
be carefully managed before entering the status.
tS
S T
S S T T im e - o u t
C h ip
Reset
R e s e t
Reset Timing Chart
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
V
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the program counter and stack
pointer, leaving the other circuits in their original state.
Some registers remain unchanged during other reset
conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish between different ²chip resets².
TO
PDF
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
D D
0 .0 1 m F
1 0 0 k W
1 0 0 k W
R E S
R E S
0 .1 m F
1 0 k W
B a s ic
R e s e t
C ir c u it
H i-n o is e
R e s e t
C ir c u it
0 .1 m F
Reset Circuit
RESET Conditions
Note:
Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the
Hi-noise Reset Circuit.
H A L T
Note: ²u² means ²unchanged²
W a rm
R e s e t
W D T
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
R E S
O S C 1
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
R e s e t
Reset Configuration
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
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V
D D
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HT46R343
The registers¢ states are summarised in the following table.
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Times-out
(HALT)*
MP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
Register
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
-11- -111
-11- -111
-11- -111
-11- -111
-uu- -uuu
PDC
-11- -111
-11- -111
-11- -111
-11- -111
-uu- -uuu
PE
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PEC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PWM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
INTC1
---0 ---0
---0 ---0
---0 ---0
---0 ---0
---u ---u
OPAC
0000 1000
0000 1000
0000 1000
0000 1000
uuuu uuuu
ADRL
xxxx ----
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
1-00 --00
1-00 --00
1-00 --00
1-00 --00
u-uu --uu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.00
14
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HT46R343
In the event count or timer mode, the timer/event counter starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt request flag T0F (T1F). In the pulse width measurement
mode with the values of the T0ON & T0E ( T1ON &T1E)
equal to 1, after the TMR0(TMR1) has received a transient from low to high (or high to low if the T0E(T1E) bit
is ²0²), it will start counting until the TMR0(TMR1) returns to the original level and resets the T0ON(T1ON).
The measured result remains in the timer/event counter
even if the activated transient occurs again. In other
words, only 1-cycle measurement can be made until the
T0ON (T1ON) is set. The cycle measurement will
re-function as long as it receives further transient pulse.
In this operation mode, the timer/event counter begins
counting not according to the logic level but to the transient edges. In the case of counter overflow, the counter
is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes,
i.e., event and timer modes.
Timer/Event Counter
Two timer/event counter (TMR) are implemented in the
microcontroller. The timer/event counter contains an
8-bit programmable count-up counter and the clock may
come from external source or an internal clock source.
An internal clock source comes from fsys (fSYS/4). Using
an external clock input allows the user to count external
events, measure time internals or pulse widths, or generate an accurate time base. While using the internal
clock allows the user to generate an accurate time base.
There are two registers related to the Timer/Event
Counter; TMR0 (TMR1), TMR0C (TMR1C). Writing
TMR0 (TMR1) will transfer the specified data to
Timer/Event Counter registers. Reading the TMR0
(TMR1) will read the contents of the Timer/Event Counter. The TMRC0 (TMR1C) is a control register, which defines the operating mode, counting enable or disable
and an active edge.
The T0TM0 & T0TM1 (T1TM0 & T1TM1) bits define the
operation mode. The event count mode is used to count
external events, which means that the clock source is
from an external TMR0 (TMR1) pin. The timer mode
functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the
pulse width measurement mode can be used to count
the high or low-level duration of the external signal
TMR0 (TMR1), and the counting is based on the internal
selected clock source.
Bit No.
0
1
2
Label
T0PSC0
T0PSC1
T0PSC2
3
T0E
4
T0ON
5
¾
6
7
To enable the counting operation, the Timer ON bit
T0ON (T1ON) should be set to 1. In the pulse width
measurement mode, the T0ON (T1ON) is automatically
cleared after the measurement cycle is completed. But
in the other two modes, the T0ON (T1ON) can only be
reset by instructions. The overflow of the Timer/Event
Counter is one of the wake-up sources and can also be
applied to a PFD (Programmable Frequency Divider)
T0M0
T0M1
Function
Defines the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable or disable the timer counting
(0=disable; 1=enable)
Unused bits, read as ²0²
Defines the operating mode (T0M1, T0M0)=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH) Register
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15
October 11, 2007
HT46R343
Bit No.
Label
0~2
¾
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
3
T1E
4
T1ON
5
¾
6
7
Function
Unused bits, read as ²0²
Enable or disable the timer counting
(0=disable; 1=enable)
Unused bits, read as ²0²
T1M0
T1M1
Defines the operating mode (T1M1, T1M0)=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
P W M
(6 + 2 ) C o m p a re
fS
T o P D 0 /P D 1 C ir c u it
8 - s ta g e P r e s c a le r
Y S
f IN
8 -1 M U X
P S C 2 ~ P S C 0
D a ta B u s
T
T 0 M 1
T 0 M 0
T M R 0
8 - B it T im e r /E v e n t
C o u n te r P r e lo a d
R e g is te r
R e lo a d
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
8 - B it T im e r /E v e n t
C o u n te r 0
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
1 /2
P F D 0
Timer/Event Counter 0
fS
Y S
D a ta B u s
/4
T 1 M 1
T 1 M 0
T M R 1
8 - B it T im e r /E v e n t
C o u n te r P r e lo a d
R e g is te r
R e lo a d
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
8 - B it T im e r /E v e n t
C o u n te r 1
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
1 /2
P F D 1
Timer/Event Counter 1
Rev. 1.00
16
October 11, 2007
HT46R343
Input/Output Ports
output by options. When the PFD function is selected,
executing ²SET [PA].3² instruction to enable PFD output and executing ²CLR [PA].3² instruction to disable
PFD output.
There are 37 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC, PD and PE,
which are mapped to the data memory of [12H], [14H],
[16H], [18H] and [1AH] respectively. All of these I/O
ports can be used for input and output operations. For
input operation, these ports are non-latching, that is, the
inputs must be ready at the T2 rising edge of instruction
²MOV A,[m]² (m=12H, 14H, 16H, 18H or 1AH). For output
operation, all the data is latched and remains unchanged
until the output latch is rewritten.
In the case of a timer/event counter OFF condition, writing data to the timer/event counter preload register will
also reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until an overflow occurs.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PEC) to control the input/output configuration. With this control register, CMOS output or Schmitt
trigger input with or without pull-high resistor structures
can be reconfigured dynamically (i.e. on-the-fly) under
software control. To function as an input, the corresponding latch of the control register must write ²1². The
input source also depends on the control register. If the
control register bit is ²1², the input will read the pad
state. If the control register bit is ²0², the contents of the
latches will move to the internal bus. The latter is possible in the ²read-modify-write² instruction.
When the timer/event counter TMR0 (TMR1) is read,
the clock is blocked to avoid errors, as this may results
in a counting error. Blocking of the clock issue should be
taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0
(TMR1) register first, before turning on the related
timer/event counter, for proper operation since the initial
value of TMR0 (TMR1) is unknown. Due to the
timer/event scheme, the programmer should pay special attention on the instruction to enable then disable
the timer for the first time, whenever there is a need to
use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function can
be operated normally.
After a device reset, the input/output lines will default to
inputs and remain at a high level or floating state, dependent upon the pull-high configuration options. Each
bit of these input/output latches can be set or cleared by
the ²SET [m].i² and ²CLR [m].i² (m=12H, 14H, 16H, 18H
or 1AH) instructions.
The definitions are as shown. The overflow signal of
timer/event 0/1 counter can be used to generate the
PFD signal. The timer prescaler is also used as the
PWM counter.
V
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
S
P A 0
P A 3
P A 4
P A 5
P B 0
P C 0
P D 0
P D 1
P D 2
P D 5
P D 6
P E 0
Q
C h ip R e s e t
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
(P D 0 o r P W M )
C K
S
Q
M
P A 3
P F D
M
R e a d D a ta R e g is te r
S y s te m
D D
P u ll- H ig h
O p tio n
U
U
~ P A 2
/P F D
/T M R 1
~ P A 7
/A N 0 ~ P B 7 /A N 7
/A N 8 ~ P C 7 /A N 1 5
/P W M 0
/P W M 1
/P C K
/T M R 0
/IN T
~ P E 7
X
P F D E N
(P A 3 )
X
W a k e - u p ( P A o n ly )
W a k e - u p o p tio n
IN T fo r P D 6 O n ly
T M R 0 fo r P D 5 O n ly
T M R 1 fo r P A 4 O n ly
Input/Output Ports
Rev. 1.00
17
October 11, 2007
HT46R343
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
two PWM functions shared with pins PD0 and PD1. If
the PWM functions are enabled, the PWM signals will
appear on PD0 and PD1, the pins are setup as outputs.
Writing a ²1² to the PD0 or PD1 data register will enable
the PWM outputs to function while writing a ²0² will force
the PD0 and PD1 outputs to remain at ²0². The I/O functions of PD0 and PD1 are as shown.
Each line of port A has the capability of waking-up the
device.
I/O
Mode
Each I/O line has a pull-high option. Once the pull-high
configuration option is selected, the I/O line has a
pull-high resistor, otherwise, there¢s none. Take note
that a non-pull-high I/O line operating in input mode will
cause a floating state.
PD0
PD1
I/P
O/P
(Normal) (Normal)
Logical
Input
PA3
Logical
Output
I/P
(PFD)
O/P
(PFD)
Logical
Input
PFD
(Timer on)
Logical
Input
Logical
Output
I/P
(PWM)
O/P
(PWM)
Logical
Input
PWM0
PWM1
It is recommended that unused I/O lines should be setup
as output pins by software instructions to avoid consuming power under input floating states.
Pin PA3 is pin-shared with the PFD signal. If the PFD
configuration option is selected, the output signal in the
output mode for PA3 will be the PFD signal generated by
the timer/event counter overflow signal. The input mode
always retains its original functions. Once the PFD option is selected, the PFD output signal is controlled by
the PA3 data register only. Writing a ²1² to the PA3 data
register will enable the PFD output function and writing
²0² will force the PA3 to remain at ²0². The I/O functions
for PA3 are shown below.
I/O
Mode
I/P
O/P
(Normal) (Normal)
PWM
The microcontroller provides a 2 channel (6+2) bits
PWM0/PWM1 output shared with PD0/PD1. The PWM
channel has its data register denoted as PWM0 and
PWM1. The frequency source of the PWM counter comes from fSYS. The PWM register is an eight bit register.
Once PD0/PD1 are selected as PWM outputs and the
output function of PD0/PD1 is enabled (PDC.0=²0² or
PDC.1=²0²), writing a 1 to the PD0/PD1 data register
will enable the PWM output function while writing a ²0²
will force the PD0/PD1 outputs to stay at ²0².
Pins PD6, PD5 and PA4 are pin-shared with INT, TMR0
and TMR1 pins respectively.
A PWM cycle is divided into four modulation cycles
(modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit
PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is
denoted by DC which is the value of PWM.7~PWM.2.
The PB and PC can also be used as A/D converter inputs. The A/D function will be described later. There are
Group 2 is denoted by AC which is the value of
PWM.1~PWM.0.
Note:
fS
Y S
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
/2
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
6+2 PWM Mode
Rev. 1.00
18
October 11, 2007
HT46R343
In a PWM cycle, the duty cycle of each modulation cycle
is shown in the table.
Parameter
AC (0~3)
Duty Cycle
i<AC
DC+1
64
i³AC
DC
64
Modulation cycle i
(i=0~3)
The ADRH and ADRL registers are the A/D conversion
result register higher-order byte and lower-order byte
and are read-only. After the A/D conversion has completed, the ADRL and ADRH registers should be read to
get the conversion result data. The ADCR register is an
A/D converter control register, which defines the A/D
channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. It
is used to start an A/D conversion, define the PB configuration, select the converted analog channel, and give
the START bit a raising edge and a falling edge
(0®1®0). At the end of an A/D conversion, the EOCB
bit is cleared and an A/D converter interrupt occurs, if
the A/D converter interrupt is enabled. The ACSR
register is an A/D clock setting register, which is used to
select the A/D clock source.
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
PWM
Modulation
Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
fSYS/64
fSYS/256
[PWM]/256
The A/D converter control register is used to control the
A/D converter. Bit2~bit0 of the ADCR register and bit 4
of ADCS are used to select an analog input channel.
There are a total of 16 channels to select. Bit5~bit3 of
the ADCR register and bit 5 of ADCS are used to set the
PB, PC configurations. PB, PC can be configured as an
analog input or as a digital I/O line decided by these 4
bits. Once a PB, PC line is selected as an analog input,
the I/O functions and pull-high resistor of this I/O line are
disabled, and the A/D converter circuit is powered on.
The EOCB bit, bit6 of ADCR, is the end of A/D conversion flag. This bit is monitored to check when the A/D
conversion has completed. The START bit of the ADCR
register is used to initiate the A/D conversion process.
When the START bit is provided with a raising edge and
then a falling edge, the A/D conversion process will begin. In order to ensure that the A/D conversion is completed, the START should remain at ²0² until the EOCB
flag is cleared to ²0² which indicates the end of the A/D
conversion.
LED Driver
The device provides a maximum of 8´8 LED drivers
which uses I/O Ports PA and PE with double the usual
sink/source current drive capabilities. To use the LED
driver function, PA and PE must be setup as outputs.
P A 0 ~ P A 7
P E 0 ~ P E 7
H T -M C U
L E D D is p la y
8 x 8 A rra y
Peripheral Clock Output - PCK
The device also provides a Peripheral Clock Output
(PCK) which is pin-shared with PD2. Once the PD2 is
selected as the PCK outputs and the output function of
PD2 is enabled (PDC.2 =²0²), writing 1 to PA0 data register will enable the PCK output function and writing ²0²
will force the PD2 to stay at ²0².
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
The PCK clock frequency can be optional : fSYS/16 or
fSYS/32 ( by configuration option).
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
PCK output = 500kHz or 250kHz if fSYS=8MHz.
Recommend to clear PD2 before entering HALT mode.
fS
Y S
/4
fP
P D 2
C K
P C K D iv id e r
P C K C lo c k
P C K D iv id e r R a tio O p tio n
(¸ 4 o r ¸ 8 )
M
U
X
Important Note for A/D initialisation:
Special care must be taken to initialise the A/D converter each time the Port B, Port C A/D channel selection bits are modified, otherwise the EOCB flag may be
in an undefined condition. An A/D initialisation is implemented by setting the START bit high and then clearing
it to zero within 10 instruction cycles of the Port B, Port C
channel selection bits being modified. Note that if the
Port B, Port C channel selection bits are all cleared to
zero then an A/D initialisation is not required.
P D 2 /P C K
P C K O p tio n
A/D Converter
The 16 channel 12-bit resolution A/D converter is implemented in the microcontrollers. The reference voltage
for the A/D is VDD. The A/D converter contains 4 special
registers, which are; ADRL, ADRH, ADCR and ACSR.
Rev. 1.00
19
October 11, 2007
HT46R343
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADRL
D3
D2
D1
D0
¾
¾
¾
¾
ADRH
D11
D10
D9
D8
D7
D6
D5
D4
Note:
D0~D11 is A/D conversion result data bit LSB~MSB.
ADRL (20H), ADRH (21H) Register
Bit No.
Label
Function
0
1
2
ACS0
ACS1
ACS2
ACS3[ACSR], ACS2, ACS1, ACS0: selected A/D channel
3
4
5
PCR0
PCR1
PCR2
Port B, C configuration selection.
If PCR0, PCR1, PCR2 and PCR3[ACSR] are all zero,
the ADC circuit is power off to reduce power consumption
6
EOCB
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialised by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialisation².
7
START Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
ADCR (22H) Register
ACS3, ACS2, ACS1, ACS0
Channel
ACS3, ACS2, ACS1, ACS0
Channel
0000
AN0
1000
AN8
0001
AN1
1001
AN9
0010
AN2
1010
AN10
0011
AN3
1011
AN11
0100
AN4
1100
AN12
0101
AN5
1101
AN13
0110
AN6
1110
AN14
0111
AN7
1111
AN15
A/D Channel
Bit No.
0
1
Label
Function
Select the A/D converter clock source.
0, 0: fSYS/2
ADCS0
0, 1: fSYS/8
ADCS1
1, 0: fSYS/32
1, 1: Undefined
2~3
¾
4
ACS3
Bit3 of 4bit A/D channel selection
Unused bit, read as ²0².
5
PCR3
Bit3 of 4bit Port B, C configuration selection.
6
¾
7
TEST
Unused bit, read as ²0².
For internal test only.
ACSR (23H) Register
Rev. 1.00
20
October 11, 2007
HT46R343
PCR3
PCR2
PCR1
PCR0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
0
1
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
AN0
0
0
1
0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB7
PB6
PB5
PB4
PB3
PB2
AN1
AN0
0
0
1
1
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB7
PB6
PB5
PB4
PB3
AN2
AN1
AN0
0
1
0
0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB7
PB6
PB5
PB4
AN3
AN2
AN1
AN0
0
1
0
1
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB7
PB6
PB5
AN4
AN3
AN2
AN1
AN0
0
1
1
0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB7
PB6
AN5
AN4
AN3
AN2
AN1
AN0
0
1
1
1
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
1
0
0
0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
1
0
0
1
PC7
PC6
PC5
PC4
PC3
PC2
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
1
0
1
0
PC7
PC6
PC5
PC4
PC3
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
1
0
1
1
PC7
PC6
PC5
PC4
AN11 AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
0
0
PC7
PC6
PC5
AN12 AN11 AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
0
1
PC7
PC6
AN13 AN12 AN11 AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
1
0
PC7
AN14 AN13 AN12 AN11 AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
1
1
AN15 AN14 AN13 AN12 AN11 AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Port B, C configuration
M in im u m
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D
tA
P C R 2 ~
P C R 0
s a m p lin g tim e
A /D
tA
D C S
0 0 0 B
s a m p lin g tim e
A /D s a m p lin g tim e
tA D C S
D C S
1 0 0 B
1 0 0 B
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
A /D c lo c k m u s t b e fS
tA D C S = 3 2 tA D
tA D C = 8 0 tA D
Y S
/2 , fS
tA D C
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
tA D C
A /D c o n v e r s io n tim e
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
Rev. 1.00
21
October 11, 2007
HT46R343
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov
ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
; reset A/D
clr
START
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp
polling_EOC
; continue polling
mov
a,ADRH
; read conversion result high byte value from the ADRH register
mov
adrh_buffer,a
; save result to user defined memory
mov
a,ADRL
; read conversion result low byte value from the ADRL register
mov
adrl_buffer,a
; save result to user defined memory
:
:
jmp
start_conversion
; start next A/D conversion
Example: using interrupt method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
mov
a,00100000B
ADCR,a
:
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
clr
START
clr
ADF
set
EADI
set
EMI
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov
acc_stack,a
mov
a,STATUS
mov
status_stack,a
:
:
mov
a,ADRH
mov
adrh_buffer,a
mov
a,ADRL
mov
adrl_buffer,a
clr
START
set
START
clr
START
:
:
EXIT_INT_ISR:
mov
a,status_stack
mov
STATUS,a
mov
a,acc_stack
reti
Rev. 1.00
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
; save ACC to user defined memory
; save STATUS to user defined memory
; read conversion result high byte value from the ADRH register
; save result to user defined register
; read conversion result low byte value from the ADRL register
; save result to user defined register
; reset A/D
; start A/D
; restore STATUS from user defined memory
; restore ACC from user defined memory
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Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as what happens when changing a
battery, the LVR will automatically reset the device internally.
V D D
5 .5 V
V
O P R
5 .5 V
V
The LVR includes the following specifications:
2 .2 V
· The low voltage (0.9V~VLVR) has to remain in its origi-
nal state to exceed tLVR. If the low voltage state does
not exceed tLVR, the LVR will ignore it and will not perform a reset function.
0 .9 V
VOPR is the voltage range for proper chip
operation at 4MHz system clock.
Note:
· The LVR uses the ²OR² function with the external RES
signal to perform a chip reset.
V
L V R
3 .0 V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilised, the SST provides an extra delay of 1024 system
clock pulses before beginning normal operation.
*2: Since the low voltage has to maintain in its original state and exceed tLVR, therefore tLVR delay enter the
reset mode.
OP Amplifier/Comparator
The calibration process is as follows:
The devices include an integrated operational amplifier
or comparator, selectable via configuration option. The
default is function is comparator. The input voltage offset is adjustable by using a common mode input to calibrate the offset value.
A P N
A P P
A P N
V R
S 1
S 2
A P O
S 3
· Set bit AOFM=1 to select the offset cancellation mode
A P O
- this closes switch S3
· Set the ARS bit to select which input pin is the
A P P
reference voltage - closes either switch S1 or S2
· Adjust bits AOF0~AOF3 until the output status
OPAOP has changed.
· Set AOFM=0 to select the normal operating mode
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Bit No.
Label
Function
0
1
2
3
AOF0
AOF1
AOF2
AOF3
OP amp/comparator input offset voltage cancellation control bits
4
ARS
OP amp/comparator input offset voltage cancellation reference selection bit
1/0 : select OPP/OPN (CP/CN) as the reference input
5
AOFM
6
OPAOP
OP amp/comparator output; positive logic
7
OPAEN
OP amp/comparator enable/disable (1/0)
If OP/comparator is disabled, output is floating.
Input offset voltage cancellation mode and OP amp/comparator mode selection
1: input offset voltage cancellation mode
0: OP amp/comparator
OPAC (1FH) Register
If the OP amp/comparator is disabled, the power consumption will be very small. To ensure that power consumption is
minimised when the device is in the Power-down mode, the OP amp/comparator should be switched off by clearing bit
OPAEN to 0 before entering the Power-down mode.
Configuration Options
The following table shows the various microcontroller configuration options. All of the configuration options must be
properly defined to ensure correct system functioning.
No.
Options
1
WDT clock source: WDTOSC or T1 (fSYS/4)
2
WDT function: enable or disable
3
CLRWDT instruction(s): one or two clear WDT instruction(s)
4
System oscillator: RC or crystal
5
Pull-high resistors (PA, PB, PD): none or pull-high
6
PWM enable or disable
7
PA0~PA7 wake-up: enable or disable
8
PFD enable or disable
9
Low voltage reset selection: enable or disable LVR function.
10
Comparator or OP selection
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Application Circuits
V
D D
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
R E S
P A 5 ~ P A 7
V
D D
P B 0 /A N 0 ~ P B 7 /A N 7
4 7 0 p F
P C 0 /A N 8 ~ P C 7 /A N 1 5
0 .1 m F
V S S
O S C
C ir c u it
P A 0 ~ P A 2
P A 3 /P F D
P A 4 /T M R 1
O S C 1
O S C 2
P D 0 /P W M
P D 1 /P W M
P D 2 /P C
P D 5 /T M R
P D 6 /IN
R
0
O S C
1
K
T
O S C 1
fS
C 1
0
P E 0 ~ P E 7
Y S
/4
O S C 2
O S C 1
C 2
A P N
A P P
P B 0 /A N 0 A P O
R 1
H T 4 6 R 3 4 3
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 2
C r y s ta l/R e s o n a to r
S y s te m O s c illa to r
F o r R 1 , C 1 , C 2 s e e n o te
O S C C ir c u it
Note: 1. Crystal/resonator system oscillators
For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For
resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is not
necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator when
VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2 should be
selected in consultation with the crystal/resonator manufacturer specifications.
2. Reset circuit
The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of
the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.
3. For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information.
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s u c c e s s f u l oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
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Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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HT46R343
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
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SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
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HT46R343
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
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Package Information
44-pin QFP (10´10) Outline Dimensions
H
C
D
G
2 3
3 3
I
3 4
2 2
L
F
A
B
E
1 2
4 4
K
a
J
1
Symbol
Rev. 1.00
1 1
Dimensions in mm
Min.
Nom.
Max.
A
13
¾
13.4
B
9.9
¾
10.1
C
13
¾
13.4
D
9.9
¾
10.1
E
¾
0.8
¾
F
¾
0.3
¾
G
1.9
¾
2.2
H
¾
¾
2.7
I
0.25
¾
0.5
J
0.73
¾
0.93
K
0.1
¾
0.2
L
¾
0.1
¾
a
0°
¾
7°
39
October 11, 2007
HT46R343
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Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
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