ETC MU9C1480L

Data Sheet Draft
MU9C1480A/L LANCAMs®
APPLICATION BENEFITS
DISTINCTIVE CHARACTERISTICS
The 1024 x 64-bit LANCAM facilitates numerous
operations:
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memory (CAM)
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16-bit I/O
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16-bit CAM/RAM segments with MUSIC’s patented
partitioning
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/MA and /MM output flags to enable faster system
performance
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Readable Device ID
Fast 90 ns compare speed
Dual configuration register set for rapid context
switching
Selectable faster operating mode with no wait
states after a no-match
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Validity bit setting accessible from the
Status register
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Single cycle reset for Segment Control register
44-Pin PLCC package / 44-Pin TQFP package
5 Volt (1480A) or 3.3 Volt (1480L) operation
DATA (6 4 )
M UX
DQ (1 5 — 0 )
I/O BU FFE E RS
DATA (1 6 )
(1 6 )
V CC
G ND
DATA (1 6 )
TR ANS LA TE
8 0 2.3 /8 02 .5
DATA (1 6 )
DE M UX
CO M M A NDS & S TATU S
(1 6 )
CO M P ARAN D*
S O U RCE AN D
DE S TINA TIO N
S E G M E NT
CO U NTE R S
M AS K 1
M AS K 2
ADD RE S S D E C O DE R
/E
INS TRUC TIO N ( W /O )*
/W
ADD RE S S ADD RE S S
CO N TR O L
10
NE X T FRE E ADDR E S S (R/O )
/CM
CO N TR O L
/RE S E T
DATA (6 4 )
S E G M E NT C O NTR O L
16
P AG E ADDR E S S (LO CA L)
DE V IC E S E LE CT (G LO B AL)
/E C
M ATCH ADD R
& /M A FLA G
CAM AR RAY
1 0 2 4 W ORDS
X 6 4 B ITS
1 K X 2 V A LIDITY BITS
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New package saves space
New speed grade allows processing of both
DA and SA within 560 ns, equivalent to 111,
10 Base-T or 11, 100 Base-T Ethernet ports
Full CAM features allow all operations to
be masked on a bit-by-bit basis
Expanded powerful instruction set for any
list processing needs
Shiftable Comparand and mask registers
assist in proximate matching algorithms
Fully compatible with all MUSIC LANCAM
series, cascadable to any practical length
without performance penalties
1024 x 64-bit CMOS content-addressable
/MA
P RIO R ITY E NCO D E R
Ø
Ø
Ø
/M M
2
11
/FF
S TATU S (1 5 -0 ) ( R/O )*
/M M , /F L
2
S TATU S (3 1 -1 6 ) (R /O )
RE G IS TE R S E T
M ATCH
AND
FL AG
LO G IC
/FI
/M F
/MI
Block Diagram
LANCAM, the MUSIC logo, and the phrase “MUSIC Semiconductors” are registered trademarks of MUSIC Semiconductors. MUSIC is
a trademark of MUSIC Semiconductors. Certain features of this device are patented under US Patent 5,383,146.
Note: This document version has not completed MUSIC’s internal approval process, therefore it should
be rechecked with a released version or with factory personnel.
21 May 1999 Rev. 3.0 Draft
MU9C1480A/L Draft
GENERAL DESCRIPTION
The MU9C1480A and MU9C1480L LANCAMs are 1024 x
64-bit content-addressable memories (CAMs), with a 16-bit
wide interface. They are pin compatible with all devices in the
MUSIC LANCAM family.
data in a short, constant time period, no matter how many
entries are in the database. The ability to search data words
up to 64 bits wide allows large address spaces to be
searched rapidly and efficiently. A patented architecture
links each CAM entry to associated data and makes this
data available for use after a successful compare operation.
Content-addressable memories, also known as associative
memories, operate in the converse way to random access
memories (RAM). In RAM, the input to the device is an
address and the output is the data stored at that address.
In CAM, the input is a data sample and the output is a flag
to indicate a match and the address of the matching data.
As a result, CAM searches large databases for matching
The MUSIC LANCAMs are ideal for address filtering and
translation applications in LAN switches and routers. The
LANCAMs are also well suited to encryption, database
accelerators, and image processing.
OPERATIONAL OVERVIEW
To use the LANCAM, the user loads the data into the
Comparand register, which is automatically compared to all
valid CAM locations. The device then indicates whether
or not one or more of the valid CAM locations contains
data that matches the target data. The status of each CAM
location is determined by two validity bits at each memory
location. The two bits are encoded to render four validity
conditions: Valid, Empty, Skip, and RAM, shown in
Table 1. The memory can be partitioned into CAM and
associated RAM segments on 16-bit boundaries, but by
using one of the two available mask registers, the CAM/RAM
partitioning can be set at any arbitrary size between zero
and 64 bits.
Comparand, and mask registers automatically triggers a
compare. Compares also may be initiated by a command
to the device. Associated RAM data is available
immediately after a successful compare operation. The
Status register reports the results of compares including
all flags and addresses. Two mask registers are available
and can be used in two different ways: to mask
comparisons or to mask data writes. The RAM validity
type allows additional masks to be stored in the CAM
array where they may be retrieved rapidly.
A simple four-wire control interface and commands
loaded into the Instruction decoder control the device.
A powerful instruction set increases the control flexibility
and minimizes software overhead. Additionally,
dedicated pins for match and multiple-match flags
enhance performance when the device is controlled by a
state machine. These and other features make the
LANCAM a powerful associative memory that drastically
reduces search delays.
The LANCAM’s internal data path is 64 bits wide for rapid
internal comparison and data movement. Vertical cascading
of additional LANCAMs in a daisy chain fashion extends
the CAM memory depth for large databases. Cascading
requires no external logic. Loading data to the Control,
Skip Bit
0
0
1
1
Empty Bit
0
1
0
1
/W
LOW
LOW
HIGH
HIGH
Entry Type
Valid
Empty
Skip
RAM
Cycle Type
Command Write cycle
Data Write cycle
Command Read cycle
Data Read cycle
Table 2: I/O Cycles
Table 1: Entry Types vs. Validity Bits
Rev. 3.0 Draft
/CM
LOW
HIGH
LOW
HIGH
2
MU9C1480A/L Draft
PIN DESCRIPTIONS
All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs
should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout
and bypassing techniques. Refer to the Electrical Characteristics section for more information.
/E (Chip Enable, Input, TTL)
The /E input enables the device while LOW. The falling
edge registers the control signals /W, /CM, and /EC. The
rising edge locks the daisy chain, turns off the DQ pins,
and clocks the Destination and Source Segment counters.
The four cycle types enabled by /E are shown in Table 2.
and 5b on page 12 explain the effect of the /EC signal on a
device with or without a match in both Standard and Enhanced
modes. /EC must be HIGH during initialization.
DQ15–0 (Data Bus, I/O, TTL)
The DQ15–0 lines convey data, commands, and status to
and from the LANCAM. /W and /CM control the direction
and nature of the information that flows to or from the
device. When /E is HIGH, DQ15–0 go to HIGH-Z.
/W (Write Enable, Input, TTL)
The /W input selects the direction of data flow during a
device cycle. /W LOW selects a Write cycle and /W HIGH
selects a Read cycle.
/MF (Match Flag, Output, TTL)
The /MF output goes LOW when one or more valid matches
occur during a compare cycle. /MF becomes valid after /E
goes HIGH on the cycle that enables the daisy chain (on
the first cycle that /EC is registered LOW by the previous
falling edge of /E; see Figure 6 on page 14). In a daisy
chain, valid match(es) in higher priority devices are passed
from the /MI input to /MF. If the daisy chain is enabled but
the match flag is disabled in the Control register, the /MF
output only depends on the /MI input of the device
(/MF=/MI). /MF is HIGH if there is no match or when the
daisy chain is disabled (/E goes HIGH when /EC was HIGH
on the previous falling edge of /E). The System Match flag
is the /MF pin of the last device in the daisy chain. /MF will
be reset when the active configuration register set is changed.
/CM (Data/Command Select, Input, TTL)
The /CM input selects whether the input signals on
DQ15–0 are data or commands. /CM LOW selects Command
cycles and /CM HIGH selects Data cycles.
/EC (Enable Daisy Chain, Input, TTL)
The /EC signal performs two functions. The /EC input enables
the /MF output to show the results of a comparison, as shown
in Figure 6 on page 14. If /EC is LOW at the falling edge of /E
in a given cycle, the /MF output is enabled. Otherwise, the
/MF output is held HIGH. The /EC signal also enables the
/MF– /MI daisy chain, which serves to select the device with
the highest-priority match in a string of LANCAMs. Tables 5a
/ MM
/ FF
/ FI
/C M
/ EC
39
38
37
36
35
34
33
32
31
30
29
G ND
DQ 4
DQ 5
V CC
V CC
/M A
/ MI
/ MF
G ND
/ R E S ET
V CC
V CC
TE S T1
/E
/W
G ND
TES T 2
G ND
G ND
DQ 6
DQ 7
V CC
7
8
9
10
11
12
13
14
15
16
17
4 4 -pi n PTQFP
L CC
(Top V ie w )
39
38
37
36
35
34
33
32
31
30
29
/M A
/ MI
/ MF
G ND
/ R E S ET
V CC
V CC
TE S T1
/E
/W
G ND
28
27
26
25
24
23
22
21
20
19
18
28
27
26
25
24
23
22
21
20
19
18
G ND
D Q 15
D Q 14
D Q 13
D Q 12
G ND
D Q 11
D Q 10
D Q9
D Q8
G ND
G ND
D Q 15
D Q 14
D Q 13
D Q 12
G ND
D Q 11
D Q 10
D Q9
D Q8
G ND
PLCC Pinout Diagram
40
41
42
(Top V ie w )
43
44
1
2
3
4
5
6
4 4 -pi n P L CC
G ND
V CC
40
41
42
43
44
1
2
3
4
5
6
TES T 2
G ND
G ND
DQ 6
DQ 7
V CC
7
8
9
10
11
12
13
14
15
16
17
D Q0
D Q1
D Q2
D Q3
/ MM
/ FF
/ FI
/C M
/ EC
G ND
V CC
D Q0
D Q1
D Q2
D Q3
G ND
DQ 4
DQ 5
V CC
V CC
TQFP Pinout Diagram
3
Rev. 3.0 Draft
MU9C1480A/L Draft
PIN DESCRIPTIONS Continued
/MI (Match Input, Input, TTL)
The /MI input prioritizes devices in vertically cascaded
systems. It is connected to the /MF output of the previous
device in the daisy chain. The /MI pin on the first device in
the chain must be tied HIGH.
/RESET (Reset, Input, TTL)
/RESET must be driven LOW to place the device in a known
state before operation, which will reset the device to the
conditions shown in Table 4 on page 10. LANCAM ‘A’
devices have a hardware reset that operates in parallel with
the internal Power-on-reset circuitry, and sets the device to
the same condition. For compatibility with the MU9C1480,
the /RESET pin has an internal pull-up resistor and may be
left unconnected. The /RESET pin should be driven by
TTL levels, not directly by an RC timeout. /E must be kept
HIGH during /RESET.
/MA (Device Match Flag, Output, TTL)
The /MA output is LOW when one or more valid matches
occur during the current or the last previous compare cycle.
The /MA output is not qualified by /EC or /MI, and reflects
the match flag from that specific device’s Status register.
/MA will be reset when the active register set is changed.
/MM (Device Multiple Match Flag, Output, TTL)
The /MM output is LOW when more than one valid match
occurs during the current or the last previous compare cycle.
The /MM output is not qualified by /EC or /MI, and reflects
the multiple match flag from that specific device’s Status
register. /MM will be reset when the active register set is changed.
/FF (Full Flag, Output, TTL)
If enabled in the Control register, the /FF output goes LOW
when no empty memory locations exist within the device
(and in the daisy chain above the device as indicated by
the /FI pin). The System Full flag is the /FF pin of the last
device in the daisy chain, and the Next Free address resides
in the device with /FI LOW and /FF HIGH. If disabled in the
Control register, the /FF output only depends on the /FI
input (/FF = /FI).
TEST1, TEST2 (Test, Input, TTL)
These pins enable MUSIC production test modes that are
not usable in an application. They should be connected to
ground, either directly or through a pull-down resistor, or
they may be left unconnected. These pins may not be
implemented on all versions of these products.
VCC, GND (Positive Power Supply, Ground)
These pins are the power supply connections to the
LANCAM. VCC must meet the voltage supply requirements
in the Operating Conditions section relative to the GND
pins, which are at 0 volts (system reference potential), for
correct operation of the device. All the ground and power
pins must be connected to their respective planes with
adequate bulk and high frequency bypassing capacitors in
close proximity to the device. The MU9C1480A and
MU9C1480L are compatible with the original MU9C1480
connections, and may be operated at -90 or slower
switching characteristics without the GND connections on
pins 1, 7, 18, 23, and 29; and the VCC connections on pins
6, 10, and 17.
/FI (Full Input, Input, TTL)
The /FI input generates a CAM-Memory-System-Full
indication in vertically cascaded systems. It is connected
to the /FF output of the previous device in the daisy chain.
The /FI pin on the first device in a chain must be tied LOW.
FUNCTIONAL DESCRIPTION
I/O bus. Internally, data is handled on a 64-bit basis, since
the Comparand register, the mask registers, and each
memory entry are 64 bits wide. Memory entries are globally
configurable into CAM and RAM segments on 16-bit
boundaries, as described in US Patent 5,383,146 assigned
to MUSIC Semiconductors. Seven different CAM/RAM
splits are possible, with the CAM width going from one to
four segments, and the remaining RAM width going from
three to zero segments. Finer resolution on compare width
is possible by invoking a mask register during a compare,
which does global masking on a bit basis. The CAM subfield
contains the associative data, which enters into compares,
while the RAM subfield contains the associated data, which
is not compared. In LAN bridges, the RAM subfield could
hold, for example, port-address and aging information
The LANCAM is a content-addressable memory (CAM)
with 16-bit I/O for network address filtering and translation,
virtual memory, data compression, caching, and table lookup
applications. The memory consists of static CAM,
organized in 64-bit data fields. Each data field can be
partitioned into a CAM and a RAM subfield on 16-bit
boundaries. The contents of the memory can be randomly
accessed or associatively accessed by the use of a compare.
During automatic comparison cycles, data in the
Comparand register is automatically compared with the
“Valid” entries in the memory array. The Device ID can be
read using a TCO PS instruction (see Table 12 on page 22).
The data inputs and outputs of the LANCAM are
multiplexed for data and instructions over a 16-bit
Rev. 3.0 Draft
4
MU9C1480A/L Draft
FUNCTIONAL DESCRIPTION Continued
related to the destination or source address information
held in the CAM subfield of a given location. In a translation
application, the CAM field could hold the dictionary entries,
while the RAM field holds the translations, with almost
instantaneous response.
register’s contents are reset, enable or disable Match flag,
enable or disable Full flag, CAM/RAM partitioning, disable
or select masking conditions, disable or select
auto-incrementing or auto-decrementing the Address
register, and select Standard or Enhanced mode. The active
Segment Control register contains separate counters to
control the writing of 16-bit data segments to the selected
persistent destination, and to control the reading of 16-bit
data segments from the selected persistent source.
Each entry has two validity bits (known as Skip bit and
Empty bit) associated with it to define its particular type:
Empty, Valid, Skip, or RAM. When data is written to the
active Comparand register, and the active Segment Control
register reaches its terminal count, the contents of the
Comparand register are automatically compared with the
CAM portion of all the valid entries in the memory array.
For added versatility, the Comparand register can be
barrel-shifted right or left one bit at a time. A Compare
instruction then can be used to force another compare
between the Comparand register and the CAM portion of
memory entries of any one of the four validity types. After
a Read or Move from Memory operation, the validity bits
of the location read or moved will be copied into the Status
register, where they can be read using Command
Read cycles.
Data can be moved from one of the data registers (CR,
MR1, or MR2) to a memory location that is based on the
results of the last comparison (Highest-Priority Match or
Next Free), or to an absolute address, or to the location
pointed to by the active Address register. Data can also be
written directly to the memory from the DQ bus using any
of the above addressing modes. The Address register may
be directly loaded and may be set to increment or
decrement, allowing DMA-type reading or writing from
memory.
There are two active mask registers at any one time, which
can be selected to mask comparisons or data writes. Mask
Register 1 has both a foreground and background mode to
support rapid context switching. Mask Register 2 does not
have this mode, but can be shifted left or right one bit at a
time. For masking comparisons, data stored in the active
selected mask register determines which bits of the
comparand are compared against the valid contents of the
memory. If a bit is set HIGH in the mask register, the same
bit position in the Comparand register becomes a “don’t
care” for the purpose of the comparison with all the memory
locations. During a Data Write cycle or a MOV instruction,
data in the specified active mask register can also determine
which bits in the destination will be updated. If a bit is
HIGH in the mask register, the corresponding bit of the
destination is unchanged.
The match line associated with each memory address is fed
into a priority encoder where multiple responses are
resolved, and the address of the highest-priority responder
(the lowest numerical match address) is generated. In LAN
applications, a multiple response might indicate an error. In
other applications the existence of multiple responders may
be valid.
Two sets of configuration registers (Control, Segment
Control, Address, Mask Register 1, and Persistent Source
and Destination) are provided to permit rapid context
switching between foreground and background activities.
The currently active set of configuration registers controls
writes, reads, moves, and compares. The foreground set
typically would be pre-loaded with values useful for
comparing input data, often called filtering, while the
background set would be pre-loaded with values useful for
housekeeping activities such as purging old entries.
Moving from the foreground task of filtering to the
background task of purging can be done by issuing a single
instruction to change the current set of configuration
registers. The match condition of the device is reset
whenever the active register set is changed.
Four input control signals and commands loaded into an
instruction decoder control the LANCAM. Two of the four
input control signals determine the cycle type. The control
signals tell the device whether the data on the I/O bus
represents data or a command, and is input or output.
Commands are decoded by instruction logic and control
moves, forced compares, validity bit manipulations, and
the data path within the device. Registers (Control, Segment
Control, Address, Next Free Address, etc.) are accessed
using Temporary Command Override instructions. The data
path from the DQ bus to/from data resources (comparand,
masks, and memory) within the device are set until changed
by Select Persistent Source and Destination instructions.
The active Control register determines the operating
conditions within the device. Conditions set by this
After a Compare cycle (caused by either a data write to the
Comparand or mask registers, a write to the Control register,
5
Rev. 3.0 Draft
MU9C1480A/L Draft
FUNCTIONAL DESCRIPTION Continued
A Page Address register in each device simplifies vertical
expansion in systems using more than one LANCAM. This
register is loaded with a specific device address during
system initialization, which then serves as the higher-order
address bits. A Device Select register allows the user to
target a specific device within a vertically cascaded system
by setting it equal to the Page Address Register value, or
to address all the devices in a string at the same time by
setting the Device Select value to FFFFH.
or a forced compare), the Status register contains the
address of the Highest-Priority Matching location in that
device, concatenated with its page address, along with
flags indicating internal match, multiple match, and full.
When the Status register is read with a Command Read
cycle, the device with the Highest-Priority Match will
respond, outputting the System Match address to the DQ
bus. The internal Match (/MA) and Multiple Match (/MM)
flags are also output on pins. Another set of flags (/MF
and /FF) that are qualified by the match and full flags of
previous devices in the system also are available directly
on output pins, and are independently daisy-chained to
provide System Match and Full flags in vertically cascaded
LANCAM arrays. In such arrays, if no match occurs during
a comparison, read access to the memory and all the
registers except the Next Free register is denied to prevent
device contention. In a daisy chain, all devices will respond
to Command and Data Write cycles, depending on the
conditions shown in Tables 5a and 5b on page 12, unless
the operation involves the Highest-Priority Match address
or the Next Free address; in which case, only the specific
device having the Highest-Priority match or the Next Free
address will respond.
Figure 1a shows expansion using a daisy chain. Note that
system flags are generated without the need for external
logic. The Page Address register allows each device in the
vertically cascaded chain to supply its own address in the
event of a match, eliminating the need for an external priority
encoder to calculate the complete Match address at the
expense of the ripple-through time to resolve the HighestPriority match. The Full flag daisy-chaining allows
Associative writes using a Move to Next Free Address
instruction, which does not need a supplied address.
Figure 1b shows an external PLD implementation of a simple
priority encoder that eliminates the daisy chain ripplethrough delays for systems requiring maximum performance
from many CAMs.
OPERATIONAL CHARACTERISTICS
Throughout the following, “aaaH” represents a three-digit
hexadecimal number “aaa,” while “bbB” represents a twodigit binary number “bb.” All memory locations are written
to or read from in 16-bit segments. Segment 0 corresponds to
the lowest order bits (bits 15–0) and Segment 3 corresponds
to the highest order bits (bits 63–48).
The Comparand register is the default source and
destination for Data Read and Write cycles. This default
state can be overridden independently by executing a Select
Persistent Source or Select Persistent Destination
instruction, selecting a different source or destination for
data. Subsequent Data Read or Data Write cycles will
access that source or destination until another SPS or SPD
instruction is executed. The currently selected persistent
source or destination can be read back through a TCO PS
or PD instruction. The sources and destinations available
for persistent access are those resources on the 64-bit bus:
Comparand register, Mask Register 1, Mask Register 2, and
the Memory array.
THE CONTROL BUS
Refer to the Block Diagram on page 1 for the following
discussion. The inputs Chip Enable (/E), Write Enable (/W),
Command Enable (/CM), and Enable Daisy Chain (/EC) are
the primary control mechanism for the LANCAM. The /EC
input of the Control bus enables the /MF Match flag output
when LOW and controls the daisy chain operation.
Instructions are the secondary control mechanism. Logical
combinations of the Control Bus inputs, coupled with the
execution of Select Persistent Source (SPS), Select Persistent
Destination (SPD), and Temporary Command Override
(TCO) instructions allow the I/O operations to and from
the DQ15–0 lines to the internal resources, as shown in
Table 3 on page 9.
Rev. 3.0 Draft
The default destination for Command Write cycles is the
Instruction decoder, while the default source for Command
Read cycles is the Status register.
Temporary Command Override (TCO) instructions provide
access to the Control register, the Page Address register,
the Segment Control register, the Address register, the Next
Free Address register, and Device Select register. TCO
6
MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
instructions are active only for one Command Read or
Write cycle after being loaded into the Instruction decoder.
return to a foreground network filtering task from a
background housekeeping task.
The data and control interfaces to the LANCAM are
synchronous. During a Write cycle, the Control and Data
inputs are registered by the falling edge of /E. When writing
to the persistently selected data destination, the
Destination Segment counter is clocked by the rising edge
of /E. During a Read cycle, the Control inputs are registered
by the falling edge of /E, and the Data outputs are enabled
while /E is LOW. When reading from the persistently
selected data source, the Source Segment counter is
clocked by the rising edge of /E.
Writing a value to the Control register or writing data to the
last segment of the Comparand or either mask register will
cause an automatic comparison to occur between the
contents of the Comparand register and the words in the
CAM segments of the memory marked valid, masked by
MR1 or MR2 if selected in the Control register.
Instruction Decoder
The Instruction decoder is the write-only decode logic for
instructions and is the default destination for Command
Write cycles. If an instruction’s Address Field flag (bit 11)
is set to a 1, it is a two-cycle instruction that is not executed
immediately. For the next cycle only, the data from a
Command Write cycle is loaded into the Address register
and the instruction then completes at that address. The
Address register will then increment, decrement, or stay at
the same value depending on the setting of Control Register
bits CT3 and CT2. If the Address Field flag is not set, the
memory access occurs at the address currently contained
in the Address register.
THE REGISTER SET
The Control, Segment Control, Address, Mask Register 1,
and the Persistent Source and Destination registers are
duplicated, with one set termed the Foreground set and
the other the Background set. The active set is chosen by
issuing Select Foreground Registers or Select Background
Registers instructions. By default, the Foreground set is
active after a reset. Having two alternate sets of registers
that determine the device configuration allows for a rapid
V cc
Vcc
16
D Q 15–0
D Q 15–0
/E
/E
/W
/W
/MI
/MI
P LD
/ FI
L AN C AM
LANCAM
/ FF
/C M
/C M
/EC
/EC
/MF
D Q 15–0
/MI
/MA
/E
/MI
/ FI
/W
/C M
L AN C AM
LANCAM
/ FF
/MA
/EC
/MF
/MI
LANCAM
/MA
D Q 15–0
/E
/MI
/MI
/ FI
LANCAM
/W
L AN C AM
/C M
/EC
/ FF
/MF
/MA
S YS TE M F U L L
S Y S TE M
M ATCH
S YS TE M M ATC H
Figure 1a: Vertical Cascading
Figure 1b: External Prioritizing
7
Rev. 3.0 Draft
MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
Control Register (CT)
The Control register contains a number of switches that
configure the LANCAM, as shown in Table 8 on page 21. It
is written or read using a TCO CT instruction. If bit 15 of
the value written during a TCO CT is a 0, the device is reset
(and all other bits are ignored). See Table 4 on page 10 for
the Reset states. Bit 15 always reads back as a 0. A write to
the Control register causes an automatic compare to occur
(except in the case of a reset). Either the Foreground or
Background Control register will be active, depending on
which register set has been selected, and only the active
Control register will be written to or read from.
Control Register bits 8–6 control the CAM/RAM
partitioning. The CAM portion of each word may be sized
from a full 64 bits down to 16 bits in 16-bit increments. The
RAM portion can be at either end of the 64-bit word.
Compare masks may be selected by bit 5 and bit 4. Mask
Register 1, Mask Register 2, or neither may be selected to
mask compare operations. The address register behavior is
controlled by bit 3 and bit 2, and may be set to increment,
decrement, or neither after a memory access. Bit 1 and bit 0
set the operating mode: Standard as shown in Table 5a on
page 12, or Enhanced as shown in Table 5b on page 12. The
device will reset to the Standard mode, and follow the
operating responses of the original MU9C1480 in Table 5a.
When operating in Enhanced mode, it is not necessary to
unlock the daisy chain with a NOP instruction before
command or data writes after a non-matching compare, as
required in Standard mode.
If the Match Flag is disabled through bit 14 and bit 13, the
internal match condition, /MA(int), used to determine a
daisy-chained device’s response is forced HIGH as shown
in Tables 5a and 5b on page 12, so that Case 6 is not
possible, effectively removing the device from the daisy
chain. With the Match Flag disabled, /MF=/MI and
operations directed to Highest-Priority Match locations are
ignored. Normal operation of the device is with the /MF
enabled. The Match Flag Enable field has no effect on the
/MA or /MM output pins or Status Register bits. These
bits always reflect the true state of the device.
Segment Control Register (SC)
The Segment Control register, as shown in Table 9 on page
22, is accessed using a TCO SC instruction. On read cycles,
D15, D10, D5, and D2 always will read back as 0s. Either the
Foreground or Background Segment Control register will
be active, depending on which register set has been
selected, and only the active Segment Control register will
be written to or read from.
If the Full Flag is disabled through bit 12 and bit 11, the
device behaves as if it is full and ignores instructions to
Next Free address. Also, writes to the Page Address register
are disabled. All other instructions operate normally.
Additionally, with the /FF disabled, /FF=/FI. Normal
operation of the device is with the /FF enabled. The Full
Flag Enable field has no effect on the /FL Status Register
bit. This bit always reflects the true state of the device.
The Segment Control register contains dual independent
incrementing counters with limits, one for data reads and
one for data writes. These counters control which 16-bit
segment of the 64-bit internal resource is accessed during
a particular data cycle on the 16-bit data bus. The actual
destination for data writes and source for data reads (called
the persistent destination and source) are set independently
with SPD and SPS instructions, respectively.
The IEEE Translation control at bit 10 and bit 9 can be used
to enable the translation hardware for writes to 64-bit
resources in the device. When translation is enabled, the
bits are reordered as shown in Figure 2.
D Q 15
D Q8
D Q7
D Q0
D Q 15
D Q8
D Q7
D Q0
Each of the two counters consists of a start limit, an end
limit, and the current count value that points to the segment
to be accessed on the next data cycle. The current count
value can be set to any segment, even if it is outside the
range set by the start and end limits. The counters count
up from the current count value to the end limit and then
jump back to the start limit. If the current count is
greater than the end limit, the current count value will
increment to three, then roll over to zero and continue
incrementing until the end limit is reached; it then jumps
back to the start limit.
If a sequence of data writes or reads is interrupted, the
Segment Control register can be reset to its initial start limit
Figure 2: IEEE 802.3/802.5 Format Mapping
Rev. 3.0 Draft
8
MU9C1480A/L Draft
Next Free Address Register (NF)
The LANCAM automatically stores the address of the first
empty memory location in the Next Free Address register,
which is then used as a memory address pointer for M@NF
operations. The Next Free Address register, shown in Table
10 on page 22, can be read using a TCO NF instruction. By
taking /EC LOW during the TCO NF instruction cycle, only
the device with /FI LOW and /FF HIGH will output the
contents of its Next Free Address register, which gives the
Next Free address in a system of daisy-chained devices.
The Next Free address may be read from a specific device
in the chain by setting the Device Select register to the
value of the desired device’s Page address and leaving
/EC HIGH.
values by using an RSC instruction. After the
LANCAM is reset, both Source and Destination counters
are set to count from Segment 0 to Segment 3 with an initial
value of 0.
Page Address Register (PA)
The Page Address register is loaded using a TCO PA
instruction followed by a Command Write cycle of a user
selected 16-bit value (not FFFFH). The entry in the PA
register is used to give a unique address to the different
devices in a daisy chain. In a daisy chain, the PA value of
each device is loaded using the SFF instruction to advance
to the next device, shown in the “Setting Page Address
Register Values” section on page 15. A software reset
(using the Control register) does not affect the Page
Address register.
The Full Flag daisy chain causes only the device whose /FI
input is LOW and /FF output HIGH to respond to an
instruction using the Next Free address. After a reset, the
Next Free Address register is set to zero.
Device Select Register (DS)
The Device Select register is used to select a specific (target)
device. The TCO DS instruction sets the 16-bit DS register
to the value of the following Command Write cycle. The DS
register can be read. A device is selected when its DS is
equal to its PA value. In a daisy chain, setting DS = FFFFH
will select all devices. However, in this case, the ability to
read information out of the device is restricted as shown in
Tables 5a and 5b on page 12. A software reset (using the
Control register) does not affect the Device Select register.
Status Register
The 32-bit Status register, shown in Table 11 on page 22, is
the default source for Command Read cycles. Bit 31 is the
internal Full flag, which will go LOW if the particular device
has no empty memory locations. Bit 30 is the internal
Multiple Match flag, which will go LOW if a Multiple match
was detected. Bit 29 and Bit 28 are the Skip and Empty
Validity bits, which reflect the validity of the last memory
location read. After a reset, the Skip and Empty bits will
read 11 until a read or move from memory has occurred.
The rest of the Status register down to bit 1 contains the
Page address of the device and the address of the HighestPriority match. After a reset or a no-match condition, the
match address bits will be all 1s. Bit 0 is the internal Match
flag, which will go LOW if a match was found in this
particular device.
Address Register (AR)
The Address register points to the CAM memory location
to be operated upon when M@[AR] or M@aaaH is part of
the instruction. It can be loaded directly by using a TCO
AR instruction or indirectly by using an instruction requiring
an absolute address, such as MOV aaaH,CR,V. After being
loaded, the Address register value will then be used for the
next memory access referencing the Address register. A
reset sets the Address register to zero.
Comparand Register (CR)
The 64-bit Comparand register is the default destination
for data writes and reads, using the Segment Control register
to select which 16-bit segment of the Comparand register is
to be loaded or read out. The persistent source and
destination for data writes and reads can be changed to the
mask registers or memory by SPS and SPD instructions.
During an automatic or forced compare, the Comparand
register is simultaneously compared against the CAM
portion of all memory locations with the correct validity
condition. Automatic compares always compare against
valid memory locations, while forced compares, using CMP
instructions, can compare against memory locations tagged
with any specific validity condition.
Control Register bits CT3 and CT2 set the Address register
to automatically increment or decrement (or not change)
during sequences of Command or Data cycles. The Address
register will change after executing an instruction that
includes M@[AR] or M@aaaH, or after a data access to
the end limit segment (as set in the Segment Control
register) when the persistent source or destination is
M@[AR] or M@aaaH.
Either the Foreground or Background Address register will
be active, depending on which register set has been
selected, and only the active Address register will be written
to or read from.
9
Rev. 3.0 Draft
MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
Cycle Type /E
Cmd Write L
/CM /W
L
L
Cmd Read
L
L
H
Data Write
L
H
L
Data Read
L
H
H
H
X
X
I/O Status SPS SPD TCO Operation
Notes
IN
Load Instruction decoder
1
IN
2,3
ü Load Address register
3
IN
ü Load Control register
3
IN
Load
Page
Address
register
ü
3
IN
Load
Segment
Control
register
ü
IN
Load
Device
Select
register
3
ü
IN
Deselected
10
OUT
3
ü Read Next Free Address register
3
OUT
ü Read Address register
4
OUT
Read Status Register bits 15–0
5
OUT
Read Status Register bits 31–16
OUT
Read
Control
register
3
ü
OUT
Read
Page
Address
register
3
ü
OUT
Read
Segment
Control
register
3
ü
3
OUT
Read
Device
Select
register
ü
OUT
ü Read Current Persistent Source or Destination 3,11
10
HIGH-Z
Deselected
IN
Load Comparand register
6,9
ü
IN
Load Mask Register 1
7,9
ü
IN
Load Mask Register 2
7,9
ü
7,9
IN
Write Memory Array at address
ü
7,9
IN
Write Memory Array at Next Free address
ü
7,9
IN
Write Memory Array at Highest-Priority match
ü
IN
Deselected
10
OUT
Read Comparand register
6, 9
ü
OUT
Read Mask Register 1
8, 9
ü
8, 9
OUT
Read Mask Register 2
ü
8, 9
OUT
Read Memory Array at address
ü
OUT
Read Memory Array at Highest-Priority match
7, 8
ü
HIGH-Z
Deselected
10
HIGH-Z
Deselected
Notes:
1. Default Command Write cycle destination (does not require a TCO instruction).
2. Default Command Write cycle destination (no TCO instruction required) if Address Field flag was set in bit 11 of the
instruction loaded in the previous cycle.
3. Loaded or read on the Command Write or Read cycle immediately following a TCO instruction. Active for one Command
Write or Read cycle only. NFA register cannot be loaded this way.
4. Default Command Read cycle source (does not require a TCO instruction).
5. Default Command Read cycle source (does not require a TCO instruction) if the previous cycle was a Command Read of
Status Register Bits 15–0. If next cycle is not a Command Read cycle, any subsequent Command Read cycle will access the
Status Register Bits 15–0.
6. Default persistent source and destination on power-up and after Reset. If other resources were sources or destinations,
SPD CR or SPS CR restores the Comparand register as the destination or source.
7. Selected by executing a Select Persistent Destination instruction.
8. Selected by executing a Select Persistent Source instruction.
9. Access may require multiple 16-bit Read or Write cycles. The Segment Control register is used to control the selection of the
desired 16-bit segment(s) by establishing the Segment counters’ start and end limits and count values.
10. Device is deselected if Device Select register setting does not equal Page Address register setting, unless the Device Select
Register is set to FFFFH, which allows only write access to the device. (Writes to the Device Select register are always
active.) Device may also be deselected under locked daisy chain conditions as shown in Tables 5a and 5b on page 12.
11. A Command Read cycle after a TCO PS or TCO PD reads back the Instruction decoder bits that were last set to select a
persistent source or destination. The TCO PS instruction will also read back the Device ID.
Table 3: Input/Output Operations
Rev. 3.0 Draft
10
MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
CAM Status
Validity bits at all memory locations
Match and Full Flag outputs
IEEE 802.3–802.5 Input Translation
CAM/RAM Partitioning
Comparison Masking
Address register auto-increment or auto-decrement
Source and Destination Segment counters count ranges
Address register and Next Free Address register
Page Address and Device Select registers
Control register after reset (including CT15)
Persistent Destination for Command writes
Persistent Source for Command reads
Persistent Source and Destination for Data reads and writes
Operating Mode
Configuration Register set
/RESET Condition
Skip = 0, Empty = 1 (empty)
Enabled
Not translated
64 bits CAM, 0 bits RAM
Disabled
Disabled
00B to 11B; loaded with 00B
Contain all 0s
Contain all 0s (no change on software reset)
Contains 0008H
Instruction decoder
Status register
Comparand register
Standard
Foreground
Table 4: Device Control State After Reset
THE MEMORY ARRAY
The Comparand register may be shifted one bit at a time to
the right or left by issuing a Shift Right or Shift Left
instruction, with the right and left limits for the wrap-around
determined by the CAM/RAM partitioning set in the Control
register. During shift rights, bits shifted off the LSB of the
CAM partition will reappear at the MSB of the CAM
partition. Likewise, bits shifted off the MSB of the CAM
partition will reappear at the LSB during shift lefts.
Memory Organization
The Memory array is organized into 64-bit words with each
word having an additional two validity bits (Skip and
Empty). By default, all words are configured to be 64 CAM
cells. However, bits 8–6 of the Control register can divide
each word into a CAM field and a RAM field. The RAM
field can be assigned to the least-significant or mostsignificant portion of each entry. The CAM/RAM
partitioning is allowed on 16-bit boundaries, permitting
selection of the configuration shown in Table 8 on page 21,
bits 8–6 (e.g., “001” sets the 48 MSBs to CAM and the 16
LSBs to RAM). Memory Array bits designated as RAM
can be used to store and retrieve data associated with the
CAM content at the same memory location.
Mask Registers (MR1, MR2)
The mask registers can be used in two different ways: either
to mask compares or to mask data writes and moves. Either
mask register can be selected in the Control register to mask
every compare, or selected by instructions to participate in
data writes or moves to and from Memory. If a bit in the
selected mask register is set to a 0, the corresponding bit in
the Comparand register will enter into a masked compare
operation. If a Mask bit is a 1, the corresponding bit in the
Comparand register will not enter into a masked compare
operation. Bits set to 0 in the mask register cause
corresponding bits in the destination register or memory
location to be updated when masking data writes or moves,
while a bit set to 1 will prevent that bit in the destination from
being changed.
Memory Access
There are two general ways to get data into and out of the
Memory array: directly or by moving the data by means of
the Comparand or mask registers.
The first way, through direct reads or writes, is set up by
issuing a Set Persistent Destination (SPD) or Set Persistent
Source (SPS) command. The addresses for the direct access
can be supplied directly; supplied from the Address
register, supplied from the Next Free Address register, or
supplied as the Highest-Priority Match address.
Additionally, all the direct writes can be masked by either
mask register.
Either the Foreground or Background MR1 can be set active,
but after a reset, the Foreground MR1 is active by default.
MR2 incorporates a sliding mask, where the data can be
replicated one bit at a time to the right or left with no wraparound by issuing a Shift Right or Shift Left instruction. The
right and left limits are determined by the CAM/RAM
partitioning set in the Control register. For a Shift Right the
upper limit bit is replicated to the next lower bit, while for a
Shift Left the lower limit bit is replicated to the next higher bit.
The second way is to move data by means of the Comparand
or mask registers. This is accomplished by issuing Data
11
Rev. 3.0 Draft
MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
COMPARE OPERATIONS
Move commands (MOV). Moves using the Comparand
register can also be masked by either of the mask registers.
During a Compare operation, the data in the Comparand
register is compared to all locations in the Memory array
simultaneously. Any mask register used during compares
must be selected beforehand in the Control register. There
are two ways compares are initiated: Automatic compare
and Forced compare.
I/O CYCLES
The LANCAM supports four basic I/O cycles: Data Read,
Data Write, Command Read, and Command Write. The states
of the /W and /CM control inputs determine the type of
cycle. These signals are registered at the beginning of a
cycle by the falling edge of /E. Table 2 on page 2 shows
how the /W and /CM signals select the cycle type.
Automatic compares perform a compare of the contents of the
Comparand register against Memory locations that are tagged
as “Valid,” and occur whenever the following happens:
During Read cycles, the DQ15–0 outputs are enabled after
/E goes LOW. During Write cycles, the data or command
to be written is captured from DQ15–0 at the beginning of
the cycle by the falling edge of /E. Figures 3 and 4 on page
13, show Read and Write cycles respectively. Figure 5 on
page 13, shows typical cycle-to-cycle timing with the Match
flag valid at the end of the Comparand Write. Data writes
and reads to the comparand, mask registers, or memory
occur in one to four 16-bit cycles, depending on the settings
in the Segment Control register. The Compare operation
automatically occurs during Data writes to the Comparand
or mask registers when the destination segment counter
reaches the end count set in the Segment Control register.
If there was a match, the second cycle reads status or
associated data, depending on the state of /CM. For
cascaded devices, /EC needs to be LOW at the start of the
cycle prior to any cycle that requires a locked daisy chain,
such as a Status register or associated data read after a
match. If there is no match in Standard mode, the output
buffers stay High-Z, and the daisy chain must be unlocked
by taking /EC HIGH during a NOP or other non-functioning
cycle, as indicated in Table 5a. Figure 6 on page 14 shows
how the internal /EC timing holds the daisy chain locking
effect over into the next cycle. In Enhanced mode, this
NOP is not needed before data or command writes following
a non-matching compare, as indicated by Table 5b. A
single-chip system does not require daisy-chained match
flag operation, hence /EC could be tied HIGH and the
/MA pin or flag in the Status register used instead of
/MF, allowing access to the device regardless of the
match condition.
Ø The Destination Segment counter in the Segment
Ø
Forced compares are initiated by CMP instructions
using one of the four validity conditions: V, R, S, and E. The
forced compare against “Empty” locations automatically
masks all 64 bits of data to find all locations with the validity
bits set to “Empty,” while the other forced compares are
only masked as selected in the Control register.
VERTICAL CASCADING
LANCAMs can be vertically cascaded to increase system
depth. Through the use of flag daisy-chaining, multiple
devices will respond as an integrated system. The flag daisy
chain allows all commands to be issued globally, with a
response only in the device containing the
Highest-Priority Matching or Next Free location. When
connected in a daisy chain, the last device’s Full flag and
Match flag accurately report the condition for the whole
string. A system in which LANCAMs are vertically
cascaded using daisy-chaining of the flags is shown in
Figure 1a on page 7.
To operate the daisy chain, the Device Select registers are
set to FFFFH to enable all devices to execute Command
Write and Data Write cycles. In normal operation, read
cycles are enabled from the device with the Highest-Priority
match by locking the daisy chain (see the “Locked Daisy
Chain” section). An individual device in the chain may be
targeted for a read or write operation by temporarily setting
the Device Select registers to the Page address of the target
device. Setting the Device Select registers back to FFFFH
restores the operation of the entire daisy chain.
The minimum timings for the /E control signal are given in
the Switching Characteristics section on page 25. Note that
at minimum timings the /E signal is non-symmetrical and
that different cycle types have different timing requirements,
as given in Table 7 on page 21.
Rev. 3.0 Draft
Control register reaches its end limit during writes to
the Comparand or mask registers.
After a command write of a TCO CT is executed (except
for a software reset), so that a compare is executed
with the new settings of the Control register.
12
MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
Case
Internal
/EC(int)
Internal
/MA (int)
External
/MI
Device Select
Register
1
1
X
X
DS=FFFFH
Command Data Write
Write1
YES3
YES4
3
4
Command
Read
Data Read
NO
NO
2
1
X
X
DS=PA
YES
YES
YES
YES
3
1
X
X
DS≠FFFFH and
NO
NO
NO
NO
4
0
X
0
X
NO
NO
NO5
NO
5
0
1
1
X
NO
NO
NO5
NO
DS≠PA
6
2
0
0
1
3
X
YES
4
YES
5
YES
YES
Command
Read
Data Read
Table 5a: Standard Mode Device Select Response
Case
Internal
/EC(int)
Internal
/MA (int)
External
/MI
Device select
Register
1
1
X
X
DS = FFFFH
YES3
YES4
NO
NO
2
1
X
X
DS = PA
YES3
YES4
YES
YES
3
1
X
X
DS ≠ FFFFH
and DS ≠ PA
NO
NO
NO
NO
4
0
0
0
X
YES3,6
YES4,7
NO5
NO
X
3,6
4,7
NO5
NO
5
6
2
0
0
1
0
X
1
Command Data Write
Write1
YES
3
X
YES
YES
4
YES
5
YES
YES
Table 5b: Enhanced Mode Device Select Response
NOTES:
1. Exceptions are:
A) A write to the Device Select register is always active in all devices;
B) A write to the Page Address register is active in the device with /FI LOW and /FF HIGH; and
C) The Set Full Flag (SFF) instruction is active in the device with /FI LOW and /FF HIGH.
2. If /MF is disabled in the Control register, Internal /MA is forced HIGH preventing a Case 6 response.
3. This is NO for a MOV instruction involving Memory at Next Free address if /FI is HIGH or the device is full.
4. This is NO if the Persistent Destination is Memory at Next Free address and /FI is HIGH or the device is full.
5. For a Command read following a TCO NF instruction, this is YES if the device contains the first empty location in a daisy chain
(i.e., /FI LOW and /FF HIGH) and NO if it does not.
6. This is NO for a MOV or VBC instruction involving Memory at Highest-Priority match.
7. This is NO if the Persistent Destination is Memory at Highest-Priority match.
Match Flag Cascading
The Match Flag daisy chain cascading is used for three
purposes: first, to allow operations on Highest-Priority
Match addresses to be issued globally over the whole
string; second, to provide a system wide match flag; third,
to lock out all devices except the one with the
Highest-Priority match for instructions such as Status reads
after a match. The Match flag logic causes only the
highest-priority device to operate on its Highest-Priority
Match location while devices with lower-priority matches
ignore Highest-Priority Match operations. The lock-out
feature is enabled by the match flag cascading and the use
of the /EC control signal, as shown in Tables 5a and 5b.
/E
/EC
/EC (INT )
/MF
Figure 6: /EC (Int) Timing Diagram
13
Rev. 3.0 Draft
MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
/E
/W
/CM
/EC
DQ 1 5 -0
DA TA O U T
Figure 3: Read Cycle
/E
/W
/C M
/EC
D Q 15– 0
Figure 4: Write Cycle
S TA T U S R EAD
C YC L E
CO M P AR AN D W RI T E
C YC L E
AS S O C IAT E D D AT A
R EA D C Y CL E
/E
/CM
/W
DQ 1 5 – 0
DA T A
DA T A
DA T A
/E C
/M F
M AT CH FL A G V A L I D
/M A, /M M
/M A A ND / M M FL AG S UP D AT ED
Figure 5: Cycle to Cycle Timing Example
Locked Daisy Chain
In a locked daisy chain, the highest-priority device is the
one with /MI HIGH and /MF LOW. In Standard mode, only
this device will respond to command and data reads and
writes, until the daisy chain has been unlocked by taking
/EC HIGH. This allows reading the associated data field
from only the Highest-Priority Match location anywhere in
a string of devices, or the Match address from the Status
register of the device with the match. It also permits
updating the entry stored at the Highest-Priority Match
location. In Enhanced mode, devices are enabled to respond
to some command and data writes, as noted in Table 5b,
but not command and data reads.
The ripple delay of the flags when connected in a daisy
chain requires the extension of the /E HIGH time until the
logic in all devices has settled out. In a string of “n” devices,
the /E HIGH time should be greater than
tEHMFV + (n-2)· tMIVMFV
If the last device’s Match flag is required by external logic
or a state machine before the start of the next CAM cycle,
one additional tMIVMFV should be added to the
/E HIGH time along with the setup time and delays for the
external logic.
Rev. 3.0 Draft
14
MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
only in the device with /FI LOW and /FF HIGH. Enhanced
mode speeds up system performance by eliminating the
need to unlock the daisy chain before Command or Data
Write cycles.
Table 5a (Standard mode) and Table 5b (Enhanced mode)
show when a device will respond to reads or writes and
when it will not, based on the state of /EC(int), the internal
match condition, and other control inputs. /EC is latched
by the falling edge of /E. /EC(int) is registered from the
latched /EC signal off the rising edge of /E, so it controls
what happens in the next cycle, as shown in Figure 6. When
/EC is first taken LOW in a string of LANCAM devices
(and assuming the Device Select registers are set to FFFFH),
all devices will respond to that command write or data write.
Full Flag Cascading
The Full Flag daisy chain cascading is used for three
purposes: first, to allow instructions that address Next Free
locations to operate globally; second, to provide a system
wide Full flag; third, to allow the loading of the Page
Address registers during initialization using the SFF
instruction. The full flag logic causes only the device
containing the first empty location to respond to Next Free
instructions such as “MOV NF,CR,V”, which will move the
contents of the Comparand register to the first empty
location in a string of devices and set that location Valid,
so it will be available for the next automatic compare. With
devices connected as in Figure 1a on page 7, the /FF output
of the last device in a string provides a full indication for
the entire string.
From then on the daisy chain will remain locked in each
subsequent cycle as long as /EC is held LOW on the falling
edge of /E in the current cycle. When the daisy chain is
locked in Standard mode, only the Highest-Priority Match
device will respond (See Case 6 of Table 5a). If, for example,
all of the CAM memory locations were empty, there would
be no match, and /MF would stay HIGH. Since none of the
devices could then be the Highest-Priority Match device,
none will respond to reads or writes until the daisy chain is
unlocked by taking /EC HIGH and asserting /E for a cycle.
IEEE 802.3/802.5 Format Mapping
To support the symmetrical mapping between the address
formats of IEEE 802.3 and IEEE 802.5, the LANCAM provides
a bit translation facility. Formally expressed, the nth input
bit, D(n), maps to the xth output bit, Q(x), through the
following expressions:
If there is a match between the data in the Comparand
register and one or more locations in memory, then only the
Highest-Priority Match device will respond to any cycle,
such as an associated data or Status Register read. If there
is not a match, then a NOP with /EC HIGH needs to be
inserted before issuing any new instructions, such as Write
to Next Free Address instruction to learn the data. Since
Next Free operations are controlled by the /FI–/FF daisy
chain, only the device with the first empty location will
respond. If an instruction is used to unlock the daisy chain
it will work only on the Highest-Priority Match device, if
one exists. If none exists, the instruction will have no effect
except to unlock the daisy chain. To read the Status registers
of specific devices when there is no match requires the use
of the TCO DS command to set DS=PA of each device.
Single chip systems can tie /EC HIGH and read the Status
register or the /MA and /MM pins to monitor match
conditions, as the daisy chain lock-out feature is not needed
in this configuration. This removes the need to insert a
NOP in the case of a no-match.
D(n) = Q(7–n) for 0 < n < 7,
D(n) = Q(23–n) for 8 < n < 15
Setting Control Register bit 10 and bit 9 selects whether to
persistently translate, or persistently not to translate, the
data written onto the 64-bit internal bus. The default
condition after a Reset command is not to translate the
incoming data. Figure 2 on page 8 shows the bit mapping
between the two formats.
INITIALIZING THE LANCAM
Initialization of the LANCAM is required to configure the
various registers on the device. Since a Control register
reset establishes the operating conditions shown in Table
4 on page 10, restoration of operating conditions better
suited for the application may be required after a reset,
whether using the Control Register reset, or the /RESET
pin. When the device powers up, the memory and registers
are in an unknown state, so the /RESET pin must be asserted
to place the device in a known state.
When the Control register is set to Enhanced mode, you
can continue to write data to the Comparand register or
issue a Move to Next Free Address instruction without
first having to issue a NOP with /EC HIGH to unlock the
daisy chain after a Compare cycle with no match, as indicated
in cases 4 and 5 of Table 5b on page 12. In Enhanced mode,
data write cycles as well as command write cycles are
enabled in all devices even when /EC is LOW. Exceptions
are data writes, moves, or VBC instructions involving HM,
which occur only in the device with the highest match; and
data writes or move instructions involving NF, which occur
Setting Page Address Register Values
In a vertically cascaded system, the user must set the
individual Page Address registers to unique values by
using the Page Address initialization mechanism. Each Page
15
Rev. 3.0 Draft
MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
Vertically Cascaded System Initialization
Table 6 shows an example of code that initializes a
daisy-chained string of LANCAM devices. The
initialization example shows how to set the Page Address
registers of each of the devices in the chain through the
use of the Set Full Flag instruction, and how the Control
registers and Segment counters of all the LANCAM devices
are set for a typical application. Each Page Address register
must contain a unique value (not FFFFH) to prevent bus
contention.
Address register must contain a unique value to prevent
bus contention. This process allows individual device
selection. The Page Address register initialization works
as follows: Writes to Page Address registers are only active
for devices with /FI LOW and /FF HIGH. At initialization,
all devices are empty, thus the top device in the string will
respond to a TCO PA instruction, and load its PA register.
To advance to the next device in the string, a Set Full Flag
(SFF) instruction is used, which is active only for the device
with /FI LOW and /FF HIGH. The SFF instruction changes
the first device’s /FF to LOW, although the device really is
empty, which allows the next device in the string to respond
to the TCO PA instruction and load its PA register. The
initialization proceeds through the chain in a similar manner
filling all the PA registers in turn. Each device must have a
unique Page Address value stored in its PA register, or
contention will result. After all the PA registers are filled,
the entire string is reset through the Control register, which
does not change the values stored in the individual PA
registers. After the reset, the Device Select registers usually
are set to FFFFH to enable operation in Case 1 of Table 5a
on page 12. The Control registers and the Segment Control
registers are then set to their normal operating values for
the application.
Cycle Type
Control bus
Op-Code
on DQ Bus
/E
/CM
/W
/EC
Command read
Command write
Command write
Commandwrite
Command write
Command write
Command write
Command write
TCO DS
FFFFH
TCO CT
0000H
TCO PA
nnnnH
SFF
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Command write
Commandwrite
Command write
Command write
Command write
Command write
TCO CT
0000H
TCO CT
8040H
TCO SC
3808H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
Command write
SPS M@HM
L
L
L
H
For typical daisy chain operation, data is loaded into the
Comparand registers of all the devices in a string
simultaneously by setting DS=FFFFH. Since reading is
prohibited when DS=FFFFH (except for the device with a
match), for a diagnostic operation you need to select a
specific device by setting DS=PA for the desired device to
be able to read from it. Refer to Tables 5a and 5b on page 12
for preconditions for reading and writing.
Initialization for a single LANCAM is similar. The Device
Select register in this case is usually set to equal the Page
Address register for normal operations. Also, the dedicated
/MA flag output can be used instead of /MF, allowing /EC
to be tied HIGH.
Comments
Clear power-up anomalies.
Target Device Select register to disable local device selection.
Disable Device Select feature.
Target Control register for reset.
Causes Reset.
Target Page Address register to set page for cascaded operation.
Page Address value.
Set Full flag; allows access to next device (repeat previous
two cycles plus this one for each device in chain.
Target Control register for reset of Full flags, but not Page address.
Causes Reset.
Target Control register for initial values.
Control register value.
Target Segment Count Control register
Set both Segment counters to write to Segment 1, 2, and 3, and
read from Segment 0.
Set Data reads from Segment 0 of the Highest-Priority match.
Notes
1
2
2
2,3
1
1
4
4
4
Notes:
1. Toggling the /RESET pin generates the same effect as this reset of the Control register, but good programming
practice dictates a software reset for initialization to account for all possible prior conditions.
2. This instruction may be omitted for a single LANCAM application.
3. The last SFF will cause the /FF pin in the last chip in a daisy chain to go LOW. In a daisy chain, DS needs to be set equal to PA
to read out a particular chip prior to a match condition.
4. A typical LANCAM control environment: Enable match flag; Enable full flag; 48 CAM bits, 16 RAM bits; Disable comparison
masking; and Enable address increment. See Table 8 on page 21 for Control Register bit assignments.
Table 6: Example Initialization Routine
Rev. 3.0 Draft
16
MU9C1480A/L Draft
INSTRUCTION SET DESCRIPTIONS*
Instruction: Select Persistent Source (SPS)
Binary Op-Code: 0000 f000 0000 0sss
f
Address Field flag†
sss
Selected source
This instruction selects a persistent source for data reads,
until another SPS instruction changes it or a reset occurs.
The default source after reset for Data Read cycles is the
Comparand register. Setting the persistent source to
M@aaaH loads the Address register with “aaaH” and the
first access to that persistent source will be at aaaH, after
which the AR value increments or decrements as set in the
Control register. The SPS M@[AR] instruction does the
same except the current Address Register value is used.
Subsequent Command Read or Write cycles revert to
reading the Status register and writing to the Instruction
decoder. All registers but the NF, PS, and PD can be written
to, and all can be read from. The Status register is only
available through non-TCO Command Read cycles.
Reading the PS register also outputs the Device ID on bits
15–4 as shown in Table 12 on page 22.
Instruction: Data Move (MOV)
Binary Op-Code: 0000 f011 mmdd dsss or
0000 f011 mmdd dvss
f
Address Field flag†
mm
Mask Register select
ddd
Destination of data
sss
Source of data
v
Validity setting if destination is a
Memory location
The MOV instruction performs a 64-bit move of the data in
the selected source to the selected destination. If the
source or destination is aaaH, the Address register is set
to “aaaH.” For MOV instructions to or from aaaH or [AR],
the Address register will increment or decrement from that
value after the move completes, as set in the Control
register. Data transfers between the Memory array and the
Comparand register may be masked by either Mask
Register 1 or Mask Register 2, in which case, only those
bits in the destination that correspond to bits in the selected
mask register set to 0 will be changed. A Memory location
used as a destination for a MOV instruction may be set to
Valid or left unchanged. If the source and destination are
the same register, no net change occurs
(a NOP).
Instruction: Select Persistent Destination (SPD)
Binary Op-Code: 0000 f001 mmdd dvvv
f
Address Field flag†
mm
Mask Register select
ddd
Selected destination
vvv
Validity setting for Memory Location
destinations
This instruction selects a persistent destination for data
writes, which remains until another SPD instruction changes
it or a reset occurs. The default destination for Data Write
cycles is the Comparand register after a reset. When the
destination is the Comparand register or the Memory array,
the data written may be masked by either Mask Register 1
or Mask Register 2, so that only destination bits
corresponding to bits in the mask register set to 0 will be
modified. An automatic compare will occur after writing the
last segment of the Comparand or mask registers, but not
after writing to Memory. Setting the persistent destination
to M@aaaH loads the Address register with “aaaH,” and
the first access to that persistent destination will be at aaaH,
after which the AR value increments or decrements as set in
the Control register. The SPD M@[AR] instruction does
the same except the current Address Register value is used.
Instruction: Validity Bit Control (VBC)
Binary Op-Code: 0000 f100 00dd dvvv
f
Address Field flag†
ddd
Destination of data
vvv
Validity setting for Memory location
The VBC instruction sets the Validity bits at the selected
memory locations to the selected state. This feature can be
used to find all valid entries by using a repetitive sequence
of CMP V through a mask of all 1s followed by a VBC HM, S.
If the VBC target is aaaH, the Address register is set to
“aaaH.” For VBC instructions to or from aaaH or [AR], the
Address register will increment or decrement from that value
after the operation completes, as set in the Control register.
Instruction: Temporary Command Override (TCO)
Binary Op-Code: 0000 0010 00dd d000
ddd
Register selected as source or
destination for only the next
Command Read or Write cycle
The TCO instruction selects a register as the source or
destination for only the next Command Read or Write cycle,
so a value can be loaded or read out of the register.
17
Rev. 3.0 Draft
MU9C1480A/L Draft
INSTRUCTION SET DESCRIPTIONS* Continued
Instruction: Compare (CMP)
Binary Op-Code: 0000 0101 0000 0vvv
vvv
Validity condition
A CMP V, S, or R instruction forces a Comparison of Valid,
Skipped, or Random entries against the Comparand register
through a mask register, if one is selected. During a CMP E
instruction, the compare is only done on the Validity bits
and all data bits are automatically masked.
sliding mask, where for a Shift Right instruction bit 1 is moved
to bit 0, while bit 0 “falls off the end,” and bit 63 is replicated to
bit 62. For a Shift Mask Left instruction, bit 0 is replicated to bit
1, bit 62 is moved to bit 63, and bit 63 “falls off the end.” With
shorter width CAM fields, the bit limits on the right or left
move to match the width of CAM field.
Instruction: Set Full Flag (SFF)
Binary Op-Code: 0000 0111 0000 0000
The SFF instruction is a special instruction used to force the
Full flag LOW to permit setting the Page Address register in
vertically cascaded systems.
Instruction: Special Instructions
Binary Op-Code: 0000 0110 00dd drrr
ddd
Target resource
rrr
Operation
These instructions are a special set for the LANCAM to
accommodate the added features over the MU9C1480. Two
alternate sets of configuration registers can be selected by
using the Select Foreground and Select Background Registers
instructions. These registers are the Control, Segment Control,
Address, Mask Register 1, and the PS and PD registers. An
RSC instruction resets the Segment Control register count
values for both the Destination and Source counters to the
original Start limits. The Shift instructions shift the designated
register one bit right or left. The right and left limits for shifting
are determined by the CAM/RAM partitioning set in the
Control register. The Comparand register is a barrel-shifter,
and for the example of a device set to 64 bits of CAM executing
a Shift Comparand Right instruction, bit 0 is moved to bit 63,
bit 1 is moved to bit 0, and bit 63 is moved to bit 62. For a Shift
Comparand Left instruction, bit 63 is moved to bit 0, bit 0 is
moved to bit 1, and bit 62 is moved to bit 63. MR2 acts as a
Rev. 3.0 Draft
Instruction: No Operation (NOP)
Binary Op-Code: 0000 0011 0000 0000
The NOP (No-OP) belongs to the MOV instructions, where a
register is moved to itself. No change occurs within the device.
This instruction is useful in unlocking the daisy chain in
Standard mode.
Notes:
* Instruction cycle lengths given in Table 7 on page 21.
† If f=1, the instruction requires an absolute address to be supplied
on the following cycle as a Command write. The value supplied on
the second cycle of the instruction will update the address register.
After operations involving M@[AR] or M@aaaH, the Address
register will increment or decrement depending on the setting in
the Control register.
18
MU9C1480A/L Draft
INSTRUCTION SET SUMMARY
Instruction: Select Persistent Destination Cont.
Operation
Mnemonic
Op-Code
MNEMONIC FORMAT
INS dst,src[msk],val
INS: Instruction mnemonic
dst: Destination of the data
src: Source of the data
msk: Mask register used
val: Validity condition set at the location written
Instruction: Select Persistent Source
Operation
Mnemonic Op-Code
Comparand Register
Mask Register 1
Mask Register 2
Memory Array at Addr. Reg.
Memory Array at Address
Mem. at Highest-Prio. Match
SPS CR
SPS MR1
SPS MR2
SPS M@[AR]
SPS M@aaaH
SPS M@HM
0000H
0001H
0002H
0004H
0804H
0005H
Instruction: Select Persistent Destination
Operation
Mnemonic
Op-Code
Comparand Register
Masked by MR1
Masked by MR2
SPD CR
SPD CR[MR1]
SPD CR[MR2]
0100H
0140H
0180H
Mask Register 1
Mask Register 2
Mem. at Addr. Reg. set Valid
Masked by MR1
Masked by MR2
SPD MR1
SPD MR2
SPD M@[AR],V
SPD M@[AR][MR1],V
SPD M@[AR][MR2],V
0108H
0110H
0124H
0164H
01A4H
Mem. at Addr. Reg. set Empty
Masked by MR1
Masked by MR2
SPD M@[AR],E
0125H
SPD M@[AR][MR1],E 0165H
SPD M@[AR][MR2],E 01A5H
Mem. at Addr. Reg. set Skip
Masked by MR1
Masked by MR2
SPD M@[AR],S
0126H
SPD M@[AR][MR1],S 0166H
SPD M@[AR][MR2],S 01A6H
SPD M@aaaH,V
0924H
SPD M@aaaH[MR1],V 0964H
SPD M@aaaH[MR2],V09A4H
Memory at Addr. set Empty
Masked by MR1
Masked by MR2
SPD M@aaaH,E
0925H
SPD M@aaaH[MR1],E 0965H
SPD M@aaaH[MR2],E 09A5H
Memory at Address set Skip
Masked by MR1
Masked by MR2
SPD M@aaaH,S
0926H
SPD M@aaaH[MR1],S 0966H
SPD M@aaaH[MR2],S 09A6H
Mem. at Address set Random
Masked by MR1
Masked by MR2
SPD M@aaaH,R
0927H
SPD M@aaaH[MR1],R 0967H
SPD M@aaaH[MR2],R 09A7H
Mem. at Highest-Prio. Match, Valid SPD M@HM,V
Masked by MR1
SPD M@HM[MR1],V
Masked by MR2
SPD M@HM[MR2],V
012DH
016DH
01ADH
Mem. at Highest-Prio. Match, Skip SPD M@HM,S
Masked by MR1
SPD M@HM[MR1],S
Masked by MR2
SPD M@HM[MR2],S
012EH
016EH
01AEH
Mem. at High.-Prio. Match, Random SPD M@HM,R
Masked by MR1
SPD M@HM[MR1],R
Masked by MR2
SPD M@HM[MR2],R
012FH
016FH
01AFH
Mem. at Next Free Addr., Valid SPD M@NF,V
Masked by MR1
SPD M@NF[MR1],V
Masked by MR2
SPD M@NF[MR2],V
0134H
0174H
01B4H
Mem. at Next Free Addr., Empty SPD M@NF,E
Masked by MR1
SPD M@NF[MR1],E
Masked by MR2
SPD M@NF[MR2],E
0135H
0175H
01B5H
Mem. at Next Free Addr., Skip
Masked by MR1
Masked by MR2
SPD M@NF,S
SPD M@NF[MR1],S
SPD M@NF[MR2],S
0136H
0176H
01B6H
Mem. at Next Free Addr., Random SPD M@NF,R
Masked by MR1
SPD M@NF[MR1],R
Masked by MR2
SPD M@NF[MR2],R
0137H
0177H
01B7H
Instruction: Temporary Command Override
Operation
Mnemonic
Op-Code
Mem. at Addr. Reg. set Random SPD M@[AR],R
0127H
Masked by MR1
SPD M@[AR][MR1],R 0167H
Masked by MR2
SPD M@[AR][MR2],R 01A7H
Memory at Address set Valid
Masked by MR1
Masked by MR2
Mem. at Highest-Prio. Match, Emp. SPD M@HM,E
Masked by MR1
SPD M@HM[MR1],E
Masked by MR2
SPD M@HM[MR2],E
Control Register
Page Address Register
Segment Control Register
Read Next Free Address
Address Register
Device Select Register
Read Persistent Source
Read Persistent Destination
TCO CT
TCO PA
TCO SC
TCO NF
TCO AR
TCO DS
TCO PS
TCO PD
Instruction: Data Move
Operation
Mnemonic
Comparand Register from:
No Operation
Mask Register 1
Mask Register 2
Memory at Address Reg.
Masked by MR1
Masked by MR2
NOP
MOV CR,MR1
MOV CR,MR2
MOV CR,[AR]
MOV CR,[AR][MR1]
MOV CR,[AR][MR2]
Memory at Address
Masked by MR1
Masked by MR2
Mask Register 1 from:
Comparand Register
No Operation
Mask Register 2
Memory at Address Reg.
Memory at Address
Mem. at Highest-Prio. Match
012CH
016CH
01ACH
19
0200H
0208H
0210H
0218H
0220H
0228H
0230H
0238H
Op-Code
0300H
0301H
0302H
0304H
0344H
0384H
MOV CR,aaaH
0B04H
MOV CR,aaaH[MR1] 0B44H
MOV CR,aaaH[MR2] 0B84H
MOV MR1,CR
NOP
MOV MR1,MR2
MOV MR1,[AR]
MOV MR1,aaaH
MOV MR1,HM
0308H
0309H
030AH
030CH
0B0CH
030DH
Rev. 3.0 Draft
MU9C1480A/L Draft
INSTRUCTION SET SUMMARY Continued
Instruction: Data Move Continued
Operation
Mnemonic
Op-Code
Mem. at Highest-Prio. Match
Masked by MR1
Masked by MR2
MOV CR,HM
MOV CR,HM[MR1]
MOV CR,HM[MR2]
0305H
0345H
0385H
Mask Register 2 from:
Comparand Register
Mask Register 1
No Operation
Memory at Address Reg.
Memory at Address
Mem. at Highest-Prio. Match
MOV MR2,CR
MOV MR2,MR1
NOP
MOV MR2,[AR]
MOV MR2,aaaH
MOV MR2,HM
0310H
0311H
0312H
0314H
0B14H
0315H
Memory at Address Register, No Change to Validity bits, from:
Comparand Register
MOV [AR],CR
0320H
Masked by MR1
MOV [AR],CR[MR1] 0360H
Masked byMR2
MOV [AR],CR[MR2] 03A0H
Mask Register 1
MOV [AR],MR1
0321H
Mask Register 2
MOV [AR],MR2
0322H
Memory at Address Register, Location set Valid, from:
Comparand Register
MOV [AR],CR,V
0324H
Masked by MR1
MOV [AR],CR[MR1],V 0364H
Masked byMR2
MOV [AR],CR[MR2],V 03A4H
Mask Register 1
MOV [AR],MR1,V
0325H
Mask Register 2
MOV [AR],MR2,V
0326H
Memory at Address, No Change to Validity bits, from:
Comparand Register
MOV aaaH0,CR
Masked by MR1
MOV aaaH,CR[MR1]
Masked byMR2
MOV aaaH,CR[MR2]
Mask Register 1
MOV aaaH,MR1
Mask Register 2
MOV aaaH,MR2
Memory at Highest-Priority Match, No Change to Validity bits,
from:
Comparand Register
MOV HM,CR
0328H
Masked by MR1
MOV HM,CR[MR1]
0368H
Masked byMR2
MOV HM,CR[MR2]
03A8H
Mask Register 1
MOV HM,MR1
0329H
Mask Register 2
MOV HM,MR2
032AH
Memory at Next Free Address,
from:
Comparand Register
Masked byMR1
Masked byMR2
Mask Register 1
Mask Register 2
Rev. 3.0 Draft
from:
032CH
036CH
03ACH
032DH
032EH
No Change to Validity bits,
MOV NF,CR
MOV NF,CR[MR1]
MOV NF,CR[MR2]
MOV NF,MR1
MOV NF,MR2
Memory at Next Free Address,
Comparand Register
Masked by MR1
Masked by MR2
Mask Register 1
Mask Register 2
Op-Code
Location set Valid, from:
MOV NF,CR,V
0334H
MOV NF,CR[MR1],V 0374H
MOV NF,CR[MR2],V 03B4H
MOV NF,MR1,V
0335H
MOV NF,MR2,V
0336H
Instruction: Validity Bit Control
Operation
Mnemonic
Op-Code
Set Validity bits at Address Register
Set Valid
VBC [AR],V
Set Empty
VBC [AR],E
Set Skip
VBC [AR],S
Set Random Access
VBC [AR],R
0424H
0425H
0426H
0427H
Set Validity bits at Address
Set Valid
Set Empty
Set Skip
Set Random Access
0C24H
0C25H
0C26H
0C27H
VBC aaaH,V
VBC aaaH,E
VBC aaaH,S
VBC aaaH,R
Set Validity bits at Highest-Priority Match
Set Valid
VBC HM,V
Set Empty
VBC HM,E
Set Skip
VBC HM,S
Set Random Access
VBC HM,R
0B20H
0B60H
0BA0H
0B21H
0B22H
Memory at Address, Location set Valid, from:
Comparand Register
MOV aaaH,CR,V
0B24H
Masked by MR1
MOV aaaH,CR[MR1],V0B64H
Masked byMR2
MOV aaaH,CR[MR2],V0BA4H
Mask Register 1
MOV aaaH,MR1,V
0B25H
Mask Register 2
MOV aaaH,MR2,V
0B26H
Memory at Highest-Priority Match, Location set Valid,
Comparand Register
MOV HM,CR,V
Masked by MR1
MOV HM,CR[MR1],V
Masked byMR2
MOV HM,CR[MR2],V
Mask Register 1
MOV HM,MR1,V
Mask Register 2
MOV HM,MR2,V
Instruction: Data Move Continued
Operation
Mnemonic
Set Validity bits at All Matching Locations
Set Valid
VBC ALM,V
Set Empty
VBC ALM,E
Set Skip
VBC ALM,S
Set Random Access
VBC ALM,R
Instruction: Compare
Operation
Mnemonic
Compare Valid Locations
Compare Empty Locations
Compare Skipped Locations
Comp. Random Access Locations
CMP V
CMP E
CMP S
CMP R
Instruction: Special Instructions
Operation
Mnemonic
Shift Comparand Right
Shift Comparand Left
Shift Mask Register 2 Right
Shift Mask Register 2 Left
Select Foreground Registers
Select Background Registers
Reset Seg. Cont. Reg. to Initial Val.
SFT CR, R
SFT CR, L
SFT M2, R
SFT M2, L
SFR
SBR
RSC
042CH
042DH
042EH
042FH
043CH
043DH
043EH
043FH
Op-Code
0504H
0505H
0506H
0507H
Op-Code
0600H
0601H
0610H
0611H
0618H
0619H
061AH
Instruction: Miscellaneous Instructions
Operation
Mnemonic
Op-Code
No Operation
Set Full Flag
0330H
0370H
03B0H
0331H
0332H
20
NOP
SFF
0300H
0700H
MU9C1480A/L Draft
INSTRUCTION SET SUMMARY Continued
CYCLE
LENGTH
Short
Medium
Long
CYCLE TYPE
Command write
Data Write
Command Read
MOV reg, reg (except L-70)
TCO reg (except CT)
TCO CT (non-reset, HMA invalid)
SPS, SPD, SFR
SBR, RSC
NOP (except L-70)
SFT (A)
MOV reg, mem
Status register or
MOV reg, reg (L-70)
16-bit register
TCO CT (reset)
VBC (NFA invalid)
SFT (L)
NOP (L-70)
MOV mem, reg
TCO CT (non-reset, HMA valid)
CMP
SFF
VBC (NFA valid)
Data Read
Comparand register
(not last segment)
Mask register
(not last segment)
Memory array
(NFA invalid)
Comparand register
Mask register
Memory array
(NFA valid)
Comparand register
(last segment)
Mask register
(last segment)
Memory array
Note: The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics section under the
tELEH parameter. For two cycle Command Writes (TCO reg or any instruction with “aaaH” as the source or destination), the
first cycle is short, and the second cycle will be the length given.
Table 7: Instruction Cycle Lengths
REGISTER BIT ASSIGNMENTS
15
14
13 12
11
10
9
RST
Match Flag
Full Flag Translation
R
E
S
E
T
=
0
Enable
=00
Disable
= 01
No Change
= 11
Enable
= 00
Disable
= 01
No Change
= 11
Input Not
Translated
= 00
Input
Translated
= 01
No Change
= 11
8
7
6
CAM/RAM Part.
64 CAM/0 RAM = 000
48 CAM/16 RAM = 001
32 CAM/32 RAM = 010
16 CAM/48 RAM = 011
48 RAM/16 CAM = 100
32 RAM/32 CAM = 101
16 RAM/48 CAM = 110
No Change = 111
5
4
3
2
Comp. Mask AR Inc/Dec
None = 00
MR1 = 01
MR2 = 10
No Change
= 11
Increment
= 00
Decrement
= 01
Disable
= 10
No Change
= 11
1
0
Mode
Standard
= 00
Enhanced
= 01
Reserved
= 10
No Change
= 11
Note: D15 reads back as 0.
Table 8: Control Register Bit Assignments
21
Rev. 3.0 Draft
MU9C1480A/L Draft
REGISTER BIT ASSIGNMENTS Continued
15
14
13
12
11
10
9
8
SDL
DCSL
DCEL
SSL
SCSL
Set
Dest.
Seg.
Limits
=0
No
Chng.
=1
Destination
Count
Start
Limit
= 00–11
Destination
Count
End
Limit
= 00–11
Set
Source
Seg.
Limits
=0
No
Chng.
=1
Source
Count
Start
Limit
= 00–11
Note:
7
6
5
SCEL
LDC
Source
Count
End
Limit
= 00–11
Load
Dest.
Seg.
Count
=0
No
Chng.
=1
4
3
2
1
LSC
DSCV
Destination
Seg.
Count
Value
= 00–11
0
SSCV
Load
Src.
Seg.
Count
=0
No
Chng.
=1
Source
Seg.
Count
Value
= 00–11
D15, D10, D5, and D2 read back as 0s.
Table 9: Segment Control Register Bit Assignments
14
15
13
12
11
10
9
8
7
Page Address, PA5–PA0
6
5
4
3
2
1
0
18
17
16
2
1
0
/MA
1
0
Next Free Address, NF9–0
Note: The Next Free Address register is read only, and is accessed by performing a Command Read
cycle immediately following a TCO NF instruction.
Table 10: Next Free Address Register Bit Assignments
31
/FL
30
/MM
29
28
27
Skip Empty
15
14
13
12
Page Address, PA4–PA0
26
25
0
24
23
22
21
20
19
Page Address Bits, PA15-PA5
11
10
9
8
7
6
5
4
3
Match Address, AM9-AM0
Note: The Status register is read only, and is accessed by performing Command Read cycles. On the first
cycle, bits 15–0 will be output, and if a second Command Read cycle is issued immediately after the
first Command Read cycle, bits 31–16 will be output.
Table 11: Status Register Bit Assignments
15
14
13
12
11
10
9
8
7
6
5
4
Device ID = 141H
3
2
PS
Note: The Persistent Source register is read only, and is accessed by performing a Command Read cycle
immediately following a TCO PS instruction.
Table 12: Persistent Source Register Bit Assignments
Rev. 3.0 Draft
22
MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
1480A
1480L
Voltage on all other pins
Temperature under bias
Storage Temperature
DC Output Current
Stresses exceeding those listed under Absolute
Maximum Ratings may include failure. Exposure
to absolute maximum ratings for extended
periods may reduce reliability. Functionality at
or above these conditions is not implied.
-0.5 to 7.0 Volts
-0.5 to 4.6 Volts
-0.5 to VCC +0.5 Volts (-2 Volts for
10 ns, measured at the 50% point)
-55°C to 125°C
-55°C to 125°C
20 mA (per output, one at a time, one
second duration.
All voltages referenced to GND.
OPERATING CONDITIONS (voltages referenced to GND at the device pin)
Symbol Parameter
Min Typical
Max
Units
4.75
5.0
5.25
Volts
3.0
3.3
VCC
Operating Supply Voltage
VIH
VIL
Input Voltage Logic 1
2.0
Input Voltage Logic 0
TA
Ambient Operating
Temperature
1480A
1480L
Commercial
Industrial
3.6
Volts
Volts
-0.5
VCC + 0.5
0.8
0
70
°C
-40
85
°C
Volts
Notes
1, 2
Still Air
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter
ICC
Average Power Supply Current
ICC(SB) Stand-by Power Supply Current
VOH
VOL
IIZ
IOZ
Typical
Max
Units
1480A
50
110
mA
1480L
30
70
mA
1480A
7
mA
1480L
2
mA
Min
Output Voltage Logic “1”
Input Leakage Current
Output Leakage Current
Others
-2
/E = HIGH
IOH = -2.0mA
0.4
Volts
IOL = 4.0mA
+2
µA
/RESET
6
9
15
TEST1,
TEST2
6
10
13
-10
t ELEL = t ELEL (min) ;9
Volts
2.4
Output Voltage Logic “0”
Notes
Kohms
VSS ≤ VIN ≤ V CC
VIN = 0 V
VIN = VCC;10
µA
10
VSS ≤ VOUT ≤ VCC;
DQN = High Impedance
CAPACITANCE
Symbol Parameter
CIN
COUT
Max
Units
Input Capacitance
6
pF
Output Capacitance
7
pF
23
Notes
f = 1 MHz, VIN = 0 V
f = 1 MHz, VOUT = 0 V
Rev. 3.0 Draft
MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
AC TEST CONDITIONS
Input Signal Transitions
Input Signal Rise Time
Input Signal Fall Time
Input Timing Reference Level
Output Timing Reference Level
0.0 Volts to 3.0 Volts
< 3 ns
< 3 ns
1.5 Volts
1.5 Volts
SWITCHING TEST FIGURES
V cc
R1
To D e vi c e
U n d e r Te s t
In p u t
W a ve f o rm
0V
V IL ( MIN)
C1
R2
5 0 % A m p li t u d e
P o in t
10ns
Figure 8: Input Signal Waveform
Figure 7: AC Test Load
SWITCHING TEST FIGURES COMPONENT VALUES
Parameter
VCC
R1
R2
C1(includes jig)
Test Load A
Test Load B
Rev. 3.0 Draft
1480A
5.0
961
510
30
5
24
1480L
3.3
635
702
30
5
Units
Volts
Ohms
Ohms
pF
pF
MU9C1480A/L Draft
SWITCHING CHARACTERISTICS (see Note 3)
·
··
Available
Cycle Time
-70
1480A
1480L
·
··
Consult factory for availability
-90
-12
·
·
·
·
Symbol
tELEL
Parameter (all times in nanoseconds)
Min
1
Chip Enable Compare Cycle Time
70
90
120
2
tELEH
Chip Enable LOW Pulse Width
Short Cycle:
15
25
35
Medium Cycle:
35
50
75
Long Cycle:
55
75
100
No
Max
Min
Max
Min
Max Notes
4
4
3
tEHEL
Chip Enable HIGH Pulse Width
15
15
20
4
tCVEL
tELCX
Control Input to Chip Enable LOW Setup Time
0
0
0
5
Control Input from Chip Enable LOW Hold Time
10
10
15
5
tELQX
tELQV
Chip Enable LOW to Outputs Active
3
3
3
6
tEHQZ
tDVEL
Chip Enable HIGH to Outputs HIGH-Z
Data to Chip Enable LOW Setup Time
0
0
0
tELDX
tFIVEL
Data from Chip Enable LOW Hold Time
10
10
15
Full In Valid to Chip Enable LOW Setup Time
0
0
0
tFIVFFV
tELFFV
Full In Valid to Full Flag Valid
5
7
8
Chip Enable LOW to Full Flag Valid
50
75
90
tMIVEL
tEHMFX
Match in Valid to Chip Enable LOW Setup Time
0
0
0
Chip Enable HIGH to /MF, /MA, /MM Invalid
0
0
0
tMIVMFV
tEHMFV
Match In Valid to /MF Valid, /MA, /MM
5
7
8
Chip Enable HIGH to /MF Valid
16
25
30
tEHMXV
tRLRH
Chip Enable HIGH to /MA and /MM Valid
18
25
30
5
6
7
Chip Enable LOW to Outputs Valid
30
50
52
8
9
10
11
12
13
14
15
16
17
18
19
3
Reset LOW Pulse Width
100
10
75
3
100
15
3
100
70
4,6
85
4,6
20
7
8
Notes:
1. -1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (see Figure 8 on page 24).
2. Common I/O lines are clamped, so that signal transients cannot fall below -0.5 Volts.
3. Over ambient operating temperature range and Vcc(min) to Vcc(max).
4. See Table 7 on page 21.
5. Control signals are /W, /CM, and /EC.
6. With load specified in Figure 7, Test Load A.
7. With load specified in Figure 7, Test Load B.
8. /E must be HIGH during this period to ensure accurate default values in the configuration registers.
9. With output and I/O pins unloaded.
10. TEST1 and/or TEST2 may not be implemented on all versions of these products.
25
Rev. 3.0 Draft
MU9C1480A/L Draft
TIMING DIAGRAMS
READ CYCLE
WRITE CYCLE
2
2
3
3
/E
/E
4
5
4
5
4
5
9
10
/W
/W
4
5
/C M
/CM
4
5
D Q 1 5- 0
/ EC
11
7
8
/F I
12
13
DQ15D0
/ FF
6
COMPARE CYCLE
1
2
3
/E
4
5
4
5
/W
/CM
V AL ID
4
5
/EC
14
/M I
15
16
/M F
17
/M A, /M M
18
Rev. 3.0 Draft
26
MU9C1480A/L Draft
PACKAGE OUTLINE
a
B
F
F
E1in
E in2.7
2.6
Pin 1
a
b
b
F1
E
a
C
2.6E1in
A
D
Dimensions are in inches
44-pin
PLCC
Dim. A
Dim. B
Dim. C
Dim. D
Dim. E
Dim. E1
Dim. F
Dim. F1
Dim. a
.170
.017
.018
.100
.650
.685
.590
.05
3°
.180
TYP
.032
TYP
.656
.630
.695
TYP
He
43°
47°
A2
E
Hd
6°
Dim. b
A1
D
L1
e
L
c
b
Dimensions are in mm.
44-pin
Min
Nom
Max
Dim. A
0.05
0.10
0.015
Dim. A2
1.35
1.40
1.45
Dim. b
0.30
0.35
0.45
Dim. c
0.08
Dim. D
Dim. E
Dim. e
10.00
10.00
0.80
0.20
27
Dim. Hd Dim. He Dim. L1
12.00
12.00
1.00
Dim. L
0.45
0.60
0.75
Rev. 3.0 Draft
MU9C1480A/L Draft
ORDERING INFORMATION
Part Number
MU9C1480A - 70DC
MU9C1480A - 90DC
MU9C1480A - 12DC
MU9C1480L - 70DC
MU9C1480L - 90DC
MU9C1480L - 12DC
MU9C1480A - 70DI
MU9C1480A - 90DI
MU9C1480A - 12DI
MU9C1480L - 70DI
MU9C1480L - 90DI
MU9C1480L - 12DI
MU9C1480L-90TAC
··
··
Cycle Time
70ns
90ns
120ns
70ns
90ns
120ns
70ns
90ns
120ns
70ns
90ns
120ns
90ns
Package
44-PIN PLCC
44-PIN PLCC
44-PIN PLCC
44-PIN PLCC
44-PIN PLCC
44-PIN PLCC
44-PIN PLCC
44-PIN PLCC
44-PIN PLCC
44-PIN PLCC
44-PIN PLCC
44-PIN PLCC
44-PIN TQFP
Temperature
0–70° C
0–70° C
0–70° C
0–70° C
0–70° C
0–70° C
-40–85° C
-40–85° C
-40–85° C
-40–85° C
-40–85° C
-40–85° C
0–70° C
Voltage
5.0 ± 0.25
5.0 ± 0.25
5.0 ± 0.25
3.3 ± 0.3
3.3 ± 0.3
3.3 ± 0.3
5.0 ± 0.25
5.0 ± 0.25
5.0 ± 0.25
3.3 ± 0.3
3.3 ± 0.3
3.3 ± 0.3
3.3 ± 0.3
··Consult factory for availability
MUSIC Semiconductors Agent or Distributor:
MUSIC Semiconductors reserves the right to make changes to
its products and specifications at any time in order to improve
on performance, manufacturability, or reliability. Information
furnished by MUSIC is believed to be accurate, but no
responsibility is assumed by MUSIC Semiconductors for the use
of said information, nor for any infringement of patents or of
other third party rights which may result from said use. No
license is granted by implication or otherwise under any patent
or patent rights of any MUSIC company.
©Copyright 1999, MUSIC Semiconductors
Worldwide Sales Headquarters
MUSIC Semiconductors
4633 Old Ironsides Drive • Suite #130
Santa Clara, California 95054
USA
Tel: 408-330-7550
http://www.music-ic.com Fax: 408-330-7559
email: [email protected] USA Only: 800-933-1550 Tech. Support
888-226-6874 Product Info.
Rev. 3.0 Draft
28
Asian Sales Office
European Sales Office
MUSIC Semiconductors
MUSIC Semiconductors
Special Export Processing Zone 1 P.O. Box 184
Carmelray Industrial Park
6470 ED Eygelshoven
Canlubang, Calamba, Laguna
The Netherlands
Philippines
Tel: +31 45 546 2177
Tel: +63 49 549 1480
Fax: +31 45 546 3663
Fax: +63 49 549 1024
Sales Tel/Fax: +632 723 62 15