PYRAMID P4C1256L

P4C1256L
LOW POWER 32K x 8
STATIC CMOS RAM
FEATURES
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin 600 mil DIP
—28-Pin 300 mil CERDIP
—28-Pin 300 mil Narrow Body SOP
VCC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE and OE
Inputs
DESCRIPTION
The P4C1256L is a 262,144-bit low power CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
locations are specified on address pins A0 to A14. Reading is accomplished by device selection (CE and output
enabling (OE) while write enable (WE) remains HIGH.
By presenting the address under these conditions, the
data in the addressed memory location is presented on
the data input/output pins. The input/output pins stay in
the HIGH Z state when either CE or OE is HIGH or WE
is LOW.
Access times of 55 ns and 70 ns are available. CMOS
is utilized to reduce power consumption to a low level.
The P4C1256L device provides asynchronous operation with matching access and cycle times. Memory
Package options for the P4C1256L include 28-pin 600
mil DIP, 28-pin 300 mil CERDIP, and 28-pin 300 mil Narrow Body SOP packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P6, D5-2), SOP (S11-3)
TOP VIEW
Document # SRAM121 REV E
Revised June 2007
1
P4C1256L
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Supply Voltage
Commercial (0°C to 70°C)
4.5V ≤ VCC ≤ 5.5V
Industrial (-40°C to 85°C)
4.5 ≤ VCC ≤ 5.5V
MAXIMUM RATINGS(1)
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings
only. Functional operation of the device is not implied at these or any other conditions in excess of those given in
the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely
affect device reliability.
Symbol
Min
Max
Supply Voltage with Respect to GND
-0.5
7.0
V
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
VCC + 0.5
V
TA
Operating Ambient Temperature
-55
125
°C
STG
Storage Temperature
-65
150
°C
IOUT
Output Current into Low Outputs
25
mA
ILAT
Latch-up Current
VCC
VTERM
Parameter
>200
Unit
mA
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
Symbol
Parameter
VOH
Output High Voltage
(I/O0 - I/O7)
IOH = –1mA, VCC = 4.5V
VOL
Output Low Voltage
(I/O0 - I/O7)
IOL = 2.1mA
VIH
Input High Voltage
VIL
Input Low Voltage
ILI
Input Leakage Current
ILO
Output Leakage Current
ISB
VCC Current
TTL Standby Current
(TTL Input Levels)
ISB1
VCC Current
CMOS Standby Current
(CMOS Input Levels)
Document # SRAM121 REV E
Min
Test Conditions
Max
Unit
V
2.4
0.4
V
VCC + 0.3
V
-0.5
0.8
V
2.2
(3)
GND ≤ VIN ≤ VCC
Ind'l.
Com'l.
-5
-2
+5
+2
µA
GND ≤ VOUT ≤ VCC
CE ≥ VIH
Ind'l.
Com'l.
-5
-2
+5
+2
µA
3
mA
100
µA
VCC = 5.5V, IOUT = 0 mA
CE = VIH
VCC = 5.5V, IOUT = 0 mA
CE ≥ VCC -0.2V
Page 2 of 11
P4C1256L
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, F = 1.0 MHz)
Symbol
Parameter
Test Conditions
Max
Unit
CIN
Input Capacitance
VIN = 0V
7
pF
COUT
Output Capacitance
VOUT = 0V
9
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
ICC
Dynamic Operating Current
Temperature
Range
Commercial
Industrial
*
**
-55
-70
-55
70
70
85
85
Unit
15
-70
15
mA
25
25
mA
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e. CE and WE ≤ VIL (max), OE is high. Switching
inputs are 0V and 3V.
**As above but @ f=1 MHz and VIL/ VIH = 0V/ VCC.
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
-70
-55
Min
Max
Min
Max
Unit
tRC
Read Cycle Time
tAA
Address Access Time
55
70
ns
tAC
Chip Enable Access
Time
Output Hold from
Address Change
55
70
ns
tOH
55
70
ns
5
5
ns
5
5
ns
tLZ
Chip Enable to
Output in Low Z
tHZ
Chip Disable to
Output in High Z
20
25
ns
tOE
Output Enable Low
to Data Valid
30
35
ns
tOLZ
Output Enable Low to
Low Z
tOHZ
Output Enable High
to High Z
tPU
Chip Enable to Power
Up Time
tPD
Chip Disable to
Power Down Time
Document # SRAM121 REV E
5
5
25
20
0
ns
0
55
ns
ns
70
ns
Page 3 of 11
P4C1256L
OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
CE CONTROLLED)(5,7)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
Document # SRAM121 REV E
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Page 4 of 11
P4C1256L
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-55
Symbol
Parameter
Min
Max
-70
Min
Max
Unit
tWC
Write Cycle Time
55
70
ns
tCW
Chip Enable Time
to End of Write
50
60
ns
tAW
Address Valid to
End of Write
50
60
ns
tAS
Address Set-up
Time
0
0
ns
tWP
Write Pulse Width
40
50
ns
tAH
Address Hold
Time
0
0
ns
tDW
Data Valid to End
of Write
25
30
ns
tDH
Data Hold Time
0
0
ns
tWZ
Write Enable to
Output in High Z
tOW
Output Active from
End of Write
25
5
30
5
ns
ns
WE CONTROLLED)(10,11)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
Document # SRAM121 REV E
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Page 5 of 11
P4C1256L
CE CONTROLLED)(10)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
TRUTH TABLE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
GND to 3.0V
3ns
Input Timing Reference Level
1.5V
1.5V
Output Timing Reference Level
Output Load
See Figures 1 and 2
Figure 1. Output Load
Mode
CE
OE WE
Standby
Standby
H
X
X
X
X
X
High Z Standby
High Z Standby
DOUT Disabled
L
H
H
High Z
Active
Read
L
L
H
DOUT
Active
Write
L
X
L
High Z
Active
I/O
Power
Figure 2. Thievenin Equivalent
* including scope and test fixture.
Note:
Because of the high speed of the P4C1256L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground.
Document # SRAM121 REV E
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.77V (Thevenin Voltage) at the comparator input, and a
589Ω resistor must be used in series with DOUT to match 639Ω
(Thevenin Resistance).
Page 6 of 11
P4C1256L
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Conditons
VDR
VCC for Data Retention
ICCDR
Data Retention Current
CE ≥ VCC –0.2V,
tCDR
Chip Deselect to
Data Retention Time
VIN ≥ VCC –0.2V
tR†
Operation Recovery Time
Min
Typ.*
VCC =
2.0V
3.0V
Max
VCC =
2.0V
3.0V
V
2.0
or VIN ≤ 0.2V
Unit
10
15
600
900
µA
0
ns
tRC§
ns
*TA = +25°C
§tRC = Read Cycle Time
†
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM121 REV E
Page 7 of 11
P4C1256L
ORDERING INFORMATION
SELECTION GUIDE
The P4C1256L is available in the following temperature, speed and package options.
Temperature
Range
Commercial
Industrial
Speed (ns)
Package
55
70
Plastic DIP, 600 mil
-55PC
-70PC
Ceramic DIP (CERDIP)
-55DC
-70DC
Plastic SOJ, 300 mil
-55SNC
-70SNC
Plastic DIP, 600 mil
-55PI
-70PI
Ceramic DIP (CERDIP)
-55DI
-70DI
-55SNI
-70SNI
Plastic SOJ, 300 mil
Document # SRAM121 REV E
Page 8 of 11
P4C1256L
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
α
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
α
D5-2
CERDIP DUAL IN-LINE PACKAGE
28 (300 mil)
Min
Max
0.225
0.014
0.026
0.045
0.065
0.008
0.018
1.485
0.240
0.310
0.300 BSC
0.100 BSC
0.125
0.200
0.015
0.060
0.005
0°
15°
P6
PLASTIC DUAL IN-LINE PACKAGE
28 (600 mil)
Min
Max
0.090
0.200
0.000
0.070
0.014
0.020
0.015
0.065
0.008
0.012
1.380
1.480
0.485
0.550
0.600
0.625
0.100 BSC
0.600 TYP
0.100
0.200
0°
15°
Document # SRAM121 REV E
Page 9 of 11
P4C1256L
Pkg #
# Pins
Symbol
A
A1
B
C
D
e
E
H
h
L
α
S11-3
SOIC/SOP SMALL OUTLINE IC PACKAGE
28 (300 Mil)
Min
Max
0.094
0.110
0.002
0.014
0.014
0.020
0.008
0.012
0.702
0.710
0.050 BSC
0.291
0.300
0.463
0.477
0.010
0.029
0.020
0.042
0°
8°
Document # SRAM121 REV E
Page 10 of 11
P4C1256L
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM121
P4C1256L LOW POWER 32K x 8 STATIC CMOS RAM
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
1997
DAB
New Data Sheet
A
Oct-05
JDB
Change logo to Pyramid
B
Jun-06
JDB
Added 28-pin ceramic DIP
C
Aug-06
JDB
Added Lead Free Designation
D
Mar-07
JDB
Corrected Narrow SOP width in Ordering Information and Selection
Guide
E
Jun-07
JDB
Corrected Narrow SOP package dimensions
Document # SRAM121 REV E
DESCRIPTION OF CHANGE
Page 11 of 11