Low Power, Low Profile
±2 g Dual Axis Accelerometer with
I2C Interface
MXC6202G/H/M/N
FEATURES
VDD
RoHS compliant
I2C Slave, FAST (≤400 KHz.) mode interface
1.8V compatible IO
Embedded Power up/down and self-test function
On-chip temperature sensor available
Eight customer defined 7-bit addresses
2.7 V to 3.6 V single supply continuous operation
Monolithic CMOS IC
Low power consumption: typically <2 mA @ 3.0 V
Resolution better than 1 milli-g
On chip mixed signal processing
>50,000 g shock survival rating
Low profile LCC package: 5mm X 5mm X 1.55mm
TEMP
Internal
Oscillator
TP
CLK
PD
Temperature
Sensor
CLK
No
Connect
TEMP
Coarse
Gain Adj.
Heater
Control
Fine Gain
Adj.
No
Connect
Temp
Comp.
X aixs
Fine Gain
Adj.
Coarse
Gain Adj.
Temp
Comp.
Y aixs
APPLICATIONS
CLK
A/D
CLK TEMP CLK
CLK
Acceleration
Sensor
CLKTEMP
IIC Convertor
SCL
SDA
A/D
CLK
CLK
GND
Information Appliances – Cell Phones, PDA’s, Computer
Peripherals, Mouse, Smart Pens
Consumer – LCD Projectors, Pedometers, Blood Pressure
Monitor, Digital Cameras
Gaming – Joystick/RF Interface/Menu Selection/Tilt
Sensing
GPS – Electronic Compass Tilt Correction, Dead
Reckoning Assist
GENERAL DESCRIPTION
The MXC6202G/H/M/N are low cost, dual axis
accelerometers fabricated on a standard, submicron CMOS
process. It is a complete sensing system with on-chip
mixed signal processing and integrated I2C bus, allowing
the device to be connected directly to a microprocessor
eliminating the need for A/D converters or timing
resources. The MXC6202G/H/M/N measures acceleration
with a full-scale range of ±2 g and a sensitivity of
512counts/g (G/M) or 128counts/g (H/N) @3.0 V at 25°C.
It can measure both dynamic acceleration (e.g. vibration)
and static acceleration (e.g. gravity). The
MXC6202G/H/M/N design is based on heat convection and
requires no solid proof mass.
Information furnished by MEMSIC is believed to be accurate and reliable. However,
no responsibility is assumed by MEMSIC for its use, or for any infringements of
patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of MEMSIC.
MEMSIC MXC6202G/H/M/N Rev.B
VREF
MXC6202G/H/M/N FUNCTIONAL BLOCK DIAGRAM
This design eliminates the stiction problems associated with
legacy technologies and provides shock survival greater
than 50,000g’s. Memsic’s solid state design leads to
significantly lower failure rates in customer applications
and lower loss due to handling during manufacturing and
assembly processes
The MXC6202G/H/M/N is packaged in a hermetically
sealed, low profile LCC surface mount package (5 mm x 5
mm x 1.55 mm) and is available in operating temperature
ranges of 0°C to +70°C (G/H) and-40°C to +85°C(M/N).
The MXC6202G/H/M/N provides two I2C digital outputs
with 400 KHz, fast mode operation.
The maximum noise floor is 1 mg/ Hz allowing signals
below 1 milli-g to be resolved at 1 Hz bandwidth
©MEMSIC, Inc.
800 Turnpike St., Suite 202, North Andover, MA 01845
Tel: 978.738.0900
Fax: 978.738.0196
www.memsic.com
Page 1 of 10
11/10/2005
ELECTRICAL CHARACTERISTICS (Measurements @ 25°C, Acceleration = 0 g unless otherwise noted; VDD = 3.0V unless
otherwise specified)
Parameter
1
Measurement Range
Nonlinearity
Alignment Error2
Transverse Sensitivity3
Sensitivity
Sensitivity Change Over Temperature
Zero g Offset Bias Level
Zero g Offset TC
Tout
Tout Sensitivity
Noise Density, RMS
Resolution
Frequency Response
Self-test
Output Drive Capability
Turn-On Time4
Operating Voltage Range
Supply Current
Power Down Current
Operating Temperature Range
Conditions
Min
Each Axis
Best fit straight line
±2.0
MXC6202G/M
MXC6202H/N
∆ from 25°C
MXC6202G/H
MXC6202M/N
MXC6202G/M
MXC6202H/N
∆ from 25°C
MXC6202G/M
MXC6202H/N
MXC6202G/M
MXC6202H/N
within 20Hz
486
118
@ 1Hz. BW
@ -3dB
-10
-15
1996
492
2550
635
2.00
0.48
15
1.7
Typ
Max
0.5
±1.0
±2.0
512
128
1.0
2048
512
0.8
2710
675
2.33
0.58
0.7
0.5
17
2.2
@ 2.7 V – 3.6 V
2.7
MXC6202G/H
MXC6202M/N
0
-40
75
3.0
1.8
538
138
+8
+10
2100
532
2870
715
2.60
0.68
1.0
1.0
19
2.7
100
100
3.6
2.5
1.0
+70
+85
Units
G
% of FS
degrees
%
counts/g
counts/g
%
%
counts
counts
mg/°C
counts
counts
counts/°C
counts/°C
mg/ Hz
mg
Hz
G
µA
mS
V
mA
µA
°C
°C
NOTES:
1
Guaranteed by measurement of initial offset and sensitivity
2
Alignment error is specified as the angle between the true and indicated
axis of sensitivity
3
Cross axis sensitivity is the algebraic sum of the alignment and the
inherent sensitivity errors
4
Output settled to within ± 17mg
MEMSIC MXC6202G/H/M/N Rev.B
Page 2 of 10
11/10/2005
I2C INTERFACE I/O CHARACTERISTICS
Parameter
Symbol
Test Condition
Min.
Typ.
Max.
Unit
0.6
V
Logic Input Low Level
VIL
-0.5
Logic Input High Level
VIH
1.4
V
Hysteresis of Schmitt input
Vhys
0.2
V
Logic Output Low Level
VOL
Input Leakage Current
Ii
SCL Clock Frequency
fSCL
START Hold Time
tHD;STA
0.6
µS
START Setup Time
tSU;STA
0.6
µS
LOW period of SCL
tLOW
1.3
µS
HIGH period of SCL
tHIGH
0.6
µS
Data Hold Time
tHD;DAT
0
Data Setup Time
tSU;DAT
0.1
Rise Time
tr
From VIL to VIH
0.3
µS
Fall Time
tf
From VIH to VIL
0.3
µS
Bus Free Time Between STOP and
START
STOP Setup Time
tBUF
1.3
µS
tSU;STO
0.6
µS
0.4
0.1Vdd<Vin<0.9Vdd
-10
10
µA
0
400
kHz
0.9
µS
µS
Timing Definition
MEMSIC MXC6202G/H/M/N Rev.B
Page 3 of 10
11/10/2005
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) ………………...-0.5 V to +7.0V
Storage Temperature ……….…………-65°C to +150°C
Acceleration ……………………………………..50,000 g
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; the functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Pin Description: LCC-8 Package
Pin
Name
Description
1
NC
Do Not Connect
2
COM
Connected to Ground
3
GND
Connected to Ground
4
TEST
Do Not Connect
5
VDD2
Power Supply for I2C bus
6
SCL
Serial Clock Line for I2C bus
7
SDA
Serial Data Line for I2C bus
8
VDD
2.7 V to 3.6 V
Note: The MEMSIC logo’s arrow indicates the -X sensing
direction of the device. The +Y sensing direction is rotated 90°
away from the +X direction following the right-hand rule. Small
circle indicates pin one (1).
Ordering Guide
MXC6202XGP
Package type:
Code
P
B
Type
LCC8
RoHS compliant
LCC8, Pb-free
RoHS compliant
Performance Grade:
Code
Temp
G
0~70°C
H
0~70°C
M
-40~85°C
N
-40~85°C
Resolution
4096counts
1024counts
4096counts
1024counts
Address code: 0~7
Number Address
0
20H
1
22H
2
24H
3
26H
4
28H
5
2AH
6
2CH
7
2EH
All parts are shipped in tape and reel packaging.
Caution: ESD (electrostatic discharge) sensitive device.
MEMSIC MXC6202G/H/M/N Rev.B
Page 4 of 10
11/10/2005
TYPICAL CHARACTERISTICS, % OF UNITS (@ 25°C, VDD = 3V)
OffsetX Distribution
OffsetY Distribution
60%
60%
50%
50%
40%
40%
30%
30%
20%
20%
10%
10%
Offset (mg)
Offset (mg)
0%
0%
-96
-76
-56
-36
-15
5
25
46
66
86
-96
-76
-56
-36
-15
5
25
46
66
86
0g OffsetY Deviation to Target
0g OffsetX Deviation to Target
SensitivityX Distribution
SensitivityY Distribution
35%
35%
30%
30%
25%
25%
20%
20%
15%
15%
10%
10%
5%
Sen (mg)
0%
5%
Sen (mg)
0%
-48
-38
-28
-18
-8
3
13
23
33
43
-48
SensitivityX Deviation to Target
MEMSIC MXC6202G/H/M/N Rev.B
-38
-28
-18
-8
3
13
23
33
43
SensitivityY Deviation to Target
Page 5 of 10
11/10/2005
OVER TEMPERATURE CHARACTERISTICS
Tout vs. Temp
Tout Sensitivity Distribution
3000
25%
2950
2900
20%
2850
2800
15%
2750
2700
10%
2650
2600
5%
2550
2500
-50
Tout TC
T(C)
0%
-10
30
70
2.02
110
2.11
2.29
2.38
2.47
2.56
Normalized SensitivityY vs. Temp
Normalized SensitivityX vs. Temp
1.10
1.10
1.08
1.08
1.06
1.06
1.04
1.04
1.02
1.02
1.00
1.00
0.98
0.98
0.96
0.96
0.94
0.94
0.92
0.92
0.90
0.90
0.88
0.88
-50
2.20
-10
30
70
T(C) 110
-50
-10
OffsetX TC Distribution
30
70
T(C) 110
OffsetY TC Distribution
30%
30%
25%
25%
20%
20%
15%
15%
10%
10%
5%
5%
TC(mg/C)
0%
TC(mg/C)
0%
-1.9
-1.3
-0.7
-0.1
0.5
MEMSIC MXC6202G/H/M/N Rev.B
1.1
1.7
-1.9
Page 6 of 10
-1.3
-0.7
-0.1
0.5
1.1
1.7
11/10/2005
A single heat source, centered in the silicon chip is
suspended across a cavity. Equally spaced
aluminum/polysilicon thermopiles (groups of
thermocouples) are located equidistantly on all four sides of
the heat source (dual axis). Under zero acceleration, a
temperature gradient is symmetrical about the heat source,
so that the temperature is the same at all four thermopiles,
causing them to output the same voltage.
Acceleration in any direction will disturb the temperature
profile, due to free convection heat transfer, causing it to be
asymmetrical. The temperature, and hence voltage output
of the four thermopiles will then be different. The
differential voltage at the thermopile outputs is directly
proportional to the acceleration. There are two identical
acceleration signal paths on the accelerometer, one to
measure acceleration in the x-axis and one to measure
acceleration in the y-axis. Please visit the MEMSIC
website at www.memsic.com for a picture/graphic
description of the free convection heat transfer principle.
DISCUSSION OF TILT APPLICATIONS AND
RESOLUTION
Tilt Applications: One of the most popular applications of
the MEMSIC accelerometer product line is in
tilt/inclination measurement. An accelerometer uses the
force of gravity as an input to determine the inclination
angle of an object.
A MEMSIC accelerometer is most sensitive to changes in
position, or tilt, when the accelerometer’s sensitive axis is
perpendicular to the force of gravity, or parallel to the
Earth’s surface. Similarly, when the accelerometer’s axis is
parallel to the force of gravity (perpendicular to the Earth’s
surface), it is least sensitive to changes in tilt.
Following table and figure help illustrate the output
changes in the X- and Y-axes as the unit is tilted from +90°
to 0°. Notice that when one axis has a small change in
output per degree of tilt (in mg), the second axis has a large
change in output per degree of tilt. The complementary
nature of these two signals permits low cost accurate tilt
sensing to be achieved with the MEMSIC device (reference
application note AN-00MX-007).
MEMSIC
THEORY OF OPERATION
The MEMSIC device is a complete dual-axis acceleration
measurement system fabricated on a monolithic CMOS IC
process. The device operation is based on heat transfer by
natural convection and operates like other accelerometers
except that the proof mass in the MEMSIC sensor is a gas.
MXC6202G/H/M/N PIN DESCRIPTIONS
VDD – This is the supply input for the circuits and the
sensor heater in the accelerometer. The DC voltage should
be between 2.7 and 3.6 volts. Refer to the section on PCB
layout and fabrication suggestions for guidance on external
parts and connections recommended.
Accelerometer Position Relative to Gravity
GND– This is the ground pin for the accelerometer.
X-Axis
COM– This pin should be connected to ground.
TEST– Do Not Connect, factory use only.
VDD2– This pin is the I2C input digital power supply, the
voltage on this pin determines the I2C bus logic voltage,
and is 1.8V compatible. Note: The voltage on this pin
should never go higher than the voltage on VDD, if VDD2
has a lower power supply voltage than VDD, power should
be applied to VDD first.
X-Axis
Orientatio
n
To Earth’s
Surface
(deg.)
SDA– This pin is the I2C serial data line, and operates in
FAST (400 KHz.) mode.
SCL– This pin is the I2C serial clock line, and operates in
FAST (400 KHz.) mode.
MEMSIC MXC6202G/H/M/N Rev.B
Page 7 of 10
90
85
80
70
60
45
30
20
10
5
0
X Output
(g)
Change
per deg.
of tilt
(mg)
Y-Axis
Y Output
(g)
1.000
0.15
0.000
0.996
1.37
0.087
0.985
2.88
0.174
0.940
5.86
0.342
0.866
8.59
0.500
0.707
12.23
0.707
0.500
15.04
0.866
0.342
16.35
0.940
0.174
17.16
0.985
0.087
17.37
0.996
0.000
17.45
1.000
Changes in Tilt for X- and Y-Axes
Change
per deg.
of tilt
(mg)
17.45
17.37
17.16
16.35
15.04
12.23
8.59
5.86
2.88
1.37
0.15
11/10/2005
RESOLUTION
The accelerometer resolution is limited by noise. The
output noise will vary with the measurement bandwidth.
With the reduction of the bandwidth, by applying an
external low pass filter, the output noise drops. Reduction
of bandwidth will improve the signal to noise ratio and the
resolution. The output noise scales directly with the square
root of the measurement bandwidth. The maximum
amplitude of the noise, its peak- to- peak value,
approximately defines the worst case resolution of the
measurement. With a simple RC low pass filter, the rms
noise is calculated as follows:
Noise (mg rms) = Noise(mg/ Hz ) * ( Bandwidth( Hz) *1.6)
The peak-to-peak noise is approximately equal to 6.6 times
the rms value (for an average uncertainty of 0.1%).
HARDWARE DESIGN CONSIDERATION
1. One capacitor is recommended for best rejection of
power supply noise (reference figure below). The
capacitor should be located as close as possible to the
device supply pin (VDD). The capacitor lead length
should be as short as possible, and a surface mount
capacitor is preferred. For typical applications, the
capacitor can be ceramic 0.1 µF.
SOFTWARE DESIGN CONSIDERATION
In order to further reduce the noise on the I2C bus, we
recommend to use the following software limiter filter in
the acceleration signal process routine:
Int iAccReal[0x02];//Real-time acceleration data array
Int iAccFilter;//Filtered acceleration data
SoftwareLimiterFilter()
{
if (abs(iAccReal[0x00]-iAccReal[0x01])<0x80) then
iAccFilter=iAccReal[0x00];
iAccReal[0x01]= iAccReal[0x00];
}
I2C INTERFACE DESCRIPTION
A slave mode I2C circuit has been implemented into the
Memsic thermal accelerometer as a standard interface for
customer applications. The A/D converter and MCU
functionality have been added to the Memsic sensor,
thereby increasing ease-of-use, and lowering power
consumption, footprint and total solution cost.
The I2C (or Inter IC bus) is an industry standard bidirectional two-wire interface bus. A master I2C device can
operate READ/WRITE controls to an unlimited number of
devices on the bus by proper addressing. The Memsic
accelerometer operates only in a slave mode, i.e. only
responding to calls by a master device
I2C BUS CHARACTERISTICS
Power supply noise rejection
2.
3.
4.
5.
Robust low inductance ground wiring should be used.
Care should be taken to ensure there is “thermal
symmetry” on the PCB immediately surrounding the
MEMSIC device and that there is no significant heat
source nearby. Based on the experiment, with a
120degC heating source at 11mm away of MEMSIC
device, the offset change will be within 5mg.
A metal ground plane should be added directly beneath
the MEMSIC device. The size of the plane should be
similar to the MEMSIC device’s footprint and be as
thick as possible.
Vias can be added symmetrically around the ground
plane. These vias will increase the thermal isolation of
the device from the rest of the PCB and improve
performance.
MEMSIC MXC6202G/H/M/N Rev.B
I2C bus
The two wires in I2C bus are called SDA (serial data line)
and SCL (serial clock line). In order for a data transfer to
start, the bus has to be free, which is defined by both wires
in a HIGH output state. Due to the open-drain/pull-up
resistor structure and wire-AND operation, any device on
the bus can pull lines low and overwrite a HIGH signal.
The data on the SDA line has to be stable during the HIGH
period of the SCL line. In other words, valid data can only
change when the SCL line is LOW.
Page 8 of 10
11/10/2005
I2C BUS DATA TRANSFER
A data transfer is started with a “START” condition and
ended with a “STOP” condition. A “START” condition is
defined by a HIGH to LOW transition on the SDA line
while SCL line is HIGH. A “STOP” condition is defined by
a LOW to HIGH transition on the SDA line while SCL line
is HIGH. All data transfer in I2C system is 8-bits long. Each
byte has to be followed by an acknowledge bit. Each data
transfer involves a total of 9 clock cycles. Data is
transferred starting with the most significant bit (MSB).
After a “START” condition, master device calls a specific
slave device, in our case, the Memsic accelerometer with a
7-bit device address. To avoid potential address conflict,
either by ICs from other manufacturers or by other Memsic
accelerometers on the same bus, a total of 8 different
addresses can be programmed into a Memsic device at the
factory.
Following the 7-bit address, the 8th bit determines the
direction of data transfer: [1] for READ and [0] for
WRITE. After being addressed, the available Memsic
device being called will respond by an “Acknowledge”
signal, which is pulling SDA line LOW.
output register refresh rate. Unused MSB’s will be simply
filled by “0”s.
Note that temperature output shares the same registers with
X channel output. Customer can select which signal needs
to be read out by using TOEN bit.
Resolution
Refreshing rate
Zero-G Offset
10 bits
400Hz
512
12 bits
100Hz
2048
The master can stop slave data transfer after any of the five
bytes by not sending an acknowledge command and
followed by a “STOP” condition.
In order to read an acceleration signal, the master device
should operate a WRITE action with a code of [xxxxxxx0]
into the Memsic device 8-bit internal register.
Bit
0
1
2
3
Name
Function
PD (Power Down)
Power down [1]/on [0]
ST (Self-test)
Self-test on [1]/off [0]
BGTST (bandgap test) Bandgap test [1]/normal[0]
TOEN (temperature Temp Out EN [1]/disable[0]
out enable)
The ST bit serves as a self-test function to verify the
Memsic accelerometer is operating properly. BGTST is
used to calibrate the temperature output signal’s initial
offset. By flipping the BGTST bit and taking the average of
two readings, the temperature output initial offset will be
calibrated to within datasheet specifications.
After writing code of [xxxxxxx0] into the control register,
if a “READ” signal is received, during next 9 clock cycles,
the Memsic device being called will transfer 8-bits of data
to the I2C bus. If an “Acknowledge” by master device is
received, the Memsic device will continue to transfer the
next byte. The same procedure repeats until 5 bytes of data
are transferred to master device. Those 5 bytes of data are
defined as following (“T” is temperature output):
1. Internal register
2. MSB X/T axis
3. LSB X/T axis
4. MSB Y axis
5. LSB Y axis
Even though each axis consists of two bytes, which are 16bits of data, the actual accelerometer resolution is limited to
either 12 bits or 10 bits, which depends on an internal
MEMSIC MXC6202G/H/M/N Rev.B
Data transfer
POWER DOWN MODE
The Memsic accelerometer can enter a power down mode
by the master device writing a code of [xxxxxxx1] into the
accelerometer’s internal register. A wake up operation is
performed when the master writes into the same register a
code of [xxxxxxx0]. Note that the MXC6202G/H/M/N
needs about 75mS (typical) for power up time.
EXAMPLE OF DATA COMMUNICATION
First cycle: START followed by a calling to slave address
[0010xxx] to WRITE (8th SCL, SDA keep low). [xxx] Is
determined by factory programming, a total of 8 different
addresses are available.
Second cycle: After an acknowledge signal is received by
the master device (Memsic device pulls SDA line low
during 9th SCL pulse), master device sends “[00000000]” as
the target address to be written into. Memsic device should
acknowledge at the end (9th SCL pulse). Note: since
Memsic device has only one internal register that can be
written into, user should always indicate “[00000000]” as
the write address.
Third cycle: Master device writes to internal Memsic
device memory code “[xxxxxxx0]” as a wake-up call. The
Memsic device should send acknowledge signal. A STOP
command indicates the end of write operation. A 75msS
(typical) wait period should be given to Memsic device to
return from a power-down mode. The delay value depends
on the type of Memsic device. Generally speaking, low
power products tend to have longer startup time.
Page 9 of 10
11/10/2005
Fourth cycle: Master device sends a START command
followed by calling Memsic device address with a WRITE
(8th SCL, SDA keep low). An “acknowledge” should be
sent by Memsic device at the end.
Fifth cycle: Master device writes to Memsic device a
“[00000000]” as the starting address for which internal
memory is to be read. Since “[00000000]” is the address of
internal control register, reading from this address can serve
as a verification of operation and to confirm the write
command has been successful. Note: the starting address in
principle can be any of the 5 addresses. For example, user
can start read from address [0000001], which is X channel
MSB.
Sixth cycle: Master device calls Memsic device address
with a READ (8th SCL cycle SDA line high). Memsic
device should acknowledge at the end.
Seventh cycle: Master device cycles SCL line, first
addressed memory data appears on SDA line. If in step 7,
“[00000000]” was sent, internal control register data
should appear (in the following steps, this case is assumed).
Master device should send acknowledge at the end.
Eighth cycle: Master device continues cycle SCL line, next
byte of internal memory should appear on SDA line (MSB
of X channel). The internal memory address pointer
automatically moves to the next byte. Master
acknowledges.
Ninth cycle: LSB of X channel. In the case that TOEN bit
of internal register was set to “1”, the MSB and LSB of
TOUT (temperature) should appear in last two steps.
Tenth cycle: MSB of Y channel.
Eleventh cycle: LSB of Y channel.
Master ends communications by sending NO acknowledge
and followed by a STOP command. Note: if mater device
continues to cycle SCL line, the memory pointer will go to
sixth and seventh positions, which always have
“[00000000]”. After seventh position, pointer will go to
zero again.
Optional: Master powers down Memsic device by writing
into internal control register. (See step 1 through 4 for
WRITE operation)
LCC-8 PACKAGE DRAWING
Hermetically Sealed Package Outline
MEMSIC MXC6202G/H/M/N Rev.B
Page 10 of 10
11/10/2005