Century Semiconductor Inc. CS5825 28:4 LVDS Receiver GENERAL DESCRIPTION FEATURES CS5825 receives four LVDS data channels and one LVDS clock channel. Each data channel is deserialized into 7-bit parallel data bus for output. The clock channel is used for frame sync and fed into an internal PLL that generates the 7X serial clock used in the deserializer. A digital phase alignment circuit can generate the sampling clock of the deserializer front-end. The frame sync clock aligned to the output 7-bit data is also output for timing reference. CS5825 supports open-safe design of LVDS when the input is not connected to LVDS drivers and the receiver outputs are forced low. Putting CS5825 into inhibit mode by a shutdown control (SHTDNN) signal can lower power consumption. • Four 7-bit serial data LVDS channels and one clock LVDS channel. • Compatible with ANSI TIA/EIA-644 LVDS standard. • Wide serial clocking speed ranges from 31MHz to 68MHz. • Support open-safe LVDS design. • Fully integrated on-chip PLL and digital phase alignment provide accurate deserializer operation. • Support power-down mode. • 5V/3.3V tolerant data input. • Single 3.3V supply operation. • CMOS low power consumption. • Functional compatible with DS90CF384 and SN75LVDS86. • Available in 56-pin TSSOP package. BLOCK DIAGRAM CS5825 AIP DIN AIM CLK BIP DIN BIM PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER CLK D0,D1,D2,D3, D4,D6,D7 D8,D9,D12,D13, D14,D15,D18 CIP DIN CIM PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER CLK D19,D20,D21,D22, D24,D25,D26 DIP DIN DIM PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER CLK 7xCLK CKIP CKIM SHTDNN PHASE LOCK LOOP AND PHASE ALIGNER D27,D5,D10,D11, D16,D17,D23 CLKOUT CONTROL LOGIC CS5825 Century Semiconductor, Inc. Taiwan: No. 2, Industry East Rd. 3rd, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349 USA: 1485 Saratoga Ave. #200 San Jose, CA, 95129 Tel: 408-973-8388 Fax: 408-973-9388 [email protected] [email protected] www.century-semi.com Rev.0.0 May 2001 page 1 of 13 Century Semiconductor Inc. CS5825 PIN CONNECTION DIAGRAM D22 1 56 VDD D23 2 55 D21 D24 3 54 D20 VSS 4 53 D19 D25 5 52 VSS D26 6 51 D18 D27 7 50 D17 LVDS_VSS 8 49 D16 AIM 9 48 VDD AIP 10 47 D15 BIM 11 46 D14 BIP 12 45 D13 LVDS_VDD 13 44 VSS LVDS_VSS 14 43 D12 CIM 15 42 D11 CIP 16 41 D10 CKIM 17 40 VDD CKIP 18 39 D9 DIM 19 38 D8 DIP 20 37 D7 LVDS_VSS 21 36 VSS PLL_VSS 22 35 D6 PLL_VDD 23 34 D5 PLL_VSS 24 33 D4 SHTDNN 25 32 D3 CLKOUT 26 31 VDD D0 27 30 D2 VSS 28 29 D1 CS5825 Figure-1 56-pin TSSOP page 2 of 13 Century Semiconductor Inc. CS5825 PIN DESCRIPTION Name Pin Description AIP, AIM I LVDS data channel A input. These are differential LVDS inputs for A channel corresponds to D0, D1, D2, D3, D4, D6, D7. AIP is the positive data input and AIM is the negative input. BIP, BIM I LVDS data channel B output. These are differential LVDS inputs for B channel corresponds to D8, D9, D12, D13, D14, D15, D18. CIP, CIM I LVDS data channel C output. These are differential LVDS outputs for C channel corresponds to D19, D20, D21, D22, D24, D25, D26. DIP, DIM I LVDS data channel C output. These are differential LVDS outputs for D channel corresponds to D27, D5, D10, D11, D16, D17, D23. CKIP, CKIM I LVDS clock channel input. These are differential LVDS input for the frame sync clock. The clock is sent to an on-chip PLL to generate 7X serial clock; An phase aligner is used to align the deserializer clock. D0,D1,D2,D3,D4, D6, D7 O Parallel data output for LVDS channel A. D[0] is LSB and D[7] is MSB. MSB is shifted in first. D8,D9,D12,D13, D14,D15,D18 O Parallel data output for LVDS channel B. D[8] is LSB and D[18] is MSB. D19,D20,D21,D22 ,D24,D25,D26 O Parallel data output for LVDS channel C. D[19] is LSB and D[26] is MSB. D27,D5,D10,D11, D16,D17,D23 O Parallel data output for LVDS channel C. D[19] is LSB and D[23] is MSB. CLKOUT O Parallel data clock output. This clock signal recovered clock for data output reference. The falling edge should be used as the strobe for the next stage. SHTDNN I Shutdown control (low active). When SHTDNN is low, the internal PLL is put into inhibit mode and all data outputs are forced low. This also resets all internal registers. For normal operation, SHTDNN should be set to high. VDD P Positive power supply for TTL outputs. A 3.3V supply should be used. VSS P Negative power supply. Connect to 0V. LVDS_VDD P Positive power supply for LVDS inputs. LVDS_VSS P Negative power supply for LVDS inputs. PLL_VDD P Positive power supply for PLL. PLL_VSS P Negative power supply for PLL. page 3 of 13 Century Semiconductor Inc. CS5825 FUNCTIONAL DESCRIPTION Serial-In Parallel-Out 7-Bit Shift Register It receives the serial data from the transmitter. It uses the 7xclk to strobe the serial data and sends 7-bit parallel data with input clock’s frequency. Phase Lock Loop and Phase Aligner The PLL generates the seven times input clock which is used for deserialized. The phase aligner is used for synchronous the input clock and output. Control logic There are two modes in this circuit. One is normal mode, and another is power down mode. Two modes are controlled by the control signal “SHTDNN”. If SHTDNN is high, the circuit is in the normal mode, else if low, the circuit is in the power down mode. In the power down mode, every block is off to make sure the least power consumption. page 4 of 13 Century Semiconductor Inc. CS5825 Recommended Operating Conditions Symbol Min Typ Max Unit Supply voltage 3 3.3 3.6 V VIH(SHTDN) High-level input voltage 2 - - V VIL(SHTDN) Low-level input voltage - - 0.8 V Receiver input range 0 - 2.4 V Operating free-air temperature 0 - 70 °C Min Typ Max Unit Cycle time, input clock* 14.7 tc 32.4 ns tsu1 Setup time, input 600 - - ps th1 Hold time, input 600 - - ps VCC TA Parameter Timing Requirements Symbol tc Parameter Note: Parameter tc is defined as the mean duration of a minimum of 32000 clock cycles. Electrical Characteristics over recommended operating conditions (unless otherwise noted) Symbol Parameter VIT+ Min Typ Max Unit Differential input high threshold voltage - - 100 mV VIT- Differential input low threshold voltage -100 - - mV VOH High-level output voltage IOH = -4mA 2.4 - - V VOL Low-level output voltage IOL = 4mA - - 0.4 V Disabled (power down mode), All inputs open - 280 - µA Enabled, AnP = 1V, AnM = 1.4V, tc = 15.38ns - 58 72 mA Enabled, CL = 8 pF, Grayscale pattern, tc = 15.38ns - 69 - mA Enabled, CL = 8 pF, Grayscale pattern, tc = 15.38ns - 94 - mA ICC Quiescent current (average) Condition IIH High-level input current (SHTDN) VIH = VCC - - ±20 µA IIL Low-level input current (SHTDN) VIL = 0 - - ±20 µA II Input current (LVDS input terminals A and CLKIN) 0 ≤ V1 ≤ 2.4V - - ±10 µA High-impedance output current VO = 0 or VCC - - ±10 µA IOZ page 5 of 13 Century Semiconductor Inc. CS5825 Switching Characteristics over recommended operating conditions (unless otherwise noted) Symbol Parameter tsu2 Setup time, D0 - D20 valid to CLKOUT↓ th2 Hold time, CLKOUT↓ to D0 - D20 valid Condition CL = 8pF (Figure-3) Min Typ Max Unit 5 - - ns 5 - - ns Receive input skew margin tc = 15.38 ns (±0.2%), Input clock jitter < 50 ps (Figure-4) 490 - - ps td Delay time, CLKIN↑ to CLKOUT ↓ tc = 15.38 ns (±0.2%), CL = 8 pF - 3.7 - ns ∆ tc(o) Cycle time, change in output clock period# - ± 100 - ps ten Enable time, SHTDN↑ to Dn valid Figure-6 - 1 - ms tdis Disable time, SHTDN↓ to off state Figure-7 - 400 - ns tt Transition time, output (10% to 90% tr or tf) CL = 8pF - 3 - ns tw Pulse duration, output clock - - 0.43tc - ns tRSKM Switching Characteristics Symbol Parameter Min Typ Max Unit LHT low to high transition time - 2.2 5 ns HLT high to low transitions time - 2.2 5 ns Pos0 input strobe position for bit 0 (f = 65MHz) 0.7 1.1 1.4 ns Pos1 input strobe position for bit 1 (f = 65MHz) 2.9 3.3 3.6 ns Pos2 input strobe position for bit 2 (f = 65MHz) 5.1 5.5 5.8 ns Pos3 input strobe position for bit 3 (f = 65MHz) 7.3 7.7 8.0 ns Pos4 input strobe position for bit 4 (f = 65MHz) 9.5 9.9 10.2 ns Pos5 input strobe position for bit 5 (f = 65MHz) 11.7 12.1 12.4 ns Pos6 input strobe position for bit 6 (f = 65MHz) 13.9 14.3 14.6 ns SKM Rxin skew margin (f = 65MHz) 400 - - ps COP RxCLK OUT Period 14.7 - 32.2 ns COH RxCLK OUT high time (f = 65MHz) 7.5 - - ns COL RxCKK OUT low time (f = 65MHz) 3.5 - - ns SRC RxOUT setup to RxCLKOUT (f = 65MHz) 2.5 - - ns HRC RxOUT hold to RxCLKOUT (f = 65MHz) 2.5 - - ns CCD RxCLK In to RxCLK OUT delay 5 - 9 ns PLLs Phase Lock Loop set - - 10 ms PDD Power down delay - - 1 µs page 6 of 13 Century Semiconductor Inc. CS5825 Electrical Characteristics Symbol Parameter Condition Min Typ Max Unit IRCCG Receiver Supply Current CL= 8pF, f = 65MHz (Worst Case pattern) - - - mA IRCCW Receiver Supply Current CL = 8pF,f = 65MHz (Grayscale pattern) - - - mA IRCCS Receiver Power Down Supply Current - 200 300 µA Power Down = Low page 7 of 13 Century Semiconductor Inc. CS5825 TIMING DIAGRAMS CMOS/TTL OUTPUT CS 8pF Figure-2 CMOS/TTL Output Load 80% 80% 20% 20% LHT HLT Figure-3 CMOS/TTL Output Transition Times COP 2.0v 2.0v CLKOUT 0.8v COH COL SRC D[20:0] 2.0v Setup HRC 2.0v Hold Figure-4 Setup/Hold and High/Low Times page 8 of 13 Century Semiconductor Inc. CS5825 TEST PATTERN CLKIN D0, 6, 12 D1, 7, 13 D2, 8, 14 D3, 9, 15 D18, 19, 20 D4, 5, 10, 11, 16, 17 Figure-5 16-Grayscale Testing Pattern Waveforms tsu2 CLKIN/CLKOUT Even Dn Odd Dn Figure-6 The Worst-case Testing Pattern Waveforms tsu2 70% VOH D0 - D20 30% VOH th2 70% VOH CLKOUT 30% VOH Figure-7 Setup and Hold Time Waveforms page 9 of 13 Century Semiconductor Inc. CS5825 PARAMETER MEASUREMENT INFORMATION tc 4/7 tc ± t(RSKM) (see Note A) tsu1 th1 3/7 tc ± t(RSKM) (see Note A) An and An CLKIN 7 x CLK (Internal) td tW CLKOUT tr < 1ns 80% CLKIN or An ≈ 300mV 0V 20% ≈ -300mV td tW VOH 1.4V VOL CLKOUT NOTE A: CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance or delay is then reduced until there are no data errors observed. The magnitude of the advance or delay is t(RSKM). Figure-8 Receiver Input Skew Margin, Setup/Hold Time, and Delay Time Definitions page 10 of 13 Century Semiconductor Inc. CS5825 Vdiff=0v CKIP/CKIM CCD CLKOUT Figure-9 Clock-in to Clock-out Delay 2V Power Down 3V Vcc PLLs CKIP/CKIM 2V RxCLK OUT Figure-10 Phase Lock Loop Stable Time Power Down (Low Active) 1.5V RxCLK In PDD RxOUT Low Figure-11 Power Down Delay page 11 of 13 Century Semiconductor Inc. CS5825 CKIP/CKIM AI BI CI Pos0 Min. Pos0 Max. Pos1 Min Pos1 Max. Pos2 Min. Pos2 Max. Pos3 Min. Pos3 Max. Pos4 Min. Pos4 Max. Pos5 Min. Pos5 Max. Pos6 Min. Pos6 Max. Figure-12 Strobe positions of LVDS inputs Ideal Strobe Position *IP or *IM ~1.4V C *IM or *IP ~1.0V RSKM min. max. Tpposn RSKM min. max. Rsposn min. max. Tpposn+1 Figure-13 Skew Margin of LVDS data inputs page 12 of 13 Century Semiconductor Inc. CS5825 PACKAGE OUTLINE (56-pin TSSOP) D c E1 E L θ A2 A A1 b e Symbol Dimensions in Millimeters Dimensions in Inches MIN NOM MAX MIN NOM MAX A 1.05 - 1.20 0.041 - 0.047 A1 0.05 - 0.15 0.002 - 0.006 A2 - 0.90 - - 0.035 - b 0.17 0.20 0.27 0.007 0.008 0.010 c 0.09 0.15 0.20 0.004 0.006 0.008 D 13.90 14.00 14.10 0.547 0.551 0.555 E 7.80 8.10 8.40 0.307 0.319 0.330 E1 6.00 6.10 6.20 0.236 0.240 0.244 e - 0.50 - - 0.0197 - L 0.50 - 0.75 0.020 - 0.030 θ 0° - 7° 0° - 7° page 13 of 13