DS90C363/DS90CF364 +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link— 65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link— 65 MHz General Description Features The DS90C363 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF364 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 170 Mbytes/sec. The Transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The Transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge Transmitter will interoperate with a Falling edge Receiver (DS90CF364) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. n 20 to 65 MHz shift clock support n Programmable Transmitter (DS90C363) strobe select (Rising or Falling edge strobe) n Single 3.3V supply n Chipset (Tx + Rx) power consumption < 250 mW (typ) n Power-down mode ( < 0.5 mW total) n Single pixel per clock XGA (1024x768) ready n Supports VGA, SVGA, XGA and higher addressability. n Up to 170 Megabyte/sec bandwidth n Up to 1.3 Gbps throughput n Narrow bus reduces cable size and cost n 290 mV swing LVDS devices for low EMI n PLL requires no external components n Low profile 48-lead TSSOP package n Falling edge data strobe Receiver n Compatible with TIA/EIA-644 LVDS standard n ESD rating > 7 kV n Operating Temperature: −40˚C to +85˚C Block Diagrams Application DS012886-14 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS012886 www.national.com DS90C363/DS90CF364 +3.3V Programmable LVDS 18-Bit-Color Flat Panel Display (FPD) Link — 65 MHz September 1999 Block Diagrams (Continued) DS90C363 DS012886-1 Order Number DS90C363MTD See NS Package Number MTD48 DS90CF364 DS012886-24 Order Number DS90CF364MTD See NS Package Number MTD48 www.national.com 2 Absolute Maximum Ratings (Note 1) DS90C363 DS90CF364 Package Derating: DS90C363 DS90CF364 ESD Rating (HBM, 1.5 kΩ, 100 pF) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 sec) Maximum Package Power Dissipation MTD48 (TSSOP) Package: −0.3V −0.3V −0.3V −0.3V to to to to −0.3V to +4V (VCC + 0.3V) (VCC + 0.3V) (VCC + 0.3V) (VCC + 0.3V) 1.98 W 1.89 W 16 mW/˚C above +25˚C 15 mW/˚C above +25˚C > 7 kV Recommended Operating Conditions Continuous +150˚C −65˚C to +150˚C Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) +260˚C Capacity 25˚C Min 3.0 Nom 3.3 Max 3.6 Units V −40 0 +25 +85 2.4 100 ˚C V mVPP Max Units V Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ CMOS/TTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC VIL Low Level Input Voltage GND 0.8 VOH High Level Output Voltage IOH = −0.4 mA 2.7 3.3 V V VOL Low Level Output Voltage IOL = 2 mA VCL Input Clamp Voltage ICL = −18 mA IIN Input Current VIN = VCC, GND, 2.5V or 0.4V ± 5.1 ± 10 µA IOS Output Short Circuit Current VOUT = 0V −60 −120 mA 345 450 mV 35 mV 0.06 0.3 V −0.79 −1.5 V LVDS DC SPECIFICATIONS VOD Differential Output Voltage ∆VOD Change in VOD between RL = 100Ω 250 complimentary output states VOS Offset Voltage (Note 4) ∆VOS Change in V OS 1.125 1.25 1.375 V 35 mV −3.5 −5 mA ±1 ± 10 µA +100 mV between complimentary output states IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω IOZ Output TRI-STATE ® Current PWR DWN = 0V, VOUT = 0V or VCC VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current VCM = +1.2V −100 mV VIN = +2.4V, VCC = 3.6V VIN = 0V, VCC = 3.6V ± 10 ± 10 µA µA TRANSMITTER SUPPLY CURRENT ICCTW ICCTG Transmitter Supply Current, Worst Case Transmitter Supply Current, 16 Grayscale RL = 100Ω, CL = 5 pF, Worst Case Pattern (Figures 1, 3 ), TA = −40˚C to +85˚C f = 32.5 MHz 31 45 mA f = 37.5 MHz 32 50 mA f = 65 MHz 42 55 mA RL = 100Ω, CL = 5 pF, 16 Grayscale Pattern (Figures 2, 3 ), TA = −40˚C to +85˚C f = 32.5 MHz 23 35 mA f = 37.5 MHz 28 40 mA f = 65 MHz 31 45 mA 3 www.national.com Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units 10 55 µA 65 mA TRANSMITTER SUPPLY CURRENT ICCTZ Transmitter Supply Current PWR DWN = Low Power Down Driver Outputs in TRI-STATE ® under Power Down Mode RECEIVER SUPPLY CURRENT ICCRW ICCRG ICCRZ Receiver Supply Current, Worst Case Receiver Supply Current, 16 Grayscale CL = 8 pF, Worst Case Pattern (Figures 1, 4 ), TA = −40˚C to +85˚C f = 32.5 MHz 49 f = 37.5 MHz 53 70 mA f = 65 MHz 78 105 mA CL = 8 pF, 16 Grayscale Pattern (Figures 2, 4 ), TA = −40˚C to +85˚C f = 32.5 MHz 28 45 mA f = 37.5 MHz 30 47 mA f = 65 MHz 43 60 mA 10 55 µA Receiver Supply Current PWR DWN = Low Power Down Receiver Outputs Stay Low during Power Down Mode Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VCC = 3.3V and T A = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆V OD). Note 4: VOS previously referred as VCM. www.national.com 4 Transmitter Switching Characteristics Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified Typ Max Units LLHT Symbol LVDS Low-to-High Transition Time (Figure 3 ) Parameter 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time (Figure 3 ) 0.75 1.5 ns TCIT TxCLK IN Transition Time (Figure 5 ) 5 ns TCCS TxOUT Channel-to-Channel Skew (Figure 6 ) TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 17 ) TPPos1 TPPos2 Min 250 f = 65 MHz ps −0.4 0 0.3 ns Transmitter Output Pulse Position for Bit 1 1.8 2.2 2.5 ns Transmitter Output Pulse Position for Bit 2 4.0 4.4 4.7 ns TPPos3 Transmitter Output Pulse Position for Bit 3 6.2 6.6 6.9 ns TPPos4 Transmitter Output Pulse Position for Bit 4 8.4 8.8 9.1 ns TPPos5 Transmitter Output Pulse Position for Bit 5 10.6 11.0 11.3 ns TPPos6 Transmitter Output Pulse Position for Bit 6 12.8 13.2 13.5 ns TCIP TxCLK IN Period (Figure 7) 15 T 50 ns TCIH TxCLK IN High Time (Figure 7) 0.35T 0.5T 0.65T ns 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time (Figure 7) TSTC TxIN Setup to TxCLK IN (Figure 7 ) THTC TxIN Hold to TxCLK IN (Figure 7 ) TCCD TxCLK IN to TxCLK OUT Delay 25˚C, VCC = 3.3V (Figure 9 ) 5.5 ns TPLLS Transmitter Phase Lock Loop Set (Figure 11 ) 10 ms TPDD Transmitter Power Down Delay (Figure 15 ) 100 ns f = 65 MHz 5 2.5 ns 0 ns 3.0 3.7 www.national.com Receiver Switching Characteristics Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified Typ Max Units CLHT Symbol CMOS/TTL Low-to-High Transition Time (Figure 4 ) Parameter Min 2.2 5.0 ns CHLT CMOS/TTL High-to-Low Transition Time (Figure 4 ) 2.2 5.0 ns RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 18 ) 0.7 1.1 1.4 ns RSPos1 Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6 ns RSPos2 Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8 ns RSPos3 Receiver Input Strobe Position for Bit 3 7.3 7.7 8.0 ns RSPos4 Receiver Input Strobe Position for Bit 4 9.5 9.9 10.2 ns RSPos5 Receiver Input Strobe Position for Bit 5 11.7 12.1 12.4 ns RSPos6 Receiver Input Strobe Position for Bit 6 13.9 14.3 14.6 ns RSKM RxIN Skew Margin (Note 5) (Figure 19 ) RCOP RxCLK OUT Period (Figure 8) T 50 ns RCOH RxCLK OUT High Time (Figure 8 ) f = 65 MHz 7.3 8.6 ns RCOL RxCLK OUT Low Time (Figure 8) f = 65 MHz 3.45 4.9 ns RSRC RxOUT Setup to RxCLK OUT (Figure 8 ) f = 65 MHz 2.5 6.9 ns RHRC RxOUT Hold to RxCLK OUT (Figure 8 ) f = 65 MHz 2.5 5.7 RCCD RxCLK IN to RxCLK OUT Delay 25˚C, VCC = 3.3V (Figure 10 ) 5.0 7.1 RPLLS RPDD f = 65 MHz f = 65 MHz 400 15 ps ns 9.0 ns Receiver Phase Lock Loop Set (Figure 12 ) 10 ms Receiver Power Down Delay (Figure 16 ) 1 µs Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps). AC Timing Diagrams DS012886-2 FIGURE 1. “Worst Case” Test Pattern www.national.com 6 AC Timing Diagrams (Continued) DS012886-3 FIGURE 2. “16 Grayscale” Test Pattern (Notes 6, 7, 8, 9) Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 7: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 8: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 9: Recommended pin to signal mapping. Customer may choose to define differently. DS012886-15 FIGURE 3. DS90C363 (Transmitter) LVDS Output Load and Transition Times DS012886-4 FIGURE 4. DS90CF364 (Receiver) CMOS/TTL Output Load and Transition Times DS012886-16 FIGURE 5. DS90C363 (Transmitter) Input Clock Transition Time 7 www.national.com AC Timing Diagrams (Continued) DS012886-17 Measurements at Vdiff=0V TCCS measured between earliest and latest LVDS edges TxCLK Differential Low → High Edge FIGURE 6. DS90C363 (Transmitter) Channel-to-Channel Skew DS012886-18 FIGURE 7. DS90C363 (Transmitter) Setup/Hold and High/Low Times DS012886-5 FIGURE 8. DS90CF364 (Receiver) Setup/Hold and High/Low Times DS012886-19 FIGURE 9. DS90C363 (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe) www.national.com 8 AC Timing Diagrams (Continued) DS012886-6 FIGURE 10. DS90CF364 (Receiver) Clock In to Clock Out Delay DS012886-20 FIGURE 11. DS90C363 (Transmitter) Phase Lock Loop Set Time DS012886-7 FIGURE 12. DS90CF364 (Receiver) Phase Lock Loop Set Time 9 www.national.com AC Timing Diagrams (Continued) DS012886-9 FIGURE 13. Seven Bits of LVDS in One Clock Cycle DS012886-10 FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs DS012886-21 FIGURE 15. Transmitter Power Down Delay DS012886-8 FIGURE 16. Receiver Power Down Delay www.national.com 10 AC Timing Diagrams (Continued) DS012886-22 FIGURE 17. Transmitter LVDS Output Pulse Position Measurement 11 www.national.com AC Timing Diagrams (Continued) DS012886-25 FIGURE 18. Receiver LVDS Input Strobe Position www.national.com 12 AC Timing Diagrams (Continued) DS012886-11 C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11) Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 10: Cycle-to-cycle jitter is less than 250 ps at 65 MHz. Note 11: ISI is dependent on interconnect length; may be zero. FIGURE 19. Receiver LVDS Input Skew Margin DS90C363 Pin Description — FPD Link Transmitter I/O No. TxIN Pin Name I 21 Description TxOUT+ O 3 Positive LVDS differentiaI data output. TxOUT− O 3 Negative LVDS differential data output. FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN. R_FB I 1 Programmable strobe select. RTxCLK OUT+ O 1 Positive LVDS differential clock output. TxCLK OUT− O 1 Negative LVDS differential clock output. PWR DWN I 1 TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at power down. TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). V CC I 3 Power supply pins for TTL inputs. GND I 4 Ground pins for TTL inputs. PLL V CC I 1 Power supply pin for PLL. PLL GND I 2 Ground pins for PLL. LVDS V CC I 1 Power supply pin for LVDS outputs. LVDS GND I 3 Ground pins for LVDS outputs. 13 www.national.com DS90CF364 Pin Description — FPD Link Receiver Pin Name RxIN+ I/O No. I 3 Description Positive LVDS differentiaI data inputs. RxIN− I 3 RxOUT O 21 Negative LVDS differential data inputs. RxCLK IN+ I 1 RxCLK IN− I 1 Negative LVDS differential clock input. FPSHIFT OUT O 1 TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT. TTL level input. When asserted (low input) the receiver outputs are low. TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable). Positive LVDS differential clock input. PWR DWN I 1 V CC I 4 Power supply pins for TTL outputs. GND I 5 Ground pins for TTL outputs. PLL V CC I 1 Power supply for PLL. PLL GND I 2 Ground pin for PLL. LVDS V CC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. Applications Information The DS90C363 and DS90CF364 are backward compatible with the existing 5V FPD Link transmitter/receiver pair (DS90CF563 and DS90CF564). To upgrade from a 5V to a 3.3V system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL V CC of both the transmitter and receiver devices. This change may enable the removal of a 5V supply from the system, and power may be supplied from an existing 3V power source. 2. The DS90C363 (transmitter) incorporates a rise/fall strobe select pin. This select function is on pin 14, formerly a VCC connection on the 5V products. When the rise/fall strobe select pin is connected to V CC, the part is configured with a rising edge strobe. In a system currently using a 5V rising edge strobe transmitter (DS90CR563), no layout changes are required to accommodate the new rise/fall select pin on the 3.3V transmitter. The VCC signal may remain at pin 14, and the device will be configured with a rising edge strobe. When converting from a 5V falling edge transmitter (DS90CF563) to the 3V transmitter a minimal board layout change is necessary. The 3.3V transmitter will not be configured with a falling edge strobe if VCC remains connected to the select pin. To guarantee the 3.3V transmitter functions with a falling edge strobe pin 14 should be connected to ground OR left unconnected. When not connected (left open) and internal pull-down resistor ties pin 14 to ground, thus configuring the transmitter with a falling edge strobe. 3. The DS90C363 transmitter input and control inputs accept 3.3V TTL/CMOS levels. They are not 5V tolerant. www.national.com 14 Pin Diagram DS90C363 DS90CF364 DS012886-13 DS012886-23 TABLE 1. Programmable Transmitter Pin Condition Strobe Status R_FB R_FB = VCC Rising edge strobe R_FB R_FB = GND Falling edge strobe 15 www.national.com DS90C363/DS90CF364 +3.3V Programmable LVDS 18-Bit-Color Flat Panel Display (FPD) Link — 65 MHz Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Molded Thin Shrink Small Outline Package, JEDEC Dimensions show in millimeters Order Number DS90C363MTD and DS90CF364MTD NS Package Number MTD48 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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