(607 M21L216128A SRAM 128 K x 16 SRAM HIGH SPEED CMOS SRAM FEATURES ORDERING INFORMATION Fast access times : 10, 12, and 15ns Fast OE access times : 5, 6, and 7ns Single +3.3V ± 0.3V power supply Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Center power and ground pins for greater noise immunity Easy memory expansive with CE and OE options 44-pin 400mil SOJ 44-pin 400mil TSOP (TypeII) PRODUCT NO. Acess Time (ns) M21L216128A-10J Automatic CE power down M21L216128A-10T +LJKSHUIRUPDQFH ORZSRZHU FRQVXPSWLRQ &026 M21L216128A-12J WULSOHSRO\ GRXEOHPHWDO SURFHVV M21L216128A-12T M21L216128A-15J M21L216128A-15T 10 PACKING TYPE SOJ TSOP 12 15 SOJ TSOP SOJ TSOP GENERAL DESCRIPTION The M21L216128A is a high speed, low power asynchronous SRAM containing 2,097,152 bits and organized as 131,072 by 16 bits, it is produced by high performance CMOS process. This device offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers chip enable ( CE ), separate byte enable controls ( LB and HE ) and output enable ( OE ) with this organization. PIN ASSIGNMENT SOJ Top View A4 A3 A2 A1 A0 CE D Q1 D Q2 D Q3 DQ4 VCC GND DQ5 DQ6 DQ7 DQ8 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Elite Semiconduture Memory Technology Inc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 TSOP (TypeII) Top View A5 A4 A6 A3 A7 A2 OE A1 HB A0 LB CE DQ 16 D Q1 DQ 15 D Q2 DQ 14 D Q3 DQ 13 D Q4 GND VC C VC C GND DQ 12 DQ5 DQ 11 DQ6 DQ 10 DQ7 D Q9 DQ8 NC WE A8 A1 6 A9 A1 5 A10 A1 4 A11 A1 3 NC A1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE HB LB DQ16 DQ15 DQ14 DQ13 GND VCC DQ12 DQ11 DQ10 D Q9 NC A8 A9 A1 0 A1 1 NC Publication Date : Sep. 2000 Revision : 1.0 1/14 (607 M21L216128A Block Diagram éÖÖ Ôà Úá× 512 X 4096 ×ØÖâ×Øå MEMORY ARRAY ÔÄÉ DQ9 ×äÄ Öâßèàá ÜÂâ Üáãèç Üáãèç ×ÔçÔ ×ÔçÔ ÖÜåÖèÜç ÖÜåÖèÜç ×äÄÉ ×äË ÖØ ßÕ Öâáçåâß ÛÕ ÖÜåÖèÜç âØ êØ Pin Descriptions Pin No. Symbol Description 1 - 5, 18 - 22, 24-27, 42 - 44 A0 - A16 6 CE 7 - 10, 13 - 16, 29 - 32, 35 - 38 DQ1 - DQ16 17 WE Write Enable Input 39 LB Lower Byte Enable Input (DQ1 to DQ8) 40 HB Higher Byte Enable Input (DQ9 to DQ16) 41 OE Output Enable Input 11, 33 VCC Power 12, 34 GND Ground 23, 28 NC Address Inputs Chip Enable Input Data Inputs/Outputs No Connection Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 2/14 (607 M21L216128A ABSOLUTE MAXIMUM RATINGS * Voltage on VCC Supply Relative to Vss … ……-0.5V to +4.6V VIN …………………………………………..….-0.5V to VCC+1.0V Operating Temperature, Topr ………………….. 0 °C to +70 °C Storage Temperature (plastic) ……………….-55 °C to +125 °C Junction Temperature ……………………………………+125 °C Power Dissipation …..…………………………………….…1.0W *Stresses greater than those listed under Absolute Maximum. Ratings may permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Short Circuit Output Current ………………………………50mA DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATIONS (All Temperature Ranges ; VCC = 3.3V ± 0.3V unless otherwise noted) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage VIH 2.2 VCC+0.5 V 1,2 Input Low (Logic 0) Voltage VII -0.5 0.8 V 1,2 Input Leakage Current 0V ≤ VIN ≤ VCC ILI -10 10 µA Output Leakage Current Output(s) disable 0V ≤ VOUT ≤ VCC ILO -5 5 µA Output High Voltage IOH = -4.0 mA VOH 2.4 Output Low Voltage IOL = 8.0 mA VOL Supply Voltage VCC DESCRIPTION CONDITIONS 3.0 V 1 0.4 V 1 3.6 V 1 MAX SYMBOL -10 -12 -15 UNITS NOTES 3 Power Supply Current : Operating Device selected; CE ≤ VIL; VCC=MAX; f=fMAX ; outputs open ICC 190 160 130 mA TTL Standby CE ≥ VIH; VCC=MAX; f=fMAX ISB1 35 30 25 mA CMOS Standby CE1 ≥ VCC-0.2; VCC = MAX; all other inputs ≤ GND +0.2 or ≥ VCC -0.2; all inputs static ; f=0 ISB2 10 10 10 mA CAPACITANCE DESCRIPTION Input Capacitance CONDITIONS SYMBOL MAX TA= 25°C ; f=1 MHz CI 6 pF 4 VCC=3.3V CI/O 8 pF 4 Input/Output Capacitance(DQ) Elite Semiconduture Memory Technology Inc UNITS NOTES Publication Date : Sep. 2000 Revision : 1.0 3/14 (607 M21L216128A AC ELECTRICAL CHARACTERISTICS (Note 5)(All Temperature Ranges; VCC =3.3V ± 0.3V) DESCRIPTION SYMBOL -10 MIN -12 MAX MIN -15 MAX MIN MAX UNIT Notes Read Cycle Read Cycle Time tRC 10 12 Access access time tAA 10 12 15 ns Chip Enable access time tACE 10 12 15 ns Output hold from address change tOH 3 4 4 ns Chip Enable to output in Low-Z tCLZ 3 4 4 ns 4,7 Chip disable to output in High-Z tCHZ 5 6 7 ns 4,6,7 Output Enable access time tOE 5 6 7 ns Output Enable to output in Low-Z tOLZ Output Disable to output in High-Z tOHZ 5 6 7 ns Byte Enable access time tBE 6 7 8 ns Byte Enable to output in Low-Z tBLZ Byte disable to output in High-Z tBHZ 0 15 0 0 0 0 5 ns ns 0 6 7 4,6 ns 4,7 ns 4,6,7 Write Cycle Write cycle time tWC 10 12 15 ns Chip Enable to end of write tCW 8 8 9 ns Address valid to end of write, with OE HIGH tAW 8 8 9 ns Address setup time tAS 0 0 0 ns Address hold from end of write tWR 0 0 0 ns Write pulse width tWP2 10 10 11 ns Write pulse width, with OE HIGH tWP1 8 8 9 ns Data setup time tDW 5 6 7 ns Data hold time tDH 0 0 0 ns Write disable to output in Low-Z tOW 3 4 5 ns 4,7 Byte Enable to output in High-Z tWHZ ns 4,6,7 Byte Enable to end of write tBW Elite Semiconduture Memory Technology Inc 5 8 6 8 7 9 ns Publication Date : Sep. 2000 Revision : 1.0 4/14 (607 M21L216128A TRUTH TABLE MODE CE WE OE LE HE DQ1-DQ8 DQ9-DQ16 POWER LOW BYTE READ (DQ1-DQ8) L H L L H Q HIGH-Z ACTIVE HIGH BYTE READ (DQ9-DQ16) L H L H L HIGH-Z Q ACTIVE WORD READ (DQ1-DQ16) L H L L L Q Q ACTIVE LOW BYTE WRITE (DQ1-DQ8) L L X L H D HIGH-Z ACTIVE HIGH BYTE WRITE (DQ9-DQ16) L L X H L HIGH-Z D ACTIVE WORD WRITE (DQ1-DQ16) L L X L L D D ACTIVE L X X H H HIGH-Z HIGH-Z ACTIVE L H H X X HIGH-Z HIGH-Z ACTIVE H X X X X HIGH-Z HIGH-Z STANBY OUTPUT DISABLE STANDBY AC TEST CONDITIONS Input plus levels 0V to 3.0V Input rise and fail times 1.5ns Input timing reference levels 1.5V Output reference levels 1.5V Output load See Figures 1 and 2 3.3V DQ 317 è Z0 =50 50 è è DQ 30pF è 5pF 351 Vt=1.5V Fig.1 OUTPUT LOAD EQUIVALENT Elite Semiconduture Memory Technology Inc Fig.2 OUTPUT LOAD EQUIVALENT Publication Date : Sep. 2000 Revision : 1.0 5/14 (607 M21L216128A NOTES 1. All voltages referenced to GND (VSS). 2. Overshoot : VIH ≤ +6.0V for t ≤ tRC /2. Undershoot : VIL ≤ -2.0V for t ≤ tRC /2. 3. ICC is given without output current. ICC increases with greater output loading and faster cycle times. 4. This parameter is sampled. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. Output loading is specified with CL=5pF as in Fig.2. Transition is measured ± 500mV from steady static voltage. 7. At any give temperature and voltage conditions, tCHZ is less than tCLZ and tWHZ is less than tOW 8. WE is High for Read cycle. 9. Device is continuously selected. Chip enable and output enables are held in their active state. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC=Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a Write cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 6/14 (607 M21L216128A Timing Waveforms Read Cycle 1(8, 9) tRC Addr ess tAA tCH Dout Read Cycle 2(7, 8, 9, 10) tRC Addr es s tAA CE tACE tCHZ tCLZ tBE HB,LB tBHZ tBLZ OE tOE tOHZ tOLZ Dout : DON'T CARE : UNDEFINED Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 7/14 (607 M21L216128A Timing Waveforms (continued) Write Cycle 1(7, 12, 13) (Write Enable Controlled with Output Enable OE active LOW) tWC Address tAW tWR tCW CE tBW HB,LB tA S tWP2 WE tDW tDH Di n tWHZ tOW Dout DON'T CARE U NDEFINED Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 8/14 (607 M21L216128A Timing Waveforms (continued) Write Cycle 2(12, 13) (Write Enable Controlled with Output Enable OE active HIGH) tWC Address tAW tWR tCW CE tBW HB,LB tA S tWP1 WE tDW tDH Di n Dout HIG H-Z DON'T CARE U NDEFINED Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 9/14 (607 M21L216128A Timing Waveforms (continued) Write Cycle 3(12, 13) (Chip Enable Controlled) tW C A d d res s tWR tAW tAS tCW CE tBW HB,LB tWP1 WE tDW tDH Din Dout HIGH -Z DON'T CARE UN DEFINED Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 10/14 (607 M21L216128A Timing Waveforms (continued) Write Cycle 4(12, 13) (Byte Enable Controlled) tW C A d d res s tAW tCW CE tAS tBW tWR HB,LB tWP1 WE tDW tDH Din Dout HIGH -Z DON'T CARE UN DEFINED Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 11/14 (607 PACKING 44-LEAD M21L216128A DIMENSIONS SOJ SYMBOL SRAM(400mil) DIMENSION ( INCH ) DIMENSION ( MM ) MIN NOM MAX MIN NOM MAX A 0.128 0.138 0.148 3.25 3.51 3.76 A1 0.082 - - 2.08 - - A2 0.025 - - 0.60 - - b 0.015 - 0.020 0.38 - 0.51 b1 0.015 - 0.018 0.38 - 0.46 c 0.007 - 0.013 0.18 - 0.21 c1 0.007 0.008 0.011 0.18 0.20 0.28 D 1.120 1.125 1.130 28.45 28.58 28.70 E 0.435 0.440 0.445 11.05 11.18 11.30 E1 0.394 0.400 0.405 10.01 10.16 10.29 10º 0º ð e 0º 0.050BSC Elite Semiconduture Memory Technology Inc 10º 1.27 BSC Publication Date : Sep. 2000 Revision : 1.0 12/14 (607 PACKING 44-LEAD Symbol A A1 A2 B B1 C C1 D ZD E E1 L L1 e θ M21L216128A DIMENSIONS TSOP(II) SRAM(400mil) Dimension in mm Min Norm Max 1.20 0.05 0.15 0.95 1.00 1.05 0.30 0.45 0.30 0.35 0.40 0.12 0.21 0.10 0.16 18.28 18.41 18.54 0.805 REF 11.56 11.76 11.96 10.03 10.16 10.29 0.40 0.59 0.69 0.80 REF 0.80 BSC ° ° Elite Semiconduture Memory Technology Inc Dimension in inch Min Norm Max 0.047 0.002 0.006 0.037 0.039 0.042 0.012 0.018 0.012 0.014 0.016 0.005 0.008 0.004 0.006 0.720 0.725 0.730 0.0317 REF 0.455 0.463 0.471 0.395 0.400 0.4 0.016 0.023 0.027 0.031 REF 0.0315 BSC ° ° Publication Date : Sep. 2000 Revision : 1.0 13/14 (607 M21L216128A ,PSRUWDQW 1RWLFH $OO ULJKWV UHVHUYHG 1R SDUW RI WKLV GRFXPHQW PD\ EH UHSURGXFHG RU GXSOLFDWHG LQ DQ\ IRUP RU E\ DQ\ PHDQV ZLWKRXW WKH SULRU SHUPLVVLRQ RI 7KH FRQWHQWV FRQWDLQHG SXEOLFDWLRQ (607 UHVHUYHV ULJKW WKH LQ WKLV DVVX PHV WR FKDQJH (607 GRFXPHQW QR WKH DUH EHOLHYHG UHVSRQVL ELOLW\ SURG XFWV RU IRU WR DQ\ EH HUURU VSHFLILFDWLRQ LQ DFFXUDWH LQ WKLV WKLV DW WKH WL PH GRFX PHQW GRFX PHQW RI DQG ZLWKRXW QRWLFH 7KH LQIRUPDWLRQ DSSOLFDWLRQ RI LQIULQJHPHQW SDUWLHV RWKHUZLVH LV RXU RI ZKLFK FRQWDLQHG SURGXFWV SDWHQWV PD\ KHUHLQ 1R SUHVHQWHG IUR P XQGHU LWV DQ\ RQO\ UHVSRQVL ELOLW\ FRS\ULJKWV UHVXOW JUDQWHG LV RU RWKHU XVH 1R SDWHQWV DV LV D JXLGH DVVX PHG LQWHO OHFWXDO OLFHQVH FRS\ ULJKWV H[DPSOHV E\ (607 SURSHUW\ HLWKHU RU RU RWKHU IRU ULJKWV H[SUHVV IRU RI WKH DQ\ WKLUG LPSOLHG LQWHOOHFWXDO RU SUR SHUW\ ULJKWV RI (607 RU RWKHUV $Q\ VHPLFRQG XFWRU GHYLFHV PD\ KDYH LQKHUHQWO\ D FHUWDLQ UDWH RI IDLOXUH 7R P LQL P L]H ULVNV DVVRFLDWHG ZLWK FXVWR PHU V DSSOLFDWLRQ DGHTXDWH GHVLJQ DQG RSHUDWLQJ VDIHJXDUGV DJDLQVW LQMXU\ GDPDJH RU ORVV IURP VXFK IDLOXUH VKRXOG EH SURY LGHG E\ WKH FXVWRPHU ZKHQ PDNLQJ DSSO LFDWLRQ GHVLJ QV (607 V OL PLWHG GLUHFWO\ SURGXFWV WR OLIH DIIHFW DUH QRW VXSSRUW KX PDQ DXWKRUL]HG GHYLFHV OLYHV RU RU IRU XVH V\VWHP FDXVH LQ FULWLFDO ZKHUH SK\VLFDO DSSOLFD WLRQV I DLOXUH LQMXU\ RU RU VXFK DEQRUPDO SURSHUW\ DV EXW RSHUDWLRQ GDPDJH ,I QRW PD\ SURGXFWV GHVFULEHG KHUH DUH WR EH XVHG IRU VXFK NLQGV RI DSSOLFDWLRQ SXUFKDVHU PXVW GR LWV RZQ TXDOLW\ DVVXUDQFH WHVWLQJ DSSURSULDWH WR VXFK DSSOLFDWLRQV Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 14/14