33 CY7C1041AV33/ GVT73256A16 PRELIMINARY 256K x 16 Static RAM Features • • • • • • • • • • • Functional Description Fast access times: 10, 12 ns Fast OE access times: 5, 6, and 7 ns Single +3.3V ±0.3V power supply Fully static—no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Center power and ground pins for greater noise immunity Easy memory expansion with CE and OE options Automatic CE power-down High-performance, low power consumption, CMOS double-poly, double-metal process Packaged in 44-pin, 400-mil SOJ and 44-pin, 400-mil TSOP The CY7C1049AV33\GVT73512A8 is organized as a 262,144 x 16 SRAM using a four-transistor memory cell with a high-performance, silicon gate, low-power CMOS process. Cypress SRAMs are fabricated using double-layer polysilicon, double-layer metal technology. This device offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers Chip Enable (CE), separate Byte Enable controls (BLE and BHE) and Output Enable (OE) with this organization. The device offers a low-power standby mode when chip is not selected. This allows system designers to meet low standby power requirements. Functional Block Diagram Pin Configuration VCC SOJ/TSOP II Top View BLE# VSS A0 A1 A2 A3 A4 CE DQ1 DQ2 DQ3 DQ4 VCC VSS DQ5 DQ6 DQ7 DQ8 WE A5 A6 A7 A8 A9 DQ1 MEMORY ARRAY 512 ROWS X 256 X 16 COLUMNS I/O CONTROL ROW DECODER ADDRESS BUFFER A0 DQ8 DQ9 DQ16 A16 COLUMN DECODER POWER DOWN CE# BHE# WE# OE# 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 37 9 10 11 12 36 13 32 31 30 29 28 27 35 34 33 14 15 16 17 18 19 20 21 22 26 25 24 23 A17 A16 A15 OE BHE BLE DQ16 DQ15 DQ14 DQ13 VSS VCC DQ12 DQ11 DQ10 DQ9 NC A14 A13 A12 A11 A10 Selection Guide CY7C1049AV33-10/ GVT73512A8-10 CY7C1049AV33-12/ GVT73512A8-12 10 12 240 210 10 10 3.0 3.0 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Com’l/Ind’l Com’l Cypress Semiconductor Corporation • 3901 North First Street L • San Jose • CA 95134 • 408-943-2600 June 15, 2000 CY7C1041AV33/ GVT73256A16 PRELIMINARY Truth Table Mode Low Byte Read (DQ1–DQ8) High Byte Read (DQ 9–DQ16) Word Read (DQ1–DQ 16) Low Byte Write (DQ1–DQ8) High Byte Write (DQ 9–DQ16) Word Write (DQ1–DQ16) Output Disable Standby CE WE OE BLE BHE DQ1–D8 DQ 9–D16 POWER L L L L L L L L H H H H L L L X H X L L L X X X X H X L H L L H L H X X H L L H L L H X X Q High-Z Q D High-Z D High-Z High-Z High-Z High-Z Q Q High-Z D D High-Z High-Z High-Z Active Active Active Active Active Active Active Active Standby Pin Descriptions SOJ & TSOP Pin Numbers Pin Name Type Description 1, 2, 3, 4, 5, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 42, 43, 44 A0–A17 Input Addresses Inputs: These inputs determine which cell is addressed. 17 WE Input Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE is LOW for a WRITE cycle and HIGH for a READ cycle. 6 CE Input Chip Enable: This active LOW input is used to enable the device. When CE is LOW, the chip is selected. When CE is HIGH, the chip is disabled and automatically goes into standby power mode. 39, 40 BLE, BHE Input Byte Enable: These active LOW inputs allow individual bytes to be written or read. When BLE is LOW, the data is written to or read from the lower byte (DQ1–DQ8). When BHE is LOW, the data is written to or read from the higher byte (DQ 9–DQ16). 41 OE Input Output Enable: This active LOW input enables the output drivers. 7, 8, 9, 10, 13, 14, 15, 16, 29, 30, 31, 32, 35, 36, 37, 38 DQ 1–DQ16 Input/ Output SRAM Data I/O: Data inputs and data outputs. Lower byte is DQ1–DQ8 and upper byte is DQ9–DQ16. 11, 33 VCC Supply Power Supply: 3.3V ±0.3V%. 12, 34 VSS Supply Ground. Power Dissipation ......................................................... 1.0W Maximum Ratings Short Circuit Output Current ....................................... 50 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V VIN ...........................................................–0.5V to VCC+0.5V Storage Temperature (plastic)........................–55°C to +125° Range Commercial Junction Temperature ..................................................+125° Industrial Note: 1. TA is the “Instant On” case temperature. 2 Ambient Temperature[1] VCC 0°C to +70°C 3.3V ± 0.3V –40°C to +85°C CY7C1041AV33/ GVT73256A16 PRELIMINARY Electrical Characteristics Over the Operating Range Parameter Description Conditions Input High (Logic 1) Voltage VIH [2, 3] [2, 3] Min. Max. Unit 2.2 VCC+0.5 V –0.5 0.8 V VIl Input Low (Logic 0) Voltage ILI Input Leakage Current 0V < VIN < VCC –5 5 µA ILO Output Leakage Current Output(s) disabled, 0V < VOUT < VCC –5 5 µA [2] IOH = –4.0 mA 2.4 [2] IOL = 8.0 mA VOH Output High Voltage Output Low Voltage VOL VCC Supply Voltage Parameter ICC ISB1 [2] 3.0 Description Conditions TTL Standby CMOS Standby[5] V 3.6 V Typ. -10 -12 Unit std. 90 240 210 mA 240 210 low CE > V IH; VCC = Max.; f = fMAX std. 25 low ISB2 0.4 Power Power Supply Device selected; CE < VIL; VCC = Max.; Current: Operating[4, 5] f = fMAX; outputs open [5] V CE1 > VCC – 0.2; VCC = Max.; all other inputs < VSS + 0.2 or > VCC – 0.2; all inputs static; f = 0 std. 0.1 low 70 60 70 60 mA 10 10 3.0 3.0 mA Capacitance[6] Parameter Description CI Input Capacitance CI/O Input/Output Capacitance (DQ) Test Conditions Max. Unit 6 pF 8 pF TA = 25°C, f = 1 MHz, VCC = 3.3V Note: 2. All voltages referenced to VSS (GND). 3. Overshoot: VIH < +6.0V for t < tRC /2. Undershoot: VIL < –2.0V for t < tRC /2 4. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 5. Typical values are measured at 3.3V, 25°C, and 20 ns cycle time. 6. This parameter is sampled. AC Test Loads and Waveforms ALL INPUT PULSES 3.3V 3.3V 90% DQ Z 0 = 50 Ω 317Ω 50Ω Vt = 1.5V (a) 30 pF 10% 0V DQ 351Ω 5 pF (b) 3 Rise Time: 1V/ns 90% 10% ≤1.5 ns Fall Time: 1V/ns CY7C1041AV33/ GVT73256A16 PRELIMINARY Switching Characteristics[5] Over the Operating Range 7C1041AV33-10/ GVT73256A16-10 Parameter Description Min. Max. 7C1041AV33-12/ GVT73256A16-12 Min. Max. Unit READ CYCLE tRC READ Cycle Time 10 tAA Address Access Time tACE Chip Enable Access Time tOH Output Hold from Address Change 102 ns 12 ns 10 [6, 7] tHZCE Chip Disable to Output in High-Z Output Enable Access Time tLZOE Output Enable to Output in Low-Z 3 ns 3 3 ns 5 6 ns 5 6 ns 0 [6, 8] tHZOE Output Enable to Output in High-Z tABE Byte Enable Access Time tLZBE Byte Enable to Output in Low-Z[6, 7] Byte Disable to Output in High-Z 3 [6, 7, 8] tAOE tHZBE ns 10 Chip Enable to Output in Low-Z tLZCE 12 0 5 6 ns 5 6 ns 0 [6, 7, 8] Chip Enable to Power-up Time tPD Chip Disable to Power-down Time[6] 0 ns 5 [6] tPU ns 0 6 ns 12 ns 0 ns 10 WRITE CYCLE tWC WRITE Cycle Time 10 12 ns tCW Chip Enable to End of Write 8 8 ns tAW Address Valid to End of Write, with OE HIGH 8 8 ns tAS Address Set-up Time 0 0 ns tAH Address Hold from End of Write 0 0 ns tWP2 WRITE Pulse Width 10 10 ns tWP1 WRITE Pulse Width, with OE HIGH 8 8 ns tDS Data Set-up Time 5 6 ns tDH Data Hold Time 0 0 ns 3 4 ns Write Disable to Output in Low-Z [6, 7] tHZWE Write Enable to Output in High-Z [6, 7, 8] tBW Byte Enable to End of Write tLZWE 5 8 6 ns 8 ns Data Retention Characteristics Over the Operating Range (For L version only) Parameter VDR ICCDR Conditions VCC for Data Retention [9] tCDR[6] tR Description [6, 10] Data Retention Current Min. Typ. Max. 2.0 VCC = 2V CE > VCC – 0.2V; all other inputs < VSS + 0.2 or VCC = 3V >VCC – 0.2; all inputs static; f = 0 Chip Deselect to Data Retention Time Operation Recovery Time Notes: 7. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE. 8. Output loading is specified with CL=5 pF as in AC Test Loads. Transition is measured ±500mV from steady state voltage. 9. Capacitance derating applies to capacitance different from the load capacitance shown in AC Test Loads. 10. t RC = Read Cycle Time. 4 Unit V 0.2 1.6 mA 0.3 2.4 mA 0 ns tRC ns CY7C1041AV33/ GVT73256A16 PRELIMINARY Low VCC Data Retention Waveform DATA RETENTION MODE VCC tC D R 3.0V VDR 3.0V tR C CE# V IH V IL Switching Waveforms Read Cycle No. 1[11, 12] t RC VALID ADDR tAA tOH Q PREVIOUS DATA VALID DATA VALID Read Cycle No. 2[7, 11, 13, 14] t RC CE# tHZCE tABE BLE# BHE# t t AOE HZBE tLZOE OE# tLZBE tACE tHZOE tLZCE Q HIGH Z DATA VALID DON'T CARE UNDEFINED Notes: 11. WE is HIGH for read cycle. 12. Device is continuously selected. Chip Enable and Output Enables are held in their active state. 13. Address valid prior to or coincident with latest occurring chip enable. 14. Chip Enable and Write Enable can initiate and terminate a write cycle. 5 CY7C1041AV33/ GVT73256A16 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled with OE Active LOW)[9, 7, 14] t WC ADDR tA W t tA H CW CE# tB W BLE# BHE# t tW P 2 AS WE# t D t DS DH DATA VALID tH Z W E tL Z W E Q HIGH Z Write Cycle No. 2 (WE Controlled with OE Inactive HIGH)[9, 14] tW C ADDR tA W tA H tC W CE# tB W BLE# BHE# tA S tW P 1 WE# tD S D Q DATA VALID HIGH Z 6 tD H CY7C1041AV33/ GVT73256A16 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 3 (CE Controlled)[9, 14] t WC ADDR t t t AW t AS AH CW CE# t BW BLE# BHE# t WP1 WE# t D DS t DH DATA VALID Q HIGH Z DON'T CARE Write Cycle No. 4 (Byte Enable Controlled)[9, 14] t WC ADDR t t BLE# BHE# t AW t AS t AH BW CW CE# t WP1 WE# t D Q DS t DH DATA VALID HIGH Z DON'T CARE 7 CY7C1041AV33/ GVT73256A16 PRELIMINARY Ordering Information Speed (ns) 10 Ordering Code CY7C1041AV33-10VC Package Name Package Type V36 36-Lead (400-Mil) Molded SOJ Z44 44-Pin TSOP II V36 36-Lead (400-Mil) Molded SOJ Z44 44-Pin TSOP II V36 36-Lead (400-Mil) Molded SOJ Z44 44-Pin TSOP II V36 36-Lead (400-Mil) Molded SOJ Z44 44-Pin TSOP II Operating Range Commercial GVT73256A16J-10C CY7C1041AV33-10ZC GVT73256A16TS-10C CY7C1041AV33L-10VC GVT73256A16J-10LC CY7C1041AV33L-10ZC GVT73256A16TS-10LC 12 CY7C1041AV33-12VC Commercial GVT73256A16J-12C CY7C1041AV33-12ZC GVT73256A16TS-12C CY7C1041AV33L-12VC GVT73256A16J-12LC CY7C1041AV33L-12ZC GVT73256A16TS-12LC Document #: 38–00997-** Package Diagrams 44-Lead (400-Mil) Molded SOJ V34 51-85082-B 8 PRELIMINARY CY7C1041AV33/ GVT73256A16 Package Diagrams (continued) 44-Pin TSOP II Z44 51-85087-A © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.