SPECIFICATION for MRD520A Dual Channel F2F Decoder IC Uniform Industrial Corp. Taiwan, Factory 1st FL., No.1, Lane 15, Chih Chiang Street, Tu Cheng City, Taipei Hsien, Taiwan, R.O.C. USA, Office 46750 Fremont Blvd Suite 104 Fremont, CA 94538 USA Tel Fax E-mail Tel Fax E-mail : 886-2-268-7075 : 886-2-268-6327 : [email protected] APPROVED BY CHECK BY : 1-510-438-6799 : 1-510-438-6790 : [email protected] PREPARED BY CONTENTS 1. DESCRIPTION..................................................................................................... 1 2. FEATURES.......................................................................................................... 1 3. APPLICATIONS .................................................................................................. 1 4. PIN DESCRIPTION ............................................................................................. 2 5. FUNCTION DESCRIPTION................................................................................ 3 6. ABSOLUTE MAXIMUM RATINGS ................................................................... 4 7. RECOMMENDED OPERATING CONDITIONS............................................... 4 8. APPLICATION CIRCUIT .................................................................................... 5 9. TIMING DIAGRAM FOR MRD520A.................................................................. 6 10. OUTLINE DIMENSION ..................................................................................... 7 Uniform Industrial Corp. MRD520A Dual Channel F2F Decoder IC 1. DESCRIPTION The MRD520A is a 1.2um CMOS integrated circuit for purpose of amplification and decoding for F2F magnetic stripe encoding card reader. 2. FEATURES l l l l l l l Integrated Amplification Circuitry for magnetic head signals. Number of start bits (4/8 bits) to ignore selectable. Both output polarity supported. Adjustable read data output clock pulse width. Dual channel support for 75/210 BPI recording density. Magnetic head data input frequency range from 300 bit/sec to 12600 bit/sec. Idle mode controllable by external hardware or micro-processor. 3. APPLICATIONS l l Magnetic stripe card reader. POS keyboard. PIN Configuration (Top View) GND SEN1N SEN1P OP1OUT 1 28 2 27 3 26 4 25 RES ADJ1 CLS OUT1 OP2NIN 5 24 OUT1X OP2OUT 6 23 OCK1 OP3OUT OP6OUT OP5OUT 7 22 IBS 8 21 9 20 OSCO OSCI OP5NIN 10 19 OCK2 OP4OUT SEN2P 11 18 12 17 OUT2X OUT2 SEN2N 13 16 ADJ2 VREFIN 14 15 VDD OUTLINE SOP 28 PIN Page : 1 October, 1997 Uniform Industrial Corp. MRD520A Dual Channel F2F Decoder IC 4. PIN DESCRIPTION 1 GND 2 SEN1N Input from magnetic head 3 SEN1P Input from magnetic head 4 OP1OUT Amplifier OP1 output 5 OP2NIN Amplifier OP2 - input 6 OP2OUT Amplifier OP2 output 7 OP3OUT Amplifier OP3 output 8 OP6OUT Amplifier OP6 output 9 OP5OUT Amplifier OP5 output 10 OP5NIN Amplifier OP5 - input 11 OP4OUT Amplifier OP4 output 12 SEN2P Amplifier OP4 + input 13 SEN2N Amplifier OP4 - input 14 VREFIN Reference voltage for analog signal processing 15 VDD 16 ADJ2 Adjust read out clock pulse width for F2F channel 2 17 OUT2 Positive read out data for F2F channel 2 18 OUT2X Negative read out data for F2F channel 2 19 OCK2 Negative read out clock for F2F channel 2 20 OSCI RC oscillator input 21 OSCO RC oscillator output 22 IBS Select ignore leading bit, “LOW” for 4 bits and “HIGH” for 8 bits 23 OCK1 Negative read out clock for F2F channel 1 24 OUT1X Negative read out data for F2F channel 1 25 OUT1 Positive read out data for F2F channel 1 26 CLS Card Loading Signal output, “LOW” after ignore bits, “HIGH” if no input for around 12.5mS 27 ADJ1 Adjust read out clock pulse width for F2F channel 1 28 RES Power on reset, LOW reset the logic circuit and enter idle mode. Approx. 10mS after HIGH level to normal function Page : 2 October, 1997 Uniform Industrial Corp. MRD520A Dual Channel F2F Decoder IC 5. FUNCTION DESCRIPTION Data signal inputs read from a magnetic card via a magnetic head are fed into the SEN1P and SEN1N (SEN2P and SEN2N) pins, amplified and wave shaped by internal analog circuitry, then converted to logic level F2F data format. Once the F2F signals are detected, the decoding logic ignores the leading 4 or 8 bits (set by IBS pin), via the ignored bits the reference bit length is determined. The succeeding inputs are identified as bit 0 or 1 by the average bit length of preceding two bits, if the data toggles before 70% of the reference bit length then the data is identified as a “1” bit and the next data toggle regarded as the beginning of next data bit. If the data toggles after 70% of the reference bit length then the data is identified as a “0” bit and the current data toggle is as the beginning of next data. After the ignored bits, then pin CLS will be pulled low, the succeeding data bit will be shifted out after the beginning of next data bit. The pin OCK1 (OCK2) will be pulled low after the next data is detected and a 12uS delay inserted, it will be kept low for 14 to 60uS depending on the external resistor connected to pin ADJ1 (ADJ2). If the next bit comes before OCK1 (OCK2) goes high, then OCK1 (OCK2) will be forced to pull high and then begins next cycle, it means that the data signals will be ready before OCK1 (OCK2) goes low and stay valid till 12uS before next down edge of OCK1 (OCK2). Page : 3 October, 1997 Uniform Industrial Corp. MRD520A Dual Channel F2F Decoder IC 6. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions VCC Supply Voltage VDD VIN1 Input Voltage IBS,OSCI,RES,ADJ1,ADJ2 Ratings Unit -0.5 to +7.0 V -0.5 to VCC +0.5 V VIN2 Input Voltage OP2NIN,OP5NIN -0.5 to VCC +0.5 V OP1OUT,OP2OUT,OP3OUT, mA OP4OUT,OP5OUT,OP6OUT, -10 to +10 IO Output Current OSCO2,OUT2,OUT2X,OUT1, OUT1X,OCK1,OCK2 SEN1P ~ SEN1N, V -1.0 to +1.0 VID Differential Input Voltage SEN2P ~SEN2N TOPR Operating Temperature -10 to +70 ℃ TSTG Storage Temperature -50 to +140 ℃ 7. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Conditions VCC Supply Voltage VIH Input High Voltage IBS, RES VIL Input Low Voltage IBS, RES Output High Source OCK1,OUT1,OUT1X, IOH Current at VOH=VCC -0.4 OCK2, OUT2,OUT2X Output High Source IOH CLS Current at VOH=VCC -0.4 OCK1,OUT1,OUT1X, Output Low Sink Current IOL OCK2,OUT2, at VOL=0.4 OUT2X,CLS SEN1P ~ SEN1N VIN Differential Input Voltage SEN2P ~ SEN2N SEN1P ~ SEN1N FIN Input Frequency SEN2P ~ SEN2N FOSC Oscillation Frequency External resistor between ROSC OSCI & OSCO IOPR Signal input at 12.6K bps ISBY No signal input IDLE Reset = Vss Page : 4 Ratings Unit Min. Typ. Max. 4.5 5 5.5 V VCC -0.5 VCC +0.5 V -0.5 0 0.5 V -1.5 mA -0.1 mA 3 mA 5 80 mV 300 13000 Hz 2.3 MHz 30 Kohm 3.4 2.5 1.6 4.0 3.0 2.0 October, 1997 mA mA mA Uniform Industrial Corp. MRD520A Dual Channel F2F Decoder IC 8. APPLICATION CIRCUIT 1M 5V 0.1u 5V SEN1N/SEN2N SEN1P/SEN2P Mag. head RES ADJ1/ADJ2 5V 1K~3M IBS OSCO R1 OP1OUT/OP4OUT OP2NIN/OP5NIN OP2OUT/OP5OUT OP3OUT/OP4NIN C1 47p GND Rocs=30K(5V) OSCI OCK1/OCK2 OUT1/OUT2 OUT1X/OUT2X CLS VREFIN 5V 10K CLS VDD 2.2u 5V Note : R1 TK1 TK2 3.3K 22K C1 3300p 4700p Page : 5 October, 1997 Uniform Industrial Corp. MRD520A Dual Channel F2F Decoder IC 9. TIMING DIAGRAM FOR MRD520A Page : 6 October, 1997 Uniform Industrial Corp. MRD520A Dual Channel F2F Decoder IC 10. OUTLINE DIMENSION Symbol Dimensions in inch Dimensions in mm A A1 A2 0.110 Max. 0.004 Min. 0.093 +/-0.005 0.016 +0.004 -0.002 0.010 +0.004 -0.002 0.705 typ (0.725 Max) 0.295 +/-0.005 0.050 +/-0.006 0.370 NOM 0.406 +/-0.012 0.036 +/-0.008 0.055 +/-0.008 0.043 Max. 0.006 Max. 0°~ 10° 2.79 Max. 0.10 Min. 2.36 +/-0.13 0.410 +0.10 -0.05 0.254 +0.10 -0.05 17.91 typ (18.42 Max) 7.49 +/-0.13 1.270 +/-0.15 9.40 NOM 10.31 +/-0.31 0.91 +/-0.20 1.40 +/-0.20 1.09 Max. 0.15 Max. 0°~ 10° b c D E e e1 HE L LE S y Θ Note : a The max. value of dimension D included end flash. b The dimension E exclude resin lins. c The dimension E is for PCB surface mount pad pitch design reference only. d The dimension S included end flash. e All dimension are based in British system. Page : 7 October, 1997