Features • • • • • • • • Fully Integrated TX/RX with VCO Fast Settling Synthesizer Unlimited Multi-slot Operation with Advanced Closed-loop Modulation No Mechanical Tuning Required Low Current Consumption Auxiliary Voltage Regulator On-chip (3.2 V to 4.6 V) Supply-voltage Range 3 V to 4.6 V (Regulated) Ramp-signal Generator for Power Ramping and Power Control of External SiGe Power Amplifier (T7024 and T7026) • Supports Multiple Reference Clocks (10.368 MHz/13.824 MHz/20.736 MHz/27.648 MHz) • TX Preamplifier with 3 dBm Output Power at 2.45 GHz • Few Low-cost External Components Electrostatic sensitive device. Observe precautions for handling. Description The T2802 is an RF IC for low-power applications in the 2.45 GHz ISM band. The QFN48-packaged IC is a complete transceiver including image rejection mixer, IF amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, power-ramping generator for power amplifiers, integrated synthesizer, fully integrated VCO, TX filter and modulation compensation circuit for advanced closed-loop modulation concept. No mechanical tuning is necessary in production. 2.4 GHz WDECT/ISM Single-chip Transceiver T2802 Preliminary Figure 1. Block Diagram DEMOD MIXER OUT IF_IN IF_TANK IF AMP 1 IR MIXER CF TANK IF AMP 2 BB_OUT RF_IN DEMOD BB FILTER RAMP_OUT RAMP_SET RAMP GEN D/A RAMP D/A DEMOD DAC RSSI RSSI GF VCO TX/RX SWITCH TX_DATA CLOCK PC PD MCC 3-WIRE BUS DATA ENABLE RC CTRL LOGIC RX_ON TX_ON PU_RX/TX PU_PLL f TX_OUT :n TX DRIVER PU_VCO VCO REG AUX REG CP VREG_VCO VS_VCO VREG VS_REG VTUNE GND_VCO PU_REG REG_CTRL f :n CP LD REF_CLK I_CPSW Rev. 4509F–DECT–10/03 Table 1. Functional Block Description Name Description AUX REG Auxiliary voltage regulator BBF Baseband filter CP Charge pump DAC D/A converter for demodulator tuning DEMOD Demodulator GF Gaussian filter for transmit data IF AMP1 1st intermediate frequency amplifier IF AMP2 2nd intermediate frequency amplifier IR MIXER Image rejection mixer MCC Modulation compensation circuit PC Programmable counter PD Phase detector RAMP GEN Ramp-signal generator RC Reference counter RSSI Received signal-strength indicator TX DRIVER Buffer amplifier for TX_OUT TX/RX SWITCH Switches VCO signal to IR MIXER respectively TX DRIVER VCO Voltage-controlled oscillator VCO REG Voltage regulator for VCO Pin Configuration 2 RX_ON RAMP_SET 42 TX_ON 43 MIXER_OUT2 44 MIXER_OUT1 45 GND_PLL 46 VS_MIXER PU_RX/TX PU_VCO 47 PU_PLL 48 TX_DATA I_CPSW Figure 2. Pinning QFN48 41 40 39 38 37 CLOCK 1 36 RAMP_OUT DATA 2 35 IF_IN2 ENABLE 3 34 IF_IN1 REF_CLK 4 33 VS_IF LD 5 32 TX_OUT PU_REG 6 31 GND3 VS_PLL 7 30 RF_IN2 VREG 8 29 RF_IN1 REG_CTRL 9 28 GND2 VS_REG 10 27 IF_TANK2 GND_CP 11 26 IF_TANK1 VS_CP 12 25 RSSI VTUNE 20 21 22 23 24 BB_CF GND_VCO 19 BB_OUT VS_VCO VREG_VCO 18 REG_DEC 17 DAC_DEC 16 DEMOD_TANK2 15 GND1 14 DEMOD_TANK1 13 CP T2802 T2802 4509F–DECT–10/03 T2802 Pin Description Pin Symbol Function Configuration VS_PLL 1 CLOCK 3-wire-bus: Clock input 2 DATA 3-wire-bus: Data input 3 ENABLE 3-wire-bus: Enable input 7 CLOCK DATA ENABLE 1,2,3 5k 5k GND_PLL 43 VS_PLL 7 4 REF_CLK Reference-frequency input 10k 10k REF_CLK 4 GND_PLL 43 LD 5 5 LD 100 Lock-detect output GND_PLL 43 PU_REG 6 PU_REG Power-up input for auxiliary voltage regulator 6 25k 25k GND_PLL 43 3 4509F–DECT–10/03 Pin Description (Continued) Pin Symbol Function Configuration VS_PLL 7 GND1 VS_REG 10 18 VS_CP 12 GND2 28 VS_VCO 14 GND3 7 VS_PLL PLL supply voltage 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_REG 10 VS_PLL 7 8 VREG REG_CTRL 9 Auxiliary voltage-regulator output VREG 8 9 REG_CTRL Auxiliary voltage-regulator control output 10 VS_REG Auxiliary voltage-regulator supply voltage GND_PLL 43 VS_CP 12 11 GND_CP 12 VS_CP Charge-pump ground VS_PLL 7 Charge-pump supply voltage CP 13 13 CP Charge-pump output GND_PLL 43 GND_CP 11 4 T2802 4509F–DECT–10/03 T2802 Pin Description (Continued) Pin Symbol Function Configuration VS_VCO 14 VS_PLL 7 14 VS_VCO VCO voltage-regulator supply voltage 15 VREG_VCO VCO voltage-regulator control output VREG_VCO 15 16 GND_VCO VCO ground GND_PLL 43 GND_VCO 16 VREG_VCO 15 VS_PLL 7 17 VTUNE VCO tuning voltage input VTUNE 17 GND_PLL 43 GND_VCO 16 VS_PLL 7 GND1 VS_REG 10 VS_CP 12 18 GND2 28 VS_VCO 14 GND3 18 GND1 Ground 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 5 4509F–DECT–10/03 Pin Description (Continued) Pin Symbol Function Configuration VS_MIXER 42 19 DEMOD_TANK1 VS_IF 33 10k Demodulator tank circuit 10k DEMOD TANK1 19 20 DEMOD_TANK2 DEMOD TANK2 20 Demodulator tank circuit GND2 28 GND1 18 VREG_VCO 15 VS_PLL 7 21 DAC_DEC Decoupling PIN for VCO_DAC 10k DAC_DEC 21 GND_PLL 43 400 GND_VCO 16 VREG_VCO 15 VS_IF 33 22 REG_DEC 2k Decoupling PIN for VCO_REG REG_DEC 22 42k GND2 28 GND_VCO 16 6 T2802 4509F–DECT–10/03 T2802 Pin Description (Continued) Pin Symbol Function Configuration VS_IF 33 23 BB_CF Baseband filter corner-frequency control input BB_CF 23 GND2 28 GND1 18 VS_IF 33 24 BB_OUT Baseband filter output BB_OUT 24 GND2 28 GND1 18 VS_IF 33 25 RSSI Received signal strength indicator output RSSI 25 13k GND2 28 VS_IF 33 26 IF_TANK1 IF tank circuit IF_TANK1 26 27 IF_TANK2 27 IF tank circuit GND2 28 7 4509F–DECT–10/03 Pin Description (Continued) Pin Symbol Function Configuration VS_PLL 7 GND1 VS_REG 10 VS_CP 12 18 GND2 28 VS_VCO 14 GND3 28 GND2 Ground 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_MIXER 42 29 RF_IN1 RF input of image reject mixer RF_IN1 29 30 RF_IN2 RF_IN2 30 RF input of image reject mixer GND2 28 VS_PLL 7 GND1 VS_REG 10 VS_CP 12 18 GND2 28 VS_VCO 14 GND3 31 GND3 Ground 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 8 GND_PLL 43 T2802 4509F–DECT–10/03 T2802 Pin Description (Continued) Pin Symbol Function Configuration TX_OUT 32 32 TX_OUT TX driver amplifier output for PA GND3 31 VS_PLL 7 GND1 VS_REG 10 18 VS_CP 12 GND2 28 VS_VCO 14 GND3 33 VS_IF IF amplifier supply voltage 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_IF 33 34 IF_IN1 IF input of IF amplifier IF_IN1 34 35 IF_IN2 90k IF_IN2 35 IF input of IF amplifier GND2 28 VS_MIXER 42 VS_IF 33 36 RAMP_OUT Ramp-generator output for PA power ramping RAMP_OUT 36 GND2 28 9 4509F–DECT–10/03 Pin Description (Continued) Pin Symbol Function Configuration VS_MIXER 42 VS_IF 33 37 RAMP_SET Slew-rate setting of ramping signal 1k 100 RAMP SET 37 GND2 28 VS_IF 33 38 RX_ON RX control input 39 TX_ON TX control input RX_ON TX_ON 38, 39 5k 5k GND2 28 GND1 18 VS_MIXER 42 VS_IF 33 40 MIXER_OUT1 270 Mixer output to SAW filter MIXER_OUT1 40 41 MIXER_OUT2 270 MIXER_OUT2 41 Mixer output to SAW filter GND2 28 10 T2802 4509F–DECT–10/03 T2802 Pin Description (Continued) Pin Symbol Function Configuration VS_PLL 7 GND1 VS_REG 10 18 VS_CP 12 GND2 28 42 VS_MIXER Mixer supply voltage VS_VCO 14 GND3 31 43 GND_PLL PLL ground VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_VCO 14 44 PU_VCO VCO power-up input PU_VCO 44 5k 5k GND_PLL 43 GND_VCO 16 PU_RX/TX 45 25k 45 PU_RX/TX 25k RX/TX power-up input GND_PLL 43 GND1 18 11 4509F–DECT–10/03 Pin Description (Continued) Pin Symbol Function Configuration 20k 10k 46 PU_PLL 10k 10k 25k 25k 140k PLL power-up input PU PLL 46 GND PLL 43 VS_PLL 7 47 TX_DATA TX data input of Gaussian filter and modulationcompensation circuit TX_DATA 47 2.5k GND_PLL 43 VS_PLL 7 48 I_CPSW Charge-pump current control input I_CPSW 48 5k GND_PLL 43 12 T2802 4509F–DECT–10/03 T2802 Functional Description Receiver The RF signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110.592 MHz or 112.32 MHz. The IF amplifiers IF_AMP1 and IF_AMP2 with an external IF_TANK and an integrated RSSI function feed the signal to the demodulator DEMOD working at f = fIF/2 (» 55 MHz) and finally to an integrated baseband filter BB. For demodulator tunning in production an integrated 5-bit digital-to-analog (D/A) converter is provided to control the on-chip varicap diode. Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to the fully integrated VCO operating at twice the output frequency. After modulation the signal is frequency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This bus-controlled driver amplifier supplies typically +3 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled by a capacitor at the RAMP_SET pin. Synthesizer The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the fully integrated VCO (including on-chip inductors and varactors). A 3-bit digital-to-analog converter is used to pretune the frequency. The output signal is frequency-divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (fPD = 3.456 MHz). Unlimited multislot operation is possible by using the integrated advanced closed-loop modulation concept based on the modulation compensation circuit MCC. Power Supply An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided. 13 4509F–DECT–10/03 Figure 3. PLL Principle RF_IN Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD x (SMC x 32 + SSC) fVCO ext. loop filter PA driver Phase frequency detector PD fPD = 3.456 MHz Charge pump Divider by 2 VCO Mixer VCO DAC GF_DATA Controlled phase shifting Reference counter RC REF_CLK 10.368 MHz 13.824 MHz 20.736 MHz 27.648 MHz Modulation compensation MCC Gaussian filter GF 6.912 MHz SRC 3 4 6 8 1.152 Mbit/s PLL reference Frequency REF_CLK TX_DATA Baseband controller 14 T2802 4509F–DECT–10/03 T2802 The following table shows the LO frequencies for RX and TX for the DECT band plus additional channels for the extended DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported. Table 1. LO Frequencies Mode fIF/MHz Channel fANT/MHz fVCO/MHz SMC SSC C0 2401.920 2401.920 43 14 C1 2403.648 2403.648 43 15 TX RX RX 110.592 (for 10.368 MHz/ 20.736 MHz REF_CLK recommended) 112.320 (for 13.824 MHz/ 27.648 MHz REF_CLK recommended) ... ... ... ... ... C45 2479.680 2479.680 44 27 C46 2481.408 2498.688 44 28 C0 2401.920 2291.328 41 14 C1 2403.648 2293.056 41 15 ... ... ... ... ... C45 2479.680 2369.088 42 27 C46 2481.408 2370.816 42 28 C0 2401.920 2289.600 41 13 C1 2403.648 2291.328 41 14 ... ... ... ... ... C45 2479.680 2367.360 42 26 C46 2481.408 2369.088 42 27 Formula TX: fANT = fVCO = 1.728 MHz ´ (32 ´ SMC + SSC) RX: fANT = 1.728 MHz ´ (32 ´ SMC + SSC) + fIF Control Signals Table 2. Control Signals — Functions Signal Functions I_CPSW Charge pump current control PU_REG Activates AUX voltage regulator supplying the complete transceiver PU_VCO Activates VCO voltage regulator which supplies only the VCO PU_RX/TX Activates RX/TX blocks PU_PLL Activates PLL circuits: PC, PD, CP, RC RX_ON Activates RX circuits: BBF, DEMOD, IF AMP, IR MIXER TX_ON Activates TX circuits: TX-DRIVER, RAMP GEN, Starts RAMP SIGNAL at RAMP OUT Data Word 1 Bit D10 Activates GF in TX mode Data Word 1 Bit D9 Activates MCC in TX mode 15 4509F–DECT–10/03 Table 3. Control Signals — Modes Modes TX Mode RX Mode RSSI Only PU_REG 1 1 1 PU_VCO 1 1 1 PU_RX/TX 1 1 1 PU_PLL 1 1 1 RX_ON 0 1 1 TX_ON 1 0 1 BB filter OFF ON OFF Demodulator OFF ON OFF IF amplifiers and RSSI OFF ON ON IR mixer OFF ON ON RX switch OFF ON ON TX switch ON OFF OFF TX driver ON OFF OFF Ramp generator ON OFF OFF Programmable counter ON ON ON Voltage-controlled oscillator ON ON ON Gaussian filter ON OFF OFF Phase detector/charge pump ON ON ON Modulation compensation circuit ON OFF OFF Reference counter Typical current consumption at VS = 3.2 V ON ON ON 58 mA 85 mA 82 mA Serial Programming Bus The transceiver is programmed by the 3-wire bus (CLOCK, DATA and ENABLE). After the setting enable signal to low condition on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. When the enable signal has returned to high condition, the programmed information is loaded into the addressed latches according to the address bit condition (last bit). Additional leading bits are ignored and there is no check made how many pulses arrived during enable low condition. During enable low condition the bus current is increased to speed up the bus logic. To keep all information in the registers during standby, DATA_HOLD must be set to high condition. In this case the power-down current is below 100 µA. The programming of the transceiver is separated into two data words. Data word 1 controls mainly the channel information together with settings, which are closely related with the channel. Dataword 2 holds setup information, which is adjusted during production. 16 T2802 4509F–DECT–10/03 T2802 Data Word 1 MSB LSB Data bits D22 Address bit D21 D20 D19 RC D18 D17 D16 D15 D14 SC MC D13 D12 D11 D10 VS X MCC D9 E11 E10 D8 D7 D6 D5 GFCS D4 D3 VCODAC D2 D1 CPCS D0 A0 GF D11 = x: do not care Data Word 2 E12 PA E9 E8 E7 E6 E5 DEMODDAC/RAMPDAC E4 E3 MCCS E2 E1 E0 A0 TEST 0 Data Word 1 Programs PLL Settings With the Reference Counter bits D21 - D22 RC (Reference Counter) D22 D21 SRC REF_CLK 0 0 3 10.368 MHz 0 1 4 13.824 MHz 1 0 6 20.736 MHz 1 1 8 27.648 MHz With the Main Counter bits D13 - D15 MC (Main Counter) D15 D14 D13 SMC 0 0 0 40 0 0 1 41 ... ... ... ... 1 1 0 46 1 1 1 47 With the Swallow Counter bits D16 - D20 SC (Swallow Counter) D20 D19 D18 D17 D16 SSC 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 ... ... ... ... ... ... 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 17 4509F–DECT–10/03 VCO Selection With bit D12 VCO Selection D12 VCO Mode 0 RX-VCO 1 TX-VCO Gaussian Filter On/Off With bit D0 GF is used only in TX mode. Modulation Compensation Circuit On/Off D0 GF (Gaussian Filter) 0 OFF 1 ON With bit D10 MCC is used only in TX mode. D10 MCC (Modulation Compensation Circuit) 0 OFF 1 ON GFCS Adjustment With bits D7 - D9 Only in TX mode effective for setting the frequency deviation of the modulation. GFCS (Gaussian Filter Settings) 18 D9 D8 D7 GFCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% T2802 4509F–DECT–10/03 T2802 VCO_DAC Adjustment With bits D3 - D6 Used to pretune the VCO frequency in case of production tolerances of the device. Pretune DAC Voltage D6 D5 D4 D3 fVCO/% 0 0 0 0 -5 0 0 0 1 ... 0 0 1 0 ... ... ... ... ... ... 1 1 0 1 ... 1 1 1 0 ... 1 1 1 1 5 CPCS Adjustment With bits D1 - D2 Used to adjust the charge pump current. This can be used to compensate the change of the tuning sensitivity over frequency and device tolerances. CPCS (Charge-pump Current Settings) D2 D1 CPCS 0 0 -1 0 1 0 1 0 1 1 1 2 Data Word 2 Programs DEMODDAC Adjustment With bits E6 - E10 Only in RX mode effective. Used to tune the demodulator center frequency and allows to compensate tolerances of external components and the T2802. Demod DAC Voltage E10 E9 E8 E7 E6 fIFcenter % 0 0 0 0 0 -5 0 0 0 0 1 ... 0 0 0 1 0 ... ... ... ... ... ... ... 1 1 1 0 1 ... 1 1 1 1 0 ... 1 1 1 1 1 5 19 4509F–DECT–10/03 RAMPDAC Adjustment for TX Mode With bits E6 - E10 Only in TX mode effective. Used to control the power of the external PA by adjusting the ramping voltage. RAMPDAC Voltage (at Pin 36 RAMP_OUT) E10 E9 E8 E7 E6 VRAMP_OUT 0 0 0 0 0 1.1 V 0 0 0 0 1 ... 0 0 0 1 0 ... ... ... ... ... ... ... 1 0 1 1 1 1.68 V 1 1 0 0 0 1.7 V ... ... ... ... ... ... 1 1 1 1 0 ... 1 1 1 1 1 1.7 V MCCS Adjustment With bits E3 - E5 Only in TX mode effective. Adjusts the modulation compensation circuit for closed-loop modulation. This adjustment is done with a test sequence of a long stream of ,1‘ - ,0‘. The correct setting is achieved if the modulation is not affected by the PLL. MCCS (Modulation Compensation Settings) E5 E4 E3 MCCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% TEST Mode Settings With bits E0 - E2 In normal operation Lock detect output is used. All other settings are for test only. 20 E2 E1 E0 Signal at Lock Detect Output CP Mode 0 0 0 Lock detect Active 0 0 1 PC out/2 Active 0 1 0 RC out/2 Active 0 1 1 MCCTEST: RC out divided by 512 Active 1 0 0 Lock detect High imp. 1 0 1 PC out/2 High imp. 1 1 0 RC out/2 High imp. 1 1 1 GFTEST: RC out High imp. T2802 4509F–DECT–10/03 T2802 Output Power Settings With bits E11 - E12 PA (Output Power Settings) E12 E11 PA 0 0 -21 dBm 0 1 -11 dBm 1 0 -4 dBm 1 1 +3 dBm Figure 4. 3-Wire Bus Protocol Timing Diagram DATA CLOCK ENABLE TC TPER TL TS TEC TT TH Description Symbol Minimum Value Unit Clock period TPER 125 ns Set time data to clock TS 60 ns Hold time data to clock TH 60 ns Clock pulse width TC 125 ns Set time enable to clock TL 200 ns Hold time enable to data TEC 0 ns TT 250 ns Time between two protocols Figure 5. TX DATA Timing RefCLK TX_DATA TS TH Set-up time TX DATA TS > 8 ns Hold time TX DATA TH > 8 ns When using REFCLK = 10.368 MHz, TS and TH must be considered for falling and rising edge of REFCLK 21 4509F–DECT–10/03 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages refer to GND Parameters Pin Symbol Min. Max. Unit Supply voltage regulator 10 VS_REG 3.2 4.7 V 7, 12, 14, 33, 42 VS 3.0 4.7 V 1, 2, 3, 38, 39, 44-48 VIN -0.3 VS V 150 °C 150 °C Supply voltage Logic input voltage Junction temperature Tjmax Storage temperature Tstg -40 Thermal Resistance Parameters Junction ambient Handling Symbol Value Unit RthJA 25 K/W Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test requirement (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test requirement (MM) in accordance to EIA/JESD22-A115A. Operating Range Parameters Pin Symbol Min. Typ. Max. Unit Supply voltage regulator 10 VS_REG 3.2 3.6 4.6 V 7, 14, 33, 42 VS 2.9 3.0 4.6 V 12 VSCP VS 4.6 V Tamb -25 +85 °C Supply voltage Supply voltage charge pump Ambient temperature 22 T2802 4509F–DECT–10/03 T2802 Electrical Characteristics Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit IR Mixer (Pins 29, 30, 40 and 41) Input impedance Single ended, pins 29 or 30 Zin 110 + j12 W Image rejection ratio Pins 40 and 41 IRR 20 dB DSB noise figure Single ended, pins 29 or 30 NFDSB= NFSSB 10 dB Conversion gain Rload = 200 W Gconv 11 dB Input intercept point Single ended, pins 29 or 30 IIP3 -7 dBm Output impedance Differential, pins 40 and 41 Zout 175 + j145 W Differential, pins 34 and 35 Zin 1200 j480 W Lower cut-off frequency fl3dB 90 MHz Upper cut-off frequency fu3dB 130 MHz Gp 85 dB BW3dB 10 MHz NF 9 dB IF Amplifier (Pins 26, 27, 34 and 35) Input impedance Power gain Bandwidth of external tank circuit Pins 26 and 27 Noise figure RSSI (Pins 25, 34 and 35) RSSI sensitivity At IF_IN1,2; pins 34 and 35 Pmin 20 dBµV RSSI compression At IF_IN1,2; pins 34 and 35 Pmax 100 dBµV DR 80 dB Acc ±2 dB RSSI dynamic range RSSI resolution Slope of the RSSI has to be steady RSSI rise time Pin = 30 to 100 dBµV, pin 25 tr 1 µs RSSI fall time Pin = 100 to 30 dBµV, pin 25 tf 1 µs Quiescent output voltage At Pin < 20 dBµV at IF_IN1, IF_IN2, Pin 25 Iout 0.4 V Maximum output voltage At Pin = 100 dBµV at IF_IN1, IF_IN2, Pin 25 Iout 1.9 V CCRR 10 dB FM Demodulator, BB-filter (Pins 19, 20, 23 and 24) Co-channel rejection ratio At Pin = -75 dBm at IR-mixer input Sensitivity Quality factor of external tank circuit approximately 20, fres = FIF/2, pin 24 S 0.5 V/MHz Amplitude of recovered signal Nominal deviation of signal ±288 kHz, pin 24 A 450 mVpp Corner frequency Pin 23: C = 68 pF fc 680 kHz Output voltage DC range Pin 24 DEMOD_DAC range See bus protocol E6 to E10 VoutDC DfIFcenter 1 VS - 1 ±5 V % 23 4509F–DECT–10/03 Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. TX-VCO, D12 (VS) = 1 RX-VCO, D12 (VS) = 0 fvco fvco 2400 2289 Typ. Max. Unit 2500 2389 MHz MHz VCOs Frequency range Tuning gain Gtune Frequency control voltage range Pin 17 Vtune VCO_DAC range See bus protocol D3 ... D6 70 0.4 MHz/V 2.8 Dfvco,DAC ±5 Scaling factor prescaler SPSC 32/33 Scaling factor main counter SMC 40 - 47 Scaling factor swallow counter SSC V % PLL External reference input frequency AC coupled sinewave, pin 4 fREF_CLK External reference input voltage AC coupled sinewave, pin 4 VREF_CLK Scaling factor reference counter 0 31 10.368 13.824 20.736 27.648 50 MHz MHz MHz MHz 250 SRC 3/4/6/8 mVRMS Charge Pump (Pin 13) Output current VCP = VVS_CP /2, I_CPSW = ‘1’, Pin 48 ICP_nom 7.5 mA Output current VCP = VVS_CP /2, I_CPSW = ‘0’, Pin 48 ICP_nom 1.2 mA Current scaling ICP = ICP_nom + CPCS ´ ICP_step (see bus protocol D1 ... D2) ICP_step 0.2 mA IL ±100 pA fTXFCLK 6.912 MHz GFFM_nom ±400 kHz Leakage current Gaussian Transmit Filter (Gaussian Shape B ´ T = 0.5) Tx data filter clock 6 taps in filter Frequency deviation ´ Frequency deviation scaling GFFM = GFFM_nom GFCS (see bus protocol D7 ... D9) GFCS 60 130 % Modulation Compensation Circuit Oversampling OVS Digital sum variation DSV Current scaling factor See bus protocol E3 ... E5 MCCS 6 85 60 130 % TX Driver (Pin 32) Maximum output power At L = 5.6 nH, pin 32 (see bus protocol E11 - E12) PTX 3 dBm Minimum output power At L = 5.6 nH, pin 32 (see bus protocol E11 - E12) PTX -21 dBm 24 T2802 4509F–DECT–10/03 T2802 Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit RF leakage In RX mode Pleak -47 dBm Output impedance At L = 5.6 nH, 2.5 GHz, pin 32 ZOUT 13 + j40 W Minimum output voltage Pin 36 and 37 Vmin 0.7 V Maximum output voltage See bus protocol E6 - E10 Vmax Rise time Cramp = 270 pF at pin 37 tr 5 µs Fall time Cramp = 270 pF at pin 37 tf 5 µs Ramp Generator (Pins 36 and 37) 1.1 1.8 V Lock Detect and Test Mode Output (Pin 5) locked = ‘1’, unlocked = ‘0’ Lock detect output, test mode output test modes (see bus protocol E0 ... E2) LD Leakage current VOH = 4.6 V IL 5 µA Saturation voltage IOL = 0.5 mA VSL 0.4 V 3.1 V Auxiliary Regulator (Pins 8, 9 and 10) Output voltage VSREG = 3 V, pin 8 VREG Supply voltage rejection VPin10 = VDC + 0.1 Vpp fPin10 = 0.1 to 10 kHz CPin8 = 100 nF SVR 2.9 3.0 TBD dB VCO Regulator (Pins 14, 15 and 12) Output voltage VSVCO = 3 V, pin 15 VREG_VCO 2.6 2.7 2.8 V 6.912 MHz 3-wire Bus Clock fClock Logic Input Levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, PU_VCO, TX_DATA, DATA_HOLD) (Pins 1, 2, 3, 38, 39, 44, 47 and 48) High input level = ‘1’ ViH Low input level = ‘0’ ViL High input current = ‘1’ IiH Low input current = ‘0’ 1.5 V 0.5 V -5 5 µA IiL -5 5 µA 2.0 Standby Control (Pins 6, 45 and 46) Power Up PU_REG = ‘1‘ PU_RX/TX = ‘1‘ PU_PLL = ‘1‘ High input level Pin 6 Pin 45 Pin 46 VPU_REG VPU_RX/TX VPU_PLL Standby PU_REG = ‘0‘ PU_RX/TX = ‘0‘ PU_PLL = ‘0‘ Low input level Pin 6 Pin 45 Pin 46 VPU_REG,OFF VPU_RX/TX,OFF VPU_PLL,OFF V 0.7 V 25 4509F–DECT–10/03 Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit Power Up PU_REG = ‘1‘ PU_RX/TX = ‘1‘ VPU = 3 V, pin 6 VPU = 4.6 V, pin 45 IPU_REG IPU_RX/TX 20 60 30 80 40 100 µA µA PU_PLL = ‘1‘ High input current VPU = 3 V, pin 46 VPU = 4.6 V IPU_PLL 100 200 125 300 150 400 µA µA Standby PU_xxxx = ‘0’ Low input current VPU = 0 V, pin 6 VPU = 0.5 V, pins 45, 46 IPU,OFF 0.1 1 µA µA Settling Time VS = 0 ® active operation Switched from VS = 0 to VS = 3V tsoa < 10 µs Settling Time standby ® active operation Switched from PU = ‘0’ to PU = ‘1’ tssa < 10 µs Settling Time active operation ® standby Switched from PU = ‘1’ to standby tsas <2 µs RX IS 85 mA RSSI only IS 82 mA TX IS 54 mA TX (MCC, GF active) IS 58 mA Standby current PU_RX/TX = GND IS Supply current CP VVS_CP = 3 V, PLL in lock condition, Pin 13 ICP Power Supply (Pins 7, 10, 12, 14, 33 and 42) Total supply current 26 10 1 µA µA T2802 4509F–DECT–10/03 T2802 Figure 6. Typical Application Circuit RAMP_OUT TX_OUT RF_IN 47 pF 180 nH 100 nH SAW Filter TFS 112B 47pF 18 pF 27 pF RSSI 37 RAMP_SET RSSI 25 IF_TANK1 26 GND2 28 RF_IN1 29 GND3 31 RF_IN2 30 VS_IF 33 IF_TANK2 27 56 pF TX_OUT 32 27 pF IF_IN1 34 RAMP_OUT 36 150 nH IF_IN2 35 68 pF BB_OUT 24 RX_ON 38 RX_ON BB_CF 23 TX_ON 39 TX_ON REG_DEC 22 40 MIXER_OUT1 DAC_DEC 21 41 MIXER_OUT2 DEMOD_TANK2 20 T2802 42 VS_MIXER GND1 18 12 VS_CP 11 GND_CP 10 VS_REG 9 REG_CTRL 8 VREG VS_VCO 14 6 PU_REG 48 I_CPSW 7 VS_PLL 47 TX_DATA I_CPSW 22 nF GND_VCO 16 5 LD TX_DATA tbd VREG_VCO 15 4 REF_CLOCK 46 PU_PLL 3 ENABLE 45 PU_RX/TX PU_PLL 2 DATA PU_RX/TX tbd VTUNE 17 1 CLOCK 44 PU_VCO 2.2 nF 100 pF DEMOD_TANK1 19 43 GND_PLL PU_VCO BB_OUT 68 pF 180 Ω 150 nF CP 13 56 pF 470 nF CLOCK DATA ENABLE 220 pF REF_CLK LD 4.7 nF PU_REG VCC BC808 or similar tantal tantal 27 4509F–DECT–10/03 Ordering Information Extended Type Number T2802-PLQ Package QFN48 Remarks Taped and reeled Package Information 28 T2802 4509F–DECT–10/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2003. All rights reserved. Atmel ® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4509F–DECT–10/03