S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD June. 2000. Ver. 0.0 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD INTRODUCTION S6A0069 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can display 1, 2-line with 5 x 8 or 5 x 11 dots format. FUNCTIONS • Character type dot matrix LCD driver & controller. • Internal driver: 16 common and 40 segment signal output. • Easy interface with 4-bit or 8-bit MPU • Display character pattern : 5 x 8 dots format (204 kinds), 5 x 11 dots format (32 kinds) • The special character pattern can be programmable by Character Generator RAM directly. • A customer character pattern can be programmable by mask option. • It can drive a maximum 80 characters by using the S6A0065 or S6A2067 externally. • Various instruction functions • Automatic power on reset FEATURES • Internal Memory - Character Generator ROM (CGROM): 10,080 bits (204 characters x 5 x 8 dot) & ( 32 characters x 5 x 11 dot) - Character Generator RAM (CGRAM): 64 × 8 bits (8 characters × 5 × 8 dot) - Display Data RAM (DDRAM): 80 x 8 bits (80 characters max.) • Low Power Operation - Power supply voltage range: 2.7 to 5.5V (VDD) - LCD drive voltage range: 3.0 to 13.0V (VDD - V5) • CMOS process • Programmable duty cycle: 1/8, 1/11, 1/16 • Internal oscillator with an external resistor • Low power consumption • Bare chip available 2 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 BLOCK DIAGRAM VDD GND Parallel to Serial Data Conversion Circuit V1 V2 V3 V4 V5 5 Busy Flag R/W 8 RS E DB0DB3 Character Generator ROM (CGROM) 10080 bits 8 8 8 Instruction Register (IR) 8 Instruction Decoder (ID) 7 OSC2 Timing Generator Circuit Cursor & Blink Controller 8 7 OSC1 Character Generator RAM (CGRAM) 512 bits 8 Data Register (DR) Input/ Output Buffer DB4DB7 5 7 7 Display Data RAM (DDRAM) 80x8 bits 40-bit Shift Register 40-bit Latch Circuit Segment Driver 40 S1-S40 D Address Counter 16-bit Shift Register Common 16 Driver C1-C16 CLK1 CLK2 M 3 S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 PAD CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S6A0069 Y (0, 0) X Chip size: 4060 × 3840 Pad size: 100 × 100 Unit: µm OSC2 V1 V2 V3 V4 V5 CLK1 CLK2 VDD M D RS R/W E DB0 DB1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 GND OSC1 4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 S39 S40 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 DB7 DB6 DB5 DB4 DB3 DB2 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 PAD CENTER COORDINATES Unit: um PAD PAD COORDINATE NUM. NAME X 1 S22 2 COORDINATE PAD PAD Y NUM. NAME X Y -670 -1754 55 C9 1864 335 V4 -520 -1754 56 C10 1864 460 30 V5 -370 -1754 57 C11 1864 585 1090 31 CLK1 -220 -1754 58 C12 1864 710 -1864 965 32 CLK2 -70 -1754 59 C13 1864 835 S17 -1864 840 33 VDD 80 -1754 60 C14 1864 960 7 S16 -1864 715 34 M 230 -1754 61 C15 1864 1085 8 S15 -1864 590 35 D 380 -1754 62 C16 1864 1210 9 S14 -1864 465 36 RS 518 -1754 63 S40 1864 1341 10 S13 -1864 340 37 R/W 642 -1754 64 S39 1864 1466 11 S12 -1864 215 38 E 768 -1754 65 S38 886 1754 12 S11 -1864 90 39 DB0 894 -1754 66 S37 760 1754 13 S10 -1864 -35 40 DB1 1018 -1754 67 S36 636 1754 14 S9 -1864 -160 41 DB2 1864 -1488 68 S35 510 1754 15 S8 -1864 -285 42 DB3 1864 -1362 69 S34 386 1754 16 S7 -1864 -410 43 DB4 1864 -1238 70 S33 260 1754 17 S6 -1864 -535 44 DB5 1864 -1112 71 S32 136 1754 18 S5 -1864 -660 45 DB6 1864 -988 72 S31 10 1754 19 S4 -1864 -785 46 DB7 1864 -862 73 S30 -114 1754 20 S3 -1864 -910 47 C1 1864 -665 74 S29 -240 1754 21 S2 -1864 -1034 48 C2 1864 -540 75 S28 -364 1754 22 S1 -1864 -1159 49 C3 1864 -415 76 S27 -490 1754 23 GND -1864 -1285 50 C4 1864 -290 77 S26 -614 1754 24 OSC1 -1864 -1414 51 C5 1864 -165 78 S25 -740 1754 25 OSC2 -1120 -1754 52 C6 1864 -40 79 S24 -864 1754 26 V1 -970 -1754 53 C7 1864 85 80 S23 -989 1754 27 V2 -820 -1754 54 C8 1864 210 PAD PAD Y NUM. NAME X -1864 1465 28 V3 S21 -1864 1340 29 3 S20 -1864 1215 4 S19 -1864 5 S18 6 COORDINATE 5 S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD PIN DESCRIPTION PIN No VDD 33 GND V1 - V5 23 I/O - 26- 30 NAME DESCRIPTION Supply Supply Voltage for logical circuit (+3V ± 10%,+5V ±10%) Voltage 0V (GND) INTERFACE Power Supply Bias voltage level for LCD driving. S1 - S40 1-22, 63- 80 O Segment output Segment signal output for LCD drive. LCD C1 - C16 47-62 O Common output Common signal output for LCD drive. LCD OSC1 24 I Oscillator OSC2 25 O Oscillator CLK1 31 O Extension driver Latch clock extension driver latch clock. CLK2 32 O Extension driver Shift clock extension driver shift clock. M 34 O Alternated signal for LCD driver output Outputs the alternating signal to convert LCD driver waveform to AC. Extension driver D 35 O Display data interface Outputs extension driver data (the 41th dot's data) Extension driver Used as register selection input. When RS = "High", Data register is selected. When RS = "Low", Instruction register is selected. MPU Used as read/write selection input. When R/W = "High", read operation. When R/W = "Low", write operation. MPU Read/write enable signal. MPU When 8-bit bus mode, used as low order bidirectional data bus. In 4-bit bus mode open these pins. MPU When 8-bit bus mode, used as high order bidirectional data bus. In case of 4bit bus mode, used as both high and low order. DB7 is used for Busy Flag output. MPU RS 36 I Register select R/W 37 I Read/Write E 38 I Read/write enable DB0DB3 39-42 I/O DB4DB7 6 43-46 Data bus 0-7 When use internal oscillator, connect external Rf resistor. If external clock is used, connect it to OSC1. External Resistor/ Oscillator OSC1 Extension driver 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 FUNCTION DESCRIPTION System Interface This chip has all two kinds of interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus and 8-bit bus is selected by DL bit in the instruction register. During read or write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register(IR). The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM. The target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS input pin in 4-bit/8-bit bus mode. Table 1. Various Kinds of Operations according to RS and R/W Bits RS R/W Operation L L Instruction Write operation (MPU writes Instruction code into IR) L H Read Busy Flag (DB7) and address counter (DB0 - DB6) H L Data Write operation (MPU writes data into DR) H H Data Read operation (MPU reads data from DR) Busy Flag (BF) When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High. Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0 - DB6 ports. 7 S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD Display Data RAM (DDRAM) DDRAM stores display data of maximum 80 x 8 bits (80 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number. (refer to Figure1.) MSB LSB AC6 AC5 AC4 AC3 AC2 AC1 AC0 Figure 1. DDRAM Address 1) 1-line Display In case of 1 line display, the address range of DDRAM is 00H - 4FH. Extension driver will be used. Fig-2 shows the example that 40 segment extension driver is added. Display position COM1 COM8 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 SEG1 S6A0069 SEG40 14 SEG1 Extension driver (40 SEG) SEG40 SEG1 Extension driver (40 SEG) SEG40 DDRAM Address COM1 COM8 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 SEG1 S6A0069 SEG40 13 SEG1 Extension driver (40 SEG) SEG40 SEG1 Extension driver (40 SEG) SEG40 (After Shift Left) COM1 COM8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 SEG1 S6A0069 SEG40 SEG1 Extension driver (40 SEG) 15 SEG40 SEG1 Extension driver (40 SEG) (After Shift Right) Figure 2. 1-line x 24 Character Display with 40 Segment Extension Driver 8 SEG40 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 2) 2-line Display In case of 2 line display, the address range of DDRAM is 00H - 27H, 40H - 67H. Extension driver will be used. Figure 3 shows the example that 40 segment extension driver is added. Display position COM1 COM8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 DDRAM Address COM9 COM16 40 41 42 SEG1 COM1 COM8 COM9 COM16 43 44 45 S6A0069 46 47 SEG40 48 49 4A 4B 4C 4D 4E 4F SEG1 Extension driver (40 SEG) SEG40 53 54 55 56 57 SEG1 Extension driver (40 SEG) SEG40 3 4 5 6 7 8 9 10 14 15 16 17 18 19 20 21 22 23 24 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 SEG40 13 52 2 S6A0069 12 51 1 SEG1 11 50 SEG1 Extension driver (40 SEG) SEG40 SEG1 Extension driver (40 SEG) SEG40 (After Shift Left) 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 COM9 67 40 41 42 43 44 45 46 COM16 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 COM1 COM8 SEG1 S6A0069 SEG40 13 14 15 SEG1 Extension driver (40 SEG) SEG40 SEG1 Extension driver (40 SEG) SEG40 (After Shift Right) Figure 3. 2-line x 24 Character Display with 40 Segment Extension Driver 9 S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD CGROM (Character Generator ROM) CGROM has a 5 x 8 dots 204 characters pattern and a 5 x 10 dots 32 characters pattern. CGROM has 204 character patterns of 5 x 8 dots, and 32 character patterns of 5 x 11 dots. CGRAM (Character Generator RAM) CGRAM has up to 5 × 8 dot, 8 characters. By writing font data to CGRAM, user defined characters can be used (refer to Table 5) Timing Generation Circuit Timing generation circuit generates clock signals for the internal operations. LCD Driver Circuit LCD Driver circuit has 16 common and 40 segment signals for LCD driving. Data from CGRAM/CGROM is transferred to 40 bit segment latch serially, and then it is stored to 40 bit shift latch. When each common is selected by 16 bit common register, segment data also output through segment driver from 40 bit segment latch. In case of 1-line display mode, COM1- COM8 have 1/8 duty or COM1 COM11 have 1/11duty, and in 2-line mode, COM1 - COM16 have 1/16 duty ratio. Cursor / Blink Control Circuit It controls cursor/blink ON / OFF at cursor position. 10 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 Table 5. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM) Character Code (DDRAM data) CGRAM Address D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 0 0 0 0 x 0 0 0 0 . . . . . 0 . . . . . . . . . . 0 0 0 0 x . . . . . 0 1 1 1 0 0 . . . . . . . . . . 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 x P6 x CGRAM Data P5 P4 P3 P2 x 0 x x . . . . . Pattern number 0 Pattern 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 . . . . . 1 1 1 0 0 0 0 1 1 x P0 1 0 0 1 . . . . . P1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 . . . . . Pattern 8 11 S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD INSTRUCTION DESCRIPTION Outline To overcome the speed difference between internal clock of S6A0069 and MPU clock, S6A0069 performs internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus. (refer to Table 5 ) Instruction can be divided largely four kinds, (1) S6A0069 function set instructions ( set display methods, set data length, etc.) (2) Address set instructions to internal RAM (3) Data transfer instructions with internal RAM (4) Others. The address of internal RAM is automatically increased or decreased by 1. NOTE: During internal operation, Busy Flag (DB7) is read High. Busy Flag check must precede the next instruction. When an MPU program with checking the Busy Flag (DB7) is made, it must be necessary 1/2 fosc for executing the next instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "LOW". Contents 1) Clear Display RS 0 R/W DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). 2) Return Home RS 0 R/W DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 - Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change. 12 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 3) Entry Mode Set RS 0 R/W DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 I/D SH Set the moving direction of cursor and display. I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM operates the same as DDRAM, when read from or write to CGRAM. SH: Shift of entire display When DDRAM read (CGRAM read/write) operation or SH = "Low", shift of entire display is not performed. If SH = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "1" : shift left, I/D = "0" : shift right). 4) Display ON / OFF Control RS 0 R/W DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 D C B Control display/cursor/blink ON/OFF 1 bit register. D : Display ON/OFF Control Bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. C : Cursor ON/OFF Control Bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. B : Cursor Blink ON/OFF Control Bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. 5) Cursor or Display Shift RS 0 R/W DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 S/C R/L - - Shifting of right/left cursor position or display without writing or reading of display data. This instruction is used to correct or search display data (Refer to table 6). During 2-line mode display, cursor moves to the 2nd line after the 40th digit of the 1st line. Note that display shift is performed simultaneously in all the lines. When displayed data is shifted repeatedly, each line is shifted individually. When display shift is performed, the contents of the address counter are not changed. 13 S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD Table 6. Shift Patterns According to S/C and R/L Bits S/C R/L Operation 0 0 Shift cursor to the left, AC is decreased by 1 0 1 Shift cursor to the right, AC is increased by 1 1 0 Shift all the display to the left, cursor moves according to the display 1 1 Shift all the display to the right, cursor moves according to the display 6) Function Set RS 0 R/W DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 DL N F - - DL : Interface Data Length Control Bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it needs to transfer 4-bit data by two times. N : Display Line Number Control Bit When N = "Low", it means 1-line display mode. When N = "High", 2-line display mode is set. F : Display Font Type Control Bit When F = "Low", it means 5 × 8 dots format display mode When F = "High", 5 × 11 dots format display mode. 7) Set CGRAM Address RS 0 R/W DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. 8) Set DDRAM Address RS 0 R/W DB7 0 1 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". 9) Read Busy Flag & Address RS 0 R/W DB7 1 BF DB6 DB5 DB4 DB3 DB2 DB1 DB0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 This instruction shows whether S6A0069 is in internal operation or not. If the resultant BF is High, it means the internal operation is in progress and you have to wait until BF to be Low, and then the next instruction can be performed. In this instruction you can read also the value of address counter. 14 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 10) Write Data to RAM RS 1 R/W DB7 0 D7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D6 D5 D4 D3 D2 D1 D0 Write binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction (DDRAM address set, CGRAM address set). RAM set instruction can also determine the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. 11) Read Data from RAM RS 1 R/W DB7 1 D7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D6 D5 D4 D3 D2 D1 D0 Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly. NOTE: In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction. 15 S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD Table 7. Instruction Table Instruction Code Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 Description Execution time Instruction Code (fsoc=270kHz) Write "20H" to DDRAM. and set Clear Display DDRAM address to "00H" from 1.53ms AC. Set DDRAM address to "00H" from AC and return cursor to its Return Home 0 0 0 0 0 0 0 0 1 X original position if shifted. 1.53ms The contents of DDRAM are not changed. Entry Mode Set Assign cursor moving direction 0 0 0 0 0 0 0 1 I/D SH Set display(D), cursor(C), and 0 0 0 0 0 0 1 D C B Control Cursor or Display Shift 39µs enable. Display ON/OFF and make shift of entire display blinking of cursor(B) on/off 39µs control bit. Set cursor moving and display 0 0 0 0 0 1 S/C R/L X X shift control bit, and the direction, 39µs without changing DDRAM data. Set interface data length (DL : 4- Function Set 0 0 0 0 1 DL N F X X bit/8-bit), numbers of display line (N : 1-line/2-line), display font 39µs type(F : 5 X 8 dots/ 5 X 11 dots) Set CGRAM Address Set DDRAM Address 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Address Write Data to RAM Read Data from RAM counter. Set DDRAM address in address counter. 39µs 39µs Whether during internal operation Read Busy Flag and Set CGRAM address in address or not can be known by reading BF. The contents of address 0µs counter can also be read. 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Write data into internal RAM (DDRAM/CGRAM). Read data from internal RAM (DDRAM/CGRAM). 43µs 43µs NOTE: When an MPU program with checking the Busy Flag (DB7) is made, it must be necessary 1/2 fosc is necessary for executing the next instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "LOW". 16 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 INTERFACE WITH MPU 1) Interface with 8-bit MPU When interfacing data length is 8-bit, transfer is performed at a time through 8 ports, from DB0 to DB7. Example of timing sequence is shown below. RS R/W E Internal signal DB7 Internal Operation DATA Instruction Busy Busy Flag Check Busy Busy Flag Check No Busy Busy Flag Check DATA Instruction Figure 4. Example of 8-bit Bus Mode Timing Diagram 17 S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) Interface with 4-bit MPU When interfacing data length is 4-bit, only 4 ports, from DB4 to DB7, are used as data bus. At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then lower 4-bit (in case of 8-bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed by two times. Busy Flag outputs "High" after the second transfer are ended. Example of timing sequence is shown below. RS R/W E Internal signal DB7 Internal Operation D7 D3 AC3 No Busy AC3 D7 D3 Busy Instruction Busy Flag Check Busy Flag Check Figure 5. Example of 4-bit Bus Mode Timing Diagram 18 Instruction 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 APPLICATION INFORMATION ACCORDING TO LCD PANEL 1) LCD Panel: 8 Character × 1-line Character Format; 5 × 7 dots + 1-cursor line (1/4 Bias, 1/8 Duty) C1 . . . C7 C8 S1 S6A0069 . . . .. S10 S38 S39 S40 2) LCD Panel: 8 Character × 1-line Character Format; 5 × 10 dots + 1 cursor line (1/4 Bias, 1/11 Duty) C1 . . . C10 C11 S1 . . . S10 .. S6A0069 S38 S39 S40 19 S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD 3) LCD Panel: 8 Character × 2-line Character Format; 5 × 7 dots + 1-cursor line (1/5 Bias, 1/16 Duty) C1 . . . C7 C8 C9 . . . S6A0069 C15 C16 S1 . . . .. S10 S38 S39 S40 20 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 4) LCD Panel: 16 Character ×1-line Character Format; 5×7 dots + 1-cursor line (1/5 Bias, 1/16 Duty) C1 . . . C7 C8 S1 . . . S6A0069 .. S10 S39 S40 C9 . . . C16 21 S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD 5) LCD Panel: 4 Character × 2-line Character Format; 5 × 7 dots + 1-cursor line (1/4 Bias, 1/8 Duty) S1 . . . .. S10 S18 S19 S20 C1 . . . C7 C8 S6A0069 S21 . . . .. S30 S38 S39 S40 22 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 6) APPLICATION CIRCUIT LCD Panel C1-C16 S1-S40 VSS M CLK1 CLK2 VDD V1 V2 V3 V4 V5 DB0-DB7 S6A0065 SC1-S4C0 DL2 DL1 DL1 DR2 FCS CL1 SHL1 CL2 SHL2 M VSS VDD V6 V5 V4 V3 V2 V1 VEE VDD To MPU GND or Other voltage V1 V2 V3 V4 V5 VLCD (1/5 bias) S6A0069 S6A0065 OSC2 SC1-S4C0 DL2 DL1 DL1 DR2 FCS CL1 SHL1 CL2 SHL2 M VSS VDD V6 V5 V4 V3 V2 V1 VEE OSC1 V6 V5 V4 V3 S6A0065 V2 V1 VEE D SC1-S4C0 DL2 DL1 DL1 DR2 FCS SHL1 CL1 CL2 SHL2 VSS M VDD NOTE: When S6A0065 is externally connected to the S6A0069, you can increase the number of display digits up to 80 characteristics. 23 S6A0069 40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD BIAS VOLTAGE DIVIDE CIRCUIT 2) 1/5 bias, 1/16 duty 1) 1/4 bias, 1/8 or 1/11 duty VDD R R R R GND or Other voltage 24 VDD VDD V1 V2 V3 V4 V5 S6A0069 R R R R R GND or Other voltage VDD V1 V2 V3 V4 V5 S6A0069 16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 INITIALIZING When the power is turned on, S6A0069 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF(Busy Flag) is kept "High"(busy state) to the end of initialization. (1) Display Clear instruction: Write "20H" to all DDRAM (2) Set Functions instruction DL = 1 : 8-bit bus mode N = 1 : 2-line display mode F = 0 : 5 X 8 font type (3) Control Display ON/OFF instruction D = 0 : Display OFF C = 0 : Cursor OFF B = 0 : Blink OFF (4) Set Entry Mode instruction I/D = 1 : Increment by 1 SH = 0 : No entire display shift FRAME FREQUENCY Programmable Driving Method by the same font mask option: Display waveform A-Type, B-Type 1) 1/8 Duty Cycle A) A-Type Waveform 1-line selection period 1 2 3 4 ... 7 8 1 2 3 ... 7 8 VDD V1 ... COM1 ... ... V4 V5 B) B-Type Waveform VDD V1 ... COM1 V4 V5 Line selection period One Frame Frame frequency 1 Frame 1 Frame = 400 clocks = 400 x 8 x 3.7µs = 11850 µs = 11.9 ms (1 clock = 3.7 µs, fosc = 270kHz) = 1 / 11.9ms = 84.3Hz 25 S6A0069 16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) 1/11 duty cycle A) A-type Waveform 1-line selection period 1 2 3 4 ... 10 11 1 2 3 ... 10 11 VDD V1 ... COM1 ... ... V4 V5 B) B-type Waveform VDD V1 ... COM1 V4 V5 Line selection period One Frame Frame frequency 26 1 Frame 1 Frame = 400 clocks = 400 x 11 x 3.7µs = 16300µs = 16.3ms (1 clock = 3.7µs , fosc = 270kHz) = 1 / 16.3 ms = 61.4 Hz 16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 3) 1/16 duty cycle A) A-type Waveform 1-line selection period 1 2 3 4 ... 15 16 1 2 3 ... 15 16 VDD V1 ... COM1 ... ... V4 V5 B) B-type Waveform VDD V1 ... COM1 V4 V5 Line selection period One Frame Frame frequency 1 Frame 1 Frame = 200 clocks = 200 x 16 x 3.7µs = 11850 µs = 11.9 ms (1 clock = 3.7µs, fosc = 270kHz) = 1 / 11.9ms = 84.3Hz 27 S6A0069 16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INITIALIZING BY INSTRUCTION 1) 8-bit Interface Mode (Condition: fosc = 270kHz) Power On Wait for more than 30ms after D VD rises to 4.5 V. Wait for more than 40ms after D VD rises to 2.7 V. 0 1-line mode 1 2-line mode 0 Display OFF 1 Display ON 0 Display OFF 1 Display ON 0 Cursor OFF 1 Cursor ON 0 Blink OFF 1 Blink ON 0 Decrement mode 1 Increment mode 0 Entire shift off 1 Entire shift on N Function Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N F X X F Wait for more than 39 µs D Display ON/OFF Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C 0 0 0 0 0 0 1 D C B Wait for more than 39 µs B Display Clear RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 Wait for more than 1.53 sms I/D Entry Mode Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D SH Initialization End 28 SH 16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 2) 4-bit Interface Mode (Condition: fosc = 270kHz) Power On 0 4-bit mode 1 8-bit mode 0 1-line mode 1 2-line mode 0 Display off 1 Display on 0 Display off 1 Display on 0 Cursor off 1 Cursor on 0 Blink off 1 Blink on 0 Decrement mode 1 Increment mode 0 Entire shift off 1 Entire shift on D/L Wait for more than 30ms after D VD rises to 4.5 V. Wait for more than 40ms after D VD rises to 2.7 V. N Function Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 DL X X X X 0 0 0 0 1 0 X X X X 0 0 N F X X X X X X Wait for more than 39 µs F D Display ON/OFF Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 1 D C B X X X X C B Wait for more than 39 µs Display Clear RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 0 0 0 1 X X X X Wait for more than 1.53 ms Entry Mode Set RS 0 I/D R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 X X X X SH 0 0 0 1 I/D SH X X X X Initialization End 29 S6A0069 16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD MAXIMUM ABSOLUTE LIMIT Maximum Absolute Power Ratings Characteristic Symbol Unit Value Power Supply Voltage VDD V -0.3 to +7.0 LCD Drive Voltage VLCD V VDD-15.0 to VDD+0.3 VIN V -0.3 to VDD+ 0.3 Input Voltage .Voltage greater than above may damage the circuit (VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5) Temperature Characteristics Characteristic Symbol Unit Value Operating Temperature TOPR °C -30 to +85 Storage Temperature TSTG °C -55 to +125 30 16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 4.5V to 5.5V, Ta = -30 to +85°C) Characteristic Symbol Condition Min Typ Max Unit Operating Voltage VDD - 4.5 - 5.5 V Operating Current IDD Internal oscillation or external clock (VDD = 5.0V, fosc = 270kHz) - 0.35 0.6 mA Input Voltage (1) VIH1 - 2.2 - VDD (except OSC1) VIL1 - -0.3 - 0.6 Input Voltage (2) VIH2 - VDD-1.0 - VDD (OSC1) VIL2 - -0.2 - 1.0 Output Voltage (1) VOH1 IOH = -0.205mA 2.4 - - (DB0 to DB7) VOL1 IOL = 1.2mA - - 0.4 Output Voltage (2) VOH2 IO = -40µA 0.9VDD - - (except DB0 to DB7) VOL2 IO = 40µA - - 0.1VDD - - 1 - - 1 VIN = 0V to VDD -1 - 1 VIN = 0V, VDD = 5V (pull up) -50 -125 -250 Rf = 91kΩ ±2% (VDD = 5V) 190 270 350 kHz 125 270 350 kHz 45 50 55 % - - 0.2 µA 3.0 - 13.0 V Voltage Drop Input Leakage Current Input Low Current Internal Clock (external Rf) VdCOM VdSEG ILKG IIL f OSC1 IO = ±0.1mA duty - t R, t F LCD Driving Voltage VLCD V V V V f OSC External Clock V VDD-V5 (1/5, 1/4 bias) µA 31 S6A0069 16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD DC Characteristics (VDD = 2.7V to 4.5V, Ta = -30 to +85°C) Characteristic Symbol Condition Min Typ Max Unit Operating Voltage VDD - 2.7 - 4.5 V Operating Current IDD Internal oscillation or external clock (VDD = 3.0V, fosc = 270kHz) - 0.15 0.3 mA Input Voltage (1) VIH1 - 0.7 VDD - VDD (except OSC1) VIL1 - -0.3 - 0.55 Input Voltage (2) VIH2 - 0.7VDD - VDD (OSC1) VIL2 - - - 0.2 VDD Output Voltage (1) VOH1 IOH = -0.1mA 0.75 VDD - - (DB0 to DB7) VOL1 IOL = 0.1mA - - 0.2 VDD VOH2 IO = -40µA 0.8VDD - - VOL2 IO = 40µA - - 0.2VDD - - 1 - - 1 VIN = 0V VDD -1 - 1 VIN = 0V, VDD = 3V (pull up) -10 -50 -120 Rf = 75kΩ ±2% (VDD = 3V) 190 270 350 kHz 125 270 410 kHz 45 50 55 % - - 0.2 µS 3.0 - 13.0 V Output Voltage (2) (except DB0 to DB7) VdCOM Voltage Drop VdSEG Input Leakage Current ILKG IIL Input Low Current Internal Clock (external Rf) f OSC1 IO = ± 0.1mA duty - t R, t F VLCD LCD Driving Voltage VDD-V5 (1/5, 1/4 bias) NOTE: LCD Driving Voltage Duty 1/8, 1/11 Duty 1/16 Duty Bias 1/4 Bias 1/5 Bias VDD VDD VDD V1 VDD - VLCD/4 VDD - VLCD/5 V2 VDD - VLCD/2 VDD - 2VLCD/5 V3 VDD - VLCD/2 VDD - 3VLCD/5 V4 VDD - 3VLCD/4 VDD - 4VLCD/5 V5 VDD - VLCD VDD - VLCD Power 32 V V V V f OSC2 External Clock V µA 16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 AC Characteristics (VDD = 4.5 to 5.5V, Ta = -30 to +85°C) Mode Characteristics Symbol Min Typ Max tc 500 - - t R, t F - - 20 tw 230 - - R/W and RS Setup Time tsu1 40 - - R/W and RS Hold Time tH1 10 - - Data Setup Time tsu2 80 - - Data Hold Time tH2 10 - - E Cycle Time tc 500 - - t R, t F - - 20 E Pulse Width (High, Low) tw 230 - - R/W and RS Setup Time tsu 40 - - R/W and RS Hold Time tH 10 - - Data Output Delay Time tD - - 120 tDH 5 - - Symbol Min Typ Max tc 1000 - - t R, t F - - 25 tw 450 - - R/W and RS Setup Time tsu1 60 - - R/W and RS Hold Time tH1 20 - - Data Setup Time tsu2 195 - - Data Hold Time tH2 10 - - E Cycle Time tc 1000 - - t R, t F - - 25 E Pulse Width (High, Low) tw 450 - - R/W and RS Setup Time tsu 60 - - R/W and RS Hold Time tH 20 - - Data Output Delay Time tD - - 360 Data Hold Time tDH 5 - - E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) Write Mode (refer to Figure-6) E Rise / Fall Time Read Mode (refer to Figure-7) Data Hold Time Unit ns ns (VDD = 2.7 to 4.5V, Ta = -30 to +85°C) Mode Characteristic E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) Write Mode (refer to Figure-6) E Rise / Fall Time Read Mode (refer to Figure-7) Unit ns ns 33 S6A0069 16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD (VDD = 2.7 to 4.5V, Ta = -30 to +85°C) Mode Characteristic Symbol Min Typ tw 800 - Clock Rise / Fall Time t R, t F - - 25 Extension Driver Clock Setup Time tsu1 500 - - (refer to Figure-8) Data Setup Time tsu2 300 - - Data Hold Time tDH 300 - - M Delay Time tDM -1000 - 1000 Clock Pulse Width (High, Low) Interface Mode with RS VIH1 VIL1 tsu1 R/W Max - th1 VIL1 VIL1 th1 tw tf VIH1 VIL1 E tsu2 tr VIH1 VIL1 DB0-DB7 VIL1 th2 VIH1 VIL1 Valid Data tc Figure 6. Write Mode Timing Diagram RS R/W VIH1 VIL1 tsu th VIH1 VIH1 th tw tf VIH1 VIL1 E tr DB0-DB7 VIL1 tD VOH1 VOL1 tDH Valid Data tc Figure 7. Read Mode Timing Diagram 34 VOH1 VOL1 Unit ns 16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A0069 tf CLK1 VOH2 VOH2 tw tr CLK2 VOH2 VOL2 tw VOH2 VOL2 VOL2 tw tSU1 VOH2 VOL2 D tSU2 M tDH VOL2 tDM Figure 8. Interface Mode with Extension Driver Timing Diagram 35