ETC UC1608

HIGH-VOLTAGE MIXED-SIGNAL IC
128COM x 240SEG Matrix LCD Controller-Driver
Product Specification
Revision 0.52 Preview
July 24, 2002
ULTRACHIP
The Coolest LCD Driver. Ever!!
UC1608
128x240 Matrix LCD Controller-Drivers
Table Of Revision History
Version
Contents
Date of revision
0.52
First release
July 24,2002
(Revision 0.52 Preview)
1
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
Table of Content
Introduction ...........................................................................................................1
Ordering Information .............................................................................................2
Block Diagram.......................................................................................................3
Pin Description......................................................................................................4
Control Registers ..................................................................................................7
Command Summary .............................................................................................9
Command description .........................................................................................10
LCD Voltage Setting ...........................................................................................15
VLCD Quick Reference .........................................................................................16
LCD Display Controls..........................................................................................17
Host Interface .....................................................................................................19
Display Data RAM...............................................................................................20
Reset & Power Management ..............................................................................23
Absolute Maximum Ratings ................................................................................27
Specifications......................................................................................................28
AC Characteristics ..............................................................................................29
Physical Dimensions...........................................................................................32
Pad Coordinates .................................................................................................33
2
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
UC1608
Single-Chip, Ultra-Low Power
128COM x 240SEG Matrix
Passive LCD Controller-Driver
•
Support industry standard 8080 or 6800 bus
protocol in either 8-bit or 4-bit parallel
interface.
•
Support two multiplexing rates (128, 96).
•
This chip employs UltraChip’s unique DCC
(Direct Capacitor Coupling) driver architecture to
achieve near crosstalk free images.
Self-configuring 8x charge pump with onchip pumping capacitor requires only 5
external capacitors to operate.
•
In addition to low power COM and SEG drivers,
UC1608 contains all necessary circuits for high-V
LCD power supply, bias voltage generation,
timing generation and graphics data memory.
Flexible data addressing/mapping schemes
to support wide ranges of software models
and LCD layout placements.
•
Software programmable 4 temperature
compensation coefficients.
•
On-chip bypass capacitor for VLCD makes
VLCD bypass capacitor optional for small
LCD panels.
•
On-chip Power-ON Reset and Software
RESET commands, make RST pin optional.
•
VDD (digital) range: 2.4V ~ 3.3V
VDD (analog) range: 2.4V ~ 3.3V
6.5V ~ 15V
LCD VOP range:
•
Available in gold bump dies
Bump pitch: 50uM min.
Bump gap: 18uM min.
INTRODUCTION
UC1608 is an advanced high-voltage mixedsignal CMOS IC, especially designed for the
display needs of ultra-low power hand-held
devices.
Advanced circuit design techniques are
employed to minimize external component counts
and reduce connector size while achieving
extremely low power consumption.
MAIN APPLICATIONS
•
Cellular Phones, Smart Phones, PDA and
other battery operated palm top devices
and/or portable Instruments
FEATURE HIGHLIGHTS
•
Single chip controller-driver supports 128
COM x 240 SEG LCD, with vertical scroll.
(Revision 0.52 Preview)
1
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
ORDERING INFORMATION
Product ID
Description
UC1608xGAC
Gold bumped die.
UC1608xFAC
COF packaging.
General Notes
APPLICATION INFORMATION
For improved readability, the specification contains many application data points. When application information is given, it
is advisory and does not form part of the specification for the device.
BARE DIE DISCLAIMER
All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of
ninety (90) days from the date of UltraChip’s delivery. There is no post waffle saw/pack testing performed on individual die.
Although the latest modern processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers,
UltraChip has no control of third party procedures in the handling, packing or assembly of the die. Accordingly, it is the
responsibility of the customer to test and quality their application in which the die is to be used. UltraChip assumes no
liability for device functionality or performance of the die or systems after handling, packing or assembly of the die.
LIFE SUPPORT APPLICATIONS
These devices are not designed for use in life support appliances, or systems where malfunction of these products can
reasonably be expected to result in personal injuries. Customer using or selling these products for use in such
applications do so at their own risk.
2
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
BLOCK DIAGRAM
COM DRIVERS
LEVEL SHIFTER
DISPLAY DATA RAM
ROW ADDRESS GENERATOR
CONTROL &
STATUS
REGISTER
DATA RAM I/O BUFFER
CLOCK &
TIMING
GEN.
COLUMN ADDRESS GENERATOR
PAGE ADDRESS GENERATOR
POWER-ON
& RESET
CONTROL
DISPLAY DATA LATCHES
COMMAND
LEVEL SHIFTERS
HOST INTERFACE
SEG DRIVERS
VLCD & BIAS
GENERATOR
CB0
(Revision 0.52 Preview)
CB1
CB2
CLCD
CB3
3
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
PIN DESCRIPTION
Name
Type
Pins
Description
MAIN POWER SUPPLY
VDD
VDD2
VDD3
VDD2/VDD3 is the analog VDD and it should be connected to the same
power source. VDD is the digital VDD and is connected to a voltage
source that is the same, or lower than VDD2/VDD3.
PWR
VDD supplies for digital logic and display data RAM.
VDD2 supplies for VLCD and VBIAS generator, VDD3 supplies for other
analog circuits.
Minimize the trace resistance for VDD and VDD2.
VSS
VSS2
GND
Ground. Connect VSS and VSS2 to the shared GND pin.
Minimize the trace resistance for VSS and VSS2.
LCD POWER SUPPLY
VB3+ VB3–
VB2+ VB2–
VB1+ VB1–
VB0+ VB0–
PWR
LCD Bias Voltages. These are the voltage source to provide SEG
driving currents. These voltages are generated internally. Connect
capacitors of CBX value between VBX+ and VBX–.
The resistance of these four traces directly affects the SEG driving
strength of the resulting LCD module. Minimize the trace resistance is
critical in achieving high quality image.
The sensor pins for CBX capacitors. Please connect these sensor pins
as closely to proper CBX pads as possible. These signals can tolerate
input resistance of up to 2K Ohm, so, narrow COF traces can be used.
SB3+ SB3–
SB2+ SB2–
SB1+ SB1–
SB0+ SB0–
I
VLCD-IN
VLCD-OUT
PWR
However, the noise on these pins affects the accuracy of SEG driving
voltage level. To minimize noise caused by VBX-CBX charging current,
the trace resistance shared between VBX+/- and SBX+/- should be
minimized.
Main LCD Power Supply. Connect these pins together.
A by-pass capacitor CL is optional. When CL is used, connect CL
between VLCD and VSS, and keep the trace resistance under 300 Ohm.
NOTE
•
4
Recommended capacitor values:
CB: ~100x LCD load capacitance or 1.5uF (2V), whichever is higher.
CL: 10nF ~ 50nF (16V) is appropriate for most applications.
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
Name
Type
Pins
Description
HOST INTERFACE
BM[1:0]
I
Parallel/Serial.
4-bit bus modes: “LL”: 8080
8-bit bus modes: “HL”: 8080
CS
I
Chip Select. The chip is selected when CS=”H”. When the chip is not
selected, D[7:0] will be high impedance.
RST
I
“LH”: 6800
“HH”: 6800
When RST=”L”, all control registers are re-initialized by their default
states. Since UC1608 has built-in Power-ON-Reset and Software Reset
command, RST pin is not required for proper chip operation.
When RST pin is used, insert a 5~10K Ohm resistor to improve noise
filtering. When RST is not used, connect the pin to VDD.
CD
I
WR0
WR1
I
D0~D7
I/O
Select Command or Display Data for read/write operation.
”L”: Command
”H”: Display data
WR[1:0] controls the read/write operation of the host interface.
(Revision 0.52 Preview)
In parallel mode, WR[1:0] meaning depends on whether the interface is
in the 6800 mode or the 8080 mode.
Bi-directional bus for both serial and parallel host interfaces.
In 4-bit bus mode, connect unused pins to VDD or VSS.
5
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
Name
Type
Pins
Description
LCD DRIVER OUTPUT
SEG1 ~
SEG240
HV
SEG (column) driver outputs. Support up to 240 columns.
Leave unused drivers open-circuit.
COM1 ~
COM128
HV
COM (row) driver outputs. Support up to 128 rows. When Mux Rate is
not 128, please use only COM1~COM(x), x=128, or 96, and leave COM
(x+1) ~ COM128 open-circuit.
TST4
I
TST[3:1]
I/O
Test I/O pins. Leave these pins open circuit during normal use.
TP[3:1]
I
Test control. Leave these pins open circuit during normal use.
MISC. PINS
6
Test control. Connect to VSS.
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
CONTROL REGISTERS
UC1608 contains registers which control the chip operation. These registers can be modified by commands.
The following table is a summary of the control registers, their meaning and their default value. The
commands supported by UC1608 are described in the next two sections, first a summary table, followed by
a detailed description.
Name:
The Symbolic reference of the register byte.
Note that, some symbol names refer to collection of bits (flags) within one register byte.
Default:
Numbers shown in Bold fonts are values after Power-Up-Reset and System-Reset..
Name
Bits
Default
Description
SL
6
0H
Start Line. Mapping from COM1 to Display Data RAM.
CR
8
0H
Return Column Address. Useful for cursor implementation.
CA
8
0H
Display Data RAM Column Address
(Used in Host to Display Data RAM access)
PA
4
0H
BR
2
2H
Display Data RAM Page Address
(Used in Host to Display Data RAM access)
Bias Ratio. The ratio between VLCD and VBIAS.
00b= 10.7
01b= 11.3
11b= 12.7
10b=12.0
TC
2
0H
GN
2
3H
Temperature Compensation (per oC).
00b: 0.0%
01b: -0.05%
10b: -0.1%
11b: -0.2%
Gain, coarse setting of VBIAS and VLCD
PM
6
0H
Electronic Potentiometer to fine tune VBIAS and VLCD
MR
1
1H
Multiplexing Rate: Number of pixel rows:
0b: 96
1b: 128
OM
2
–
Operating Modes (Read Only)
10b: Sleep
11b: Normal
01b: (Not used)
00b: Reset
BZ
1
–
Busy with internal processes (reset, changing mode, etc.)
OK for Display RAM read/write access.
RS
1
–
Reset in progress, Host Interface not ready
PC
3
7H
Power Control and panel loading.
PC[0]:
0b: LCD: <20nF
1b: LCD: >20nF
11b: Internal VLCD
PC[2:1]: 00b: External VLCD
01b and 10b are reserved, for UltraChip only. Please do not use.
APC0
8
(Revision 0.52 Preview)
2CH
Advanced Product Configuration. For UltraChip only. Please do not use.
7
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
Name
Bits
Default
Description
DC
3
00H
Display Control:
DC[0]: PXV: Pixels Inverse (Default OFF)
DC[1]: APO: All Pixels ON (Default OFF)
DC[2]: Display ON/OFF (Default OFF).
AC
4
0H
Address Control:
AC[0]: WA: Automatic column/page Wrap Around (Default 0:OFF)
AC[1]: Reserved (always set to 0)
AC[2]: PID: PA (page address) auto increment direction (0: +1 1: -1)
AC[3]: CUM: Cursor update mode, (Default 0:OFF)
when CUM=1, CA increment on write only, wrap around suspended
LC
8
4
00H
LCD Mapping Control:
LC[0]: MSF: MSB First mapping Option
LC[1]: Reserved (always set to 0)
LC[2]: MX, Mirror X (Column sequence inversion)
LC[3]: MY, Mirror Y (Row sequence inversion)
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
COMMAND SUMMARY
The following is a list of host commands supported by UC1608
C/D:
W/R:
0: Control,
0: Write Cycle,
1: Data
1: Read Cycle
# Useful Data bits
– Don’t Care
Command
C/D W/R
D7
D6
D5
D4
D3
D2
D1
D0
Action
Default value
1
Write Data Byte
1
0
#
#
#
#
#
#
#
#
Write 1 byte
N/A
2
Read Data Byte
1
1
#
#
#
#
#
#
#
#
Read 1 byte
N/A
3
Get Status
Set Column Address LSB
0
0
1
0
BZ
0
MX
0
DE
0
RS
0
1
#
Get Status
Set CA[3:0]
N/A
0
Set Column Address MSB
Set Mux Rate and
temperature compensation.
0
0
0
0
0
1
#
#
#
#
Set CA[7:4]
0
0
0
0
1
0
0
#
#
#
Set {MR, TC[1:0]}
0
MR: 1
TC: 0
6
Set Power Control
7
Set Adv. Product Config.
(double byte command)
0
0
0
0
0
0
0
0
1
1
0
1
1
0
#
0
#
0
#
R
8
Set Start Line
0
0
0
0
#
0
#
1
#
#
#
#
#
#
#
#
#
#
#
#
Set SL[5:0]
0
9
Set Gain and Potentiometer
(double-byte command)
0
0
0
0
1
#
0
#
0
#
0
#
0
#
0
#
0
#
1
#
Set {GN[1:0],
PM[5:0]}
GN=3
PM=0
4
5
WA GN1 GN0
#
#
#
Set PC[2:0]
111b
For UltraChip only.
Do not use.
N/A
10 Set RAM Address Control
0
0
1
0
0
0
1
#
#
#
Set AC[2:0]
000b
11 Set All-Pixel-ON
12 Set Inverse Display
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
#
#
Set DC[1]
Set DC[0]
0=disable
0=disable
13 Set Display Enable
14 Set Page Address
0
0
0
0
1
1
0
0
1
1
0
1
1
#
1
#
1
#
#
#
Set DC[2]
Set PA[3:0]
0=disable
0
15 Set LCD Mapping Control
16 System Reset
0
0
0
0
1
1
1
1
0
1
0
0
#
0
#
0
#
1
#
0
Set LC[3:0]
System Reset
0
N/A
17 NOP
18 Set LCD Bias Ratio
0
0
0
0
1
1
1
1
1
1
0
0
0
1
0
0
1
#
1
#
No operation
Set BR[1:0]
N/A
10b=12
19 Reset Cursor Mode
20 Set Cursor Mode
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
1
AC[3]=0, CA=CR
AC[3]=1, CR=CA
N/A
N/A
0
0
0
0
1
#
1
#
1
#
0
#
0
#
1
#
#
#
For UltraChip only.
Do not use.
N/A
21
Set Test Control
(double byte command)
TT
* Other than commands listed above, all other bit patterns may result in undefined behavior.
(Revision 0.52 Preview)
9
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
COMMAND DESCRIPTION
(1) Write data to display memory
Action
Write data
C/D W/R D7
1
D6
0
D5
D4
D3
D2
D1
D0
8bits data write to SRAM
(2) Read data to display memory
Action
Read data
C/D W/R D7
1
D6
1
D5
D4
D3
D2
D1
D0
8bits data from SRAM
Write/Read Data Byte ( command 1,2 ) operations access display buffer RAM based on Page Address (PA)
register and Column Address (CA) register. To minimize bus interface cycles, PA and CA will be
incremented automatically depending on the setting of Access Control (AC) registers. PA and CA can also
be programmed directly by issuing Set Page Address and Set Column Address commands.
If Wrap-Around (WA) is OFF (AC[0] = 0), CA will stop increasing after reaching the end of page (MC), and
system programmers need to set the values of PA and CA explicitly. If WA is ON (AC[0]=1), when CA
reaches end of page, CA will be reset to 0 and PA will be increased or decrease by 1, depending on the
setting of Page Increment Direction (PID, AC[2]). When PA reaches the boundary of RAM (i.e. PA = 0 or 15),
PA will be wrapped around to the other end of RAM and continue.
(3) Get Status
Action
Get Status
C/D W/R D7
0
1
D6
D5
D4
D3
D2
D1
BZ MX DE RS WA GN1 GN0
D0
1
Status flag definitions:
BZ: Busy with internal process. When BZ=1 host interface can access if RS=0.
MX: Status of register LC[1], mirror X.
DE: Display enable flag. DE=1 when display enabled
RS: Reset in progress. If RS=1.host interface will be inaccessible.
WA: status of register AC[0] .automatic column/page wrap around.
GN0,1:GN[1:0] .register Gain
(4) Set Column Address
Action
Set Column Address LSB CA[3:0]
C/D W/R D7
0
0
0
D6
D5
D4
0
0
0
D3
D2
D1
D0
CA3 CA2 CA1 CA0
0
0
0
1 CA7 CA6 CA5 CA4
Set Column Address MSB CA[7:4]
0
0
Set the SRAM column address before Write/Read memory from host interface.
CA possible value=0-239
10
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
(5) Set Multiplex Rate and Temperature Compensation
Action
C/D W/R D7
D6
D5
D4
D3
Set Multiplex Rate MR
0
0
0
0
1
0
Set Temperature Compensation TC[1:0]
Set the multiplex ratio (number of rows) and temperature compensation.
MUX ratio definition:
0b=96
0
D2
D1
D0
MR TC1 TC0
1b=128
Temperature compensation curve definition:
00b= -0.00%/C
01b= -0.05%/C
10b= -0.10%/C
11b= -0.20%/C
(6) Set Power Control
Action
C/D W/R D7
D6
0
0
Set Panel Loading PC[2:0]
0
0
Set PC[0] according to the capacitance loading of LCD panel.
0b: <=20nF
D5
D4
D3
1
0
1
D2
D1
D0
PC2 PC1 PC0
1b: >20nF
Set PC[2:1] to program to use internal charge pump of external VLCD source:
00b=External VLCD
11b=Internal VLCD
(7) Set Advance Product Configuration
Action
Set APC
(Double byte command)
C/D W/R D7
0
0
0
0
0
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0
0
R
D1
D0
APC register parameter
For UltraChip only. Please Do NOT use.
(8) Set Start Line
Action
Set Start Line SL[5:0]
Set the start line number
C/D W/R D7
0
0
0
D6
1
D5
D4
D3
D2
SL5 SL4 SL3 SL2 SL1 SL0
Start line setting will scroll the displayed image up by SL rows. The valid value is between 0 (no
scrolling) and 63. One example of the visual effect on LCD is illustrated in the figure below.
0
Image row 0
0
Image row N
……….
……….
Image row 127
N
Image row N
……….
N
Image row 0
………
image row N-1
Image row 127
SL=0
(Revision 0.52 Preview)
SL=N
11
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
(9) Set Gain and Potentiometer
Action
C/D W/R D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
0
1
Set Gain and Potentiometer
0
0
GN [1:0] PM [5:0]
0
0 GN1 GN0 PM5 PM4 PM3 PM2 PM1 PM0
(Double byte command)
Program Gain (GN[1:0]) and Potentiometer (PM[5:0]). See section LCD VOLTAGE SETTING for more detail.
Effective range of GN = 0 ~ 3
PM value = 0 ~ 63
(10) Set RAM Address Control
Action
Set AC [2:0]
C/D W/R D7
0
0
1
D6
D5
D4
D3
0
0
0
1
D2
D1
D0
AC2 AC1 AC0
Program registers AC[2:0] for RAM address control.
AC[0] - WA, Automatic column/page wrap around.
0: CA or PA (depends on AC[1]= 0 or 1) will stop incrementing after reaching boundary
1: CA or PA (depends on AC[1]= 0 or 1) will restart, and PA or CA will increment by one step.
AC[1] – Auto-Increment order
0 : column (CA) increment (+1) first until CA reach CA boundary, then PA will increment by (+/-1).
1 : page (PA) increment (+/-1) first until PA reach PA boundary, then CA will increment by (+1) .
AC[2] – PID, page address (PA) auto increment direction ( 0/1 = +/- 1 )
When WA=1, controls whether page address will be adjusted by +1 or -1, when CA reached CA
boundary. No effect when WA=0.
CA boundary is 240 and PA boundary is 15 when PID=0, PA boundary is 0 when PID=1.
(11) Set All Pixel ON
Action
C/D W/R D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
1
0 DC1
Set All Pixel On DC [1]
0
0
Set DC[1] to force all SEG drivers to output ON signals. This function has no effect on the existing data
stored in display RAM.
(12) Set Inverse Display
Action
C/D W/R D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
1
1 DC0
Set Inverse Display DC [0]
0
0
Set DC[0] to force all SEG drivers to output the inverse of the data stored in display memory. This function
has no effect on the existing data stored in display RAM.
(13) Set Display Enable
Action
C/D W/R D7
Set Display Enable DC[2]
0
0
This command is for programming registers DC[2].
1
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
DC2
When DC[2] is set to 0, the IC will put itself into Sleep mode. All drivers, voltage generation circuit and timing
circuit will be halted to conserve power. When DC[2] is set to 1, UC1608 will first exit from Sleep mode,
restore the power and then turn on COM drivers and SEG drivers. There is no other explicit user action or
timing sequence required to enter or exit the Sleep mode.
12
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
(14) Set Page Address
Action
C/D W/R D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1 PA3 PA2 PA1 PA0
Set Page Address LSB PA [3:0]
0
0
Set the SRAM page address before write/read memory from host interface.
Effective range of value = 0 ~ 15
(15) Set LCD Mapping Control
Action
C/D W/R D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0 MY MX Set LCD Mapping Control LC[3:0]
0
0
MSF
Set LC[3:0] for COM (row) mirror (MY), SEG (column) mirror (MX) and MSB first or LSB first options (MSF).
MY is implemented by reversing the mapping order between RAM and COM (row) electrodes. The data
stored in RAM is not affected by MY command. MY will have immediate effect on the display image.
MX is implemented by selecting the CA or 239-CA as write/read (from host interface) display RAM
column address so this function will only take effect after rewriting the RAM data
MSF is implemented by MSB-LSB swapping. When MSB first (LC[0] ) bit is set, data D[7:0] will be realigned as D[0:7] then be stored to RAM.
(16) System Reset
Action
C/D W/R D7
D6
D5
D4
D3
D2
D1
1
1
1
0
0
0
1
System Reset
0
0
This command will activate the system reset. The system will take about 5ms to reset
D0
0
(17) NOP
Action
C/D W/R D7
No operation
0
This command is used for “no operation”.
0
1
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
0
1
1
D6
D5
D4
D3
D2
D1
D0
1
1
0
1
0
D3
D2
(18) Set LCD Bias Ratio
Action
C/D W/R D7
Set Bias Ratio BR [1:0]
Bias ratio definition:
00b= 10.7
01b=11.3
0
0
1
10b=12.0
BR1 BR0
11b=12.7
(19) Reset Cursor Mode
Action
C/D W/R D7
D6
D5
D4
D1
1
1
1
0
1
1
1
Return to Cursor. AC[3]=0, CA=CR
0
0
This command is used to reset cursor update mode function. See description below.
(Revision 0.52 Preview)
D0
0
13
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
(20) Set Cursor Mode
Action
C/D W/R D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
1
1
1
1
Set AC[3]=1 CR=CA
0
0
Set Cursor Mode command is used to turn on cursor update mode function. AC[3] will be set to 1, register
CR will be set to the value of register CA
When AC[3]=1, column address (CA) will only increment with write RAM operation but not on read RAM
operation. The address CA wraps around will also be suspended no matter what WA setting is. The
purpose of this combination of features is to support “Read-Modify-Write” for cursor implementation.
Reset Cursor Mode command will clear cursor update mode flag (AC[3]=0), CA will be restored to previous
CA value which is stored in CR, and CA, PA increment will return to its normal condition.
(21) Set Test Control
Action
Set TT
(Double byte command)
C/D W/R D7
0
0
1
D6
D5
D4
D3
D2
1
1
0
0
1
D1
D0
TT
0
0
Testing parameter
This command is used for UltraChip production testing. For UltraChip Only. Please do not use.
14
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
LCD VOLTAGE SETTING
MULTIPLEX RATES
VLCD GENERATION
Multiplex Rates (MR) is software programmable.
Two MR is supported: 96, 128.
VLCD may be supplied either by internal charge
pump or by external power supply. The source of
VLCD is controlled by PC[2:1]. For good product
performance it is recommended to keep VLCD under
13V at room temperature.
BIAS RATIO SELECTION
Bias Ratio (BR) is defined as the ratio between
VLCD and VBIAS, i.e.
BR = VLCD /VBIAS,
where VBIAS = VB1+ – VB1– = VB0+ – VB0–.
The theoretical optimum Bias Ratio can be
estimated by Mux + 1 . In some applications, BR
is set to be 10~15% lower than the optimum value
calculated above in order to lower VLCD by 5~6%.
Such setting generally will not cause visible change
in image quality.
UC1608 supports four BR as listed below. BR can
be selected by software program.
BR
0
1
2
3
Bias Ratio
10.7
11.3
12
12.7
Four (4) different temperature compensation
coefficients can be selected via software. The four
coefficients are given below:
o
where
CV0 and CPM are two constants, whose value
depends on the BR-GN register setting. The
values are provided in the table on the next
page,
PM is the numerical value of PM register,
CT is the temperature compensation coefficient
as selected by TC register.
TEMPERATURE COMPENSATION
% per C
V LCD = (CV 0 + C PM × PM ) × (1 + (T − 25) × CT %)
T is the ambient temperature in OC, and
Table 2: Bias Ratios
TC
When VLCD is generated internally, the voltage level
of VLCD is determined by four control registers: BR
(Bias Ratio), GN (Gain), PM (Potentiometer), and
TC (Temperature Compensation), with the
following relationship:
0
1
2
3
0.0
–0.05
–0.10
–0.20
LOAD DRIVING STRENGTH
The power supply circuit of UC1608 is designed to
handle LCD panels with load capacitance up to
~20nF when VDD2 = 2.5V. For larger LCD panels
use higher VDD and COF packaging.
Table 4: Temperature Compensation
(Revision 0.52 Preview)
15
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
VLCD QUICK REFERENCE
20.00
19.50
19.00
18.50
18.00
17.50
17.00
16.50
16.00
15.50
15.00
14.50
14.00
13.50
13.00
12.50
12.00
11.50
11.00
0
1
2
3
0
1
10.7
2
3
0
11.3
1
2
3
12
0
1
2
3
12.7
BR-GN
BR
10.7
11.3
12
12.7
GN
CV0 (V)
CPM (mV)
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
11.240
12.304
13.527
14.888
11.943
13.073
14.372
15.818
12.645
13.842
15.217
16.749
13.348
14.611
16.063
17.679
17.90
19.59
21.54
23.71
19.02
20.82
22.89
25.19
20.14
22.04
24.23
26.67
21.25
23.27
25.58
28.15
VLCD Range (V)
11.240
12.304
13.527
14.888
11.943
13.073
14.372
15.818
12.645
13.842
15.217
16.749
13.348
14.611
16.063
17.679
12.368
13.538
14.884
16.381
13.141
14.384
15.814
17.405
13.914
15.230
16.744
18.429
14.687
16.076
17.674
19.453
Note: For best product reliability keep VLCD under 15.5V under all temperature.
16
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
LCD DISPLAY CONTROLS
CLOCK & TIMING GENERATOR
ALL PIXELS ON (APO)
UC1608 contains a built-in system clock. All
required components for the clock oscillator are
built-in. No external parts are required.
When set, this flag will force all active SEG drivers
to output On signals, disregarding the data stored
in the display buffer.
DRIVER MODES
This flag has no effect when Display Enable is OFF
and it has no effect on data stored in RAM.
COM and SEG drivers can be in either Idle mode
or Active mode, controlled by Display Enable flag
(DC[2]). When COM drivers are in idle mode, their
outputs are high-impedance (open circuit). When
SEG drivers are in idle mode, their outputs are
connected to VSS.
DRIVER ARRANGEMENTS
The naming conventions are: COM(x), where
x=1~128, refers to the COM driver for the x-th row
of pixels on the LCD panel.
The mapping of COM(x) to LCD pixel rows is the
same for all MR, MX and MY settings. When MR is
not 128, then COM(x) ~ COM128 (X = MR+1)
should be left open circuit.
DISPLAY CONTROLS
There are three groups of display control flags in
the control register DC: Driver Enable (DE), AllPixel-ON (APO) and Inverse (PXV). DE has the
overriding effect over PXV and APO.
DRIVER ENABLE (DE)
Driver Enable is controlled by the value of DC[2].
When DE is set to OFF (logic “0”), both SEG and
COM drivers will become idle and UC1608 will put
itself into Sleep mode to conserve power.
When DE is set to ON, UC1608 will first exit from
Sleep mode, restore the power (VLCD, VBIAS etc.)
and then turn on COM and SEG drivers.
(Revision 0.52 Preview)
INVERSE (PXV)
When this flag is set to ON, active SEG drivers will
output the inverse of the value it received from the
display buffer RAM (bit-wise inversion). This flag
has no impact on data stored in RAM.
SCROLLING
SL register can be used to implement scroll
function. Setting SL to a non-zero value N will
result in the image being scrolled by N lines.
ITO LAYOUT CONSIDERATIONS FOR COM SIGNALS
Since UC1608 line rate is as fast as 10KHz and the
common scanning pulse is only 100us wide, it is
critical to minimize the RC delay experienced by
common electrodes.
It is recommended to optimize the ITO layout to
limit the worst case common electrode RC delay as
calculated below:
(RROW /3 + RCOM + ROUT) x CROW < 2uS
where
CROW :
LCD loading capacitance of one row
of pixels.
RROW :
ITO resistance over one row of
pixels within the active area
RCOM:
ITO resistance leading from COF
OLD to the active area
ROUT:
UC1608 output, 1.5K Ohm typical
17
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
RAM
W/R
POL
COM1
COM2
COM3
SEG1
SEG2
Fig. 4 COM and SEG Driving Waveform
18
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
HOST INTERFACE
Designers can either use parallel bus to achieve
high data transfer rate.
As summarized in the table below, UC1608
supports two parallel bus protocols, in either 8-bit
of 4-bit bus width.
Control Pins &
Data Pins
Bus Type
Width
Access
BM[1:0]
8080
8-bit
4-bit
8-bit
Read/Write
00
11
10
___
WR0
6800
___
01
__
_
WR
WR1
4-bit
_
R/W
__
EN
RD
D[7:4]
Data
–
Data
–
D[3:0]
Data
Data
Data
Data
* Connect unused control pins and data bus pins to VDD or VSS
Table 5: Host interfaces Choices
There is no pipeline in write interface of Display
RAM. Data is transferred directly from bus buffer
to internal RAM on the rising edges of write
pulses.
PARALLEL INTERFACE
The timing relationship between UC1608 internal
control signal RD, WR and their associated bus
actions are shown in the figure below.
8-BIT & 4-BIT BUS OPERATION
The Display RAM read interface is implemented
as a two-stage pipe-line. This architecture
requires that, every time memory address is
modified, either in 8-bit mode or 4-bit mode, by
either Set CA, or Set PA command, a dummy
read cycle need to be performed before the
actual data can propagate through the pipe-line
and be read from data port D[7:0].
UC1608 supports both 8-bit and 4-bit bus width.
The bus width is determined by pin BM[1].
4-bit bus operation exactly doubles the clock
cycles of 8-bit bus operation, MSB followed by
LSB, including the dummy read, which also
requires two clock cycles.
External
CD
___
WR
__
RD
D[7:0]
LLSB
DL
DL+K
CMSB
CLSB
Dummy
DC
DC+1
MMSB
MLSB
Internal
Write
Read
Data
Latch
Column
Address
DL
L
L+K
DL+K
L+K+1
Dummy
C
DC
C+1
DC+1
C+2
DC+2
C+3
M
Figure 5: 8 bit Parallel Interface & Related Internal Signals
(Revision 0.52 Preview)
19
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
DISPLAY DATA RAM
DATA ORGANIZATION
The display data is 1-bit per pixel and stored in a
dual port static RAM (RAM, for Display Data RAM).
The RAM size is 128x240 for UC1608. This array
of data bits is further organized into pages of 8 bit
slices to facilitate parallel bus interface.
When Mirror X (MX, LC[2]) is OFF, the 1st column
of LCD pixels will correspond to the bits of the first
byte of each page, the 2nd column of LCD pixels
correspond to the bits of the second byte of each
page, etc.
MSB FIRST OR LSB FIRST
There are two options to map D[7:0] to RAM, MSB
first (MSF=1), or LSB first (MSF=0), as illustrated in
next page.
DISPLAY DATA RAM ACCESS
The memory used in UC1608 Display Data RAM
(RAM) is a special purpose dual port RAM which
20
allows asynchronous access to both its column and
row data. Thus, RAM can be independently
accessed both for Host Interface and for display
operations.
DISPLAY DATA RAM ADDRESSING
A Host Interface (HI) memory access operation
starts with specifying Page Address (PA) and
Column Address (CA) by issuing Set Page Address
and Set Column Address commands.
If wrap-around (WA, AC[0]) is OFF (0), CA will stop
increasing after reaching the end of page (239),
and system programmers need to set the values of
PA and CA explicitly.
If WA is ON (1), when CA reaches end of page, CA
will be reset to 0 and PA will increment or
decrement, depending on the setting of Page
Increment Direction (PID, AC[2]). When PA
reaches the boundary of RAM (i.e. PA = 0 or 19),
PA will be wrapped around to the other end of RAM
and continue.
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
0
1
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
MY=0
SL=0 SL=16
Page 0
Page 1
Page 2
Page 3
Page 14
0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG236
SEG237
SEG238
SEG239
SEG240
SEG239
SEG238
SEG237
SEG236
SEG235
SEG234
SEG233
SEG5
SEG4
SEG3
SEG2
SEG1
MX
SEG240
Page 15
1
MSF
SL=0
MY=1
SL=0 SL=16 SL=16
COM1
COM113 COM128
COM96
COM16
---
COM2
COM114 COM127
COM95
COM15
---
COM3
COM115 COM126
COM94
COM14
---
COM4
COM116 COM125
COM93
COM13
---
COM5
COM117 COM124
COM92
COM12
---
COM6
COM118 COM123
COM91
COM11
---
COM7
COM19
COM122
COM90
COM10
---
COM8
COM120 COM121
COM89
COM9
---
COM9
COM121 COM120
COM88
COM8
---
COM10
COM122 COM119
COM87
COM7
---
COM11
COM123 COM118
COM86
COM6
---
COM12
COM124 COM117
COM85
COM5
---
COM13
COM125 COM116
COM84
COM4
---
COM14
COM126 COM115
COM83
COM3
---
COM15
COM127 COM114
COM82
COM2
---
COM16
COM128 COM113
COM81
COM1
---
COM17
COM1
COM112
COM80
COM128
---
COM18
COM2
COM111
COM79
COM127
---
COM19
COM3
COM110
COM78
COM126
---
COM20
COM4
COM109
COM77
COM125
---
COM21
COM5
COM108
COM76
COM124
---
COM22
COM6
COM107
COM75
COM123
---
COM23
COM7
COM106
COM74
COM122
---
COM24
COM8
COM105
COM73
COM121
---
COM25
COM9
COM104
COM72
COM120
COM96
COM26
COM10
COM103
COM71
COM119
COM95
COM27
COM11
COM102
COM70
COM118
COM94
COM28
COM12
COM101
COM69
COM117
COM93
COM29
COM13
COM100
COM68
COM116
COM92
COM30
COM14
COM99
COM67
COM115
COM91
COM31
COM15
COM98
COM66
COM114
COM90
COM32
COM16
COM97
COM65
COM113
COM89
COM113
COM97
COM16
---
COM32
---
COM114
COM98
COM15
---
COM31
---
COM115
COM99
COM14
---
COM30
---
COM116 COM100
COM13
---
COM29
---
COM117 COM101
COM12
---
COM28
---
COM118 COM102
COM11
---
COM27
---
COM19
COM103
COM10
---
COM26
---
COM120 COM104
COM9
---
COM25
---
COM121 COM105
COM8
---
COM24
---
COM122 COM106
COM7
---
COM23
---
COM123 COM107
COM6
---
COM22
---
COM124 COM108
COM5
---
COM21
---
COM125 COM109
COM4
---
COM20
---
COM126 COM110
COM3
---
COM19
---
COM127 COM111
COM2
---
COM18
---
COM128 COM112
COM1
---
COM17
128
96
---
128
MUX
96
Example for memory mapping: let MX = 0, MY = 0, SL = 0, MSF = 0, according to the data shown in the
above table:
⇒
Page 0 SEG 1: 00011110b
⇒
Page 0 SEG 2: 01111000b
(Revision 0.52 Preview)
21
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
MX IMPLEMENTATION
Column Mirroring (MX) is implemented by selecting
either (CA) or (239–CA) as the RAM column
address. Changing MX affects the data written to
the RAM.
Since MX has no effect on data already stored in
RAM, changing MX does not have immediate effect
on the displayed pattern. To refresh the display,
refresh the data stored in RAM after setting MX.
DISPLAY SCANNING
During each field of display, depending on the
setting of MR, COM electrodes will be scanned in a
fixed pattern at a rate of
(Frame Rate x Mux Rate) rows/second.
sequence and the following RAM address
generation formula.
During the display operation, the RAM line address
generation can be mathematically represented as
following:
For the 1st line period of each field
Line = SL
Otherwise
Line = Mod(Line+1, 128)
Where Mod is the modular operator, and Line is the
bit slice line address of RAM to be outputted to
SEG drivers. Line 0 corresponds to the first bit-slice
of data in RAM.
The above Line generation formula produces the
“loop around” effect as it effectively resets Line to 0
when Line+1 reaches 128.
During each row period, the signal at the SEG
drivers determines the ON/OFF status of the row of
pixels being scanned.
Effects such as page scrolling can be emulated by
changing SL dynamically.
ROW SCANNING
MY IMPLEMENTATION
For each field, the scanning starts at COM1
through COMx, where x depends on the setting of
MR.
Row Mirroring (MY) is implemented by reversing
the mapping order between COM electrodes and
RAM, i.e. the mathematical address generation
formula becomes:
COM electrode scanning (row scanning) orders are
not affected by Start Line (SL) or Mirror Y (MY,
LC[3]). When MY is 0, the effect of SL having a
value K is to change the mapping of COM1 to the
K-th bit slice of data stored in display RAM. Visually,
SL having a non-zero value is equivalent to
scrolling LCD display up by SL rows.
RAM ADDRESS GENERATION
The mapping of the data stored in the display
SRAM and the scanning electrodes can be
obtained by combining the fixed Row scanning
22
For the 1st line period of each field
Line = Mod(SL + MUX-1, 128)
where MUX = 96 or 128.
Otherwise
Line = Mod(Line-1 , 128)
Visually, the effect of MY is equivalent to flipping
the display upside down. The data stored in display
RAM is not affected by MY.
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
RESET & POWER MANAGEMENT
TYPES OF RESET
CHANGING OPERATION MODE
UC1608 has two different types of Reset:
Power-ON-Reset and System-Reset.
In addition to Power-ON-Reset, two commands will
initiate OM transitions:
Power-ON-Reset is performed right after VDD is
connected to power. Power-On-Reset will first wait
for about ~15mS, depending on the time required
for VDD to stabilize, and then trigger the System
Reset.
System Reset can also be activated by software
command or by connecting RST pin to ground. In
the following discussions, Reset means System
Reset.
RESET STATUS
When UC1608 enters RESET sequence:
•
Operation mode will be “Reset”
•
System Status bits RS and BZ will stay as “1”
until the Reset process is completed. When
RS=1, the IC will only respond to Read Status
command. All other commands are ignored.
•
All control registers are reset to default values.
Refer to Control Registers for details of their
default values.
OPERATION MODES
UC1608 has three operating modes (OM):
Reset, Normal, Sleep.
Mode
Reset
Sleep Normal
OM
Host Interface
Clock
LCD Drivers
Charge Pump
Draining Circuit
00
Active
OFF
OFF
OFF
ON
10
Active
OFF
OFF
OFF
OFF
11
Active
ON
ON
ON
OFF
Set Display Enable, and System Reset.
When DC[2] is modified by Set Display Enable, OM
will be updated automatically. There is no other
action required to enter Sleep mode.
For maximum energy utilization, Sleep mode is
designed to retain charges stored in external
capacitors CB0, CB1, and CL. To drain these
capacitors, use Reset command to activate the onchip draining circuit.
Action
Mode
OM
Set Driver Enable to “0”
Set Driver Enable to “1”
Reset command or
RST_ pin pulled “L”
Power ON reset
Sleep
Normal
10
11
Reset
00
Table 12: OM changes
Even though UC1608 consumes very little energy
in Sleep mode (typically 5uA or less), however,
since all capacitors are still charged, the leakage
through COM drivers may damage the LCD over
the long term. It is therefore recommended to use
Sleep mode only for brief Display OFF operations,
such as full-frame screen updates, and to use
RESET for extended screen OFF operations.
EXITING SLEEP MODE
UC1608 contains internal logic to check whether
VLCD and VBIAS are ready before releasing COM
and SEG drivers from their idle states. When
exiting Sleep or Reset Mode, COM and SEG
drivers will not be activated until UC1608 internal
voltage sources are restored to their proper values.
Table 11: Operating Modes
(Revision 0.52 Preview)
23
ULTRACHIP
©1999-2002
High-Voltage Mixed-Signal IC
POWER-UP SEQUENCE
UC1608 power-up sequence is simplified by built-in
“Power Ready” flags and the automatic invocation
of System-Reset command after Power-ON-Reset.
System programmers are only required to wait 15~
20 ms before the CPU starting to issue commands
to UC1608. No additional time sequences are
required between enabling the charge pump,
turning on the display drivers, writing to RAM or
any other commands.
POWER-DOWN SEQUENCE
To prevent the charge stored in capacitors CBX+,
CBX–, and CL from damaging the LCD when VDD is
switched off, use Reset mode to enable the built-in
draining circuit and discharge these capacitors.
The draining resistor is 1K Ohm for both VLCD and
VB+. It is recommended to wait 3 x RC for VLCD and
1.5 x RC for VB+. For example, if CL is 10nF, then
the draining time required for VLCD is 1~2mS.
When internal VLCD is not used, UC1608 will NOT
drain VLCD during RESET. System designers need
to make sure external VLCD source is properly
drained off before turning off VDD.
Turn on VDD
Reset command
Wait 15~20 mS
Wait 1~2 mS
Set LCD Bias Ratio (BR)
Set Gain (GN)
Set Potential Meter (PM)
Turn off VDD
Set Display Enable
Figure 12: Reference Power-Up Sequence
24
Figure 13: Reference Power-Down Sequence
Revision 0.52
UC1608
128x240 Matrix LCD Controller-Drivers
SAMPLE POWER COMMAND SEQUENCES
The following tables are examples of command sequence for power-up, power-down and display ON/OFF
operations. These are only to demonstrate some “typical, generic” scenarios. Designers are encouraged to
study related sections of the datasheet and find out what the best parameters and control sequences are for
their specific design needs.
C/D
The type of the interface cycle. It can be either Command (0) or Data (1)
W/R
The direction of data flow of the cycle. It can be either Write (0) or Read (1).
Type
Required:
Customer:
Advanced:
Optional:
These items are required
These item are not necessary if customer parameters are the same as default
We recommend new users to skip these commands and use default values.
These commands depend on what users want to do.
POWER-UP
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Chip action
R
C
–
0
–
0
–
0
–
0
–
1
–
0
–
0
–
#
–
#
– Automatic Power-ON-Reset.
# (5) Set MR and TC
C
0
0
1
1
0
0
#
#
#
# (15) Set LCD Mapping
C
R
0
0
0
1
.
.
1
0
0
0
0
0
.
.
0
0
1
1
#
#
.
.
#
1
1
0
#
#
.
.
#
0
1
0
#
#
.
.
#
1
0
0
#
#
.
.
#
0
1
0
#
#
.
.
#
1
0
0
#
#
.
.
#
1
#
0
#
#
.
.
#
1
#
1
#
#
.
.
#
1
C
R
Comments
Wait ~20ms after VDD is ON
Set up LCD specific
parameters such as format,
MX, MY, MSF, etc.
(18) Set Bias Ratio
(9) Set Gain & PM
Write display RAM
Set up display image
(13) Set Display Enable
POWER-DOWN
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
R
R
0
–
0
–
1
–
(Revision 0.52 Preview)
1
–
1
–
0
–
0
–
0
–
1
–
Chip action
0 (16) System Reset
– Draining capacitor
Comments
Wait 1~2ms before VDD OFF
25
ULTRACHIP
©1999~2002
High-Voltage Mixed-Signal IC
BRIEF DISPLAY-OFF
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Chip action
Comments
R
C
0
0
1 0 1 0 1 1 1 0 (13) Set Display Disable
1
0
# # # # # # # # Write display RAM
Set up display image (Image
update is optional. Data in
.
.
. . . . . . . .
the RAM is retained through
.
.
. . . . . . . .
the SLEEP state.)
1
0
# # # # # # # #
R
0
0
1 0 1 0 1 1 1 1 (13) Set Display Enable
* This is only recommended for very brief display OFF (under 10mS).
If image becomes unstable use the Extended Display OFF approach shown below.
EXTENDED DISPLAY-OFF
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Chip action
R
–
0
–
0
–
1
–
1
–
1
–
0
–
0
–
0
–
1
–
0 (16)System Reset.
–
–
C
C
–
1
.
.
1
0
–
0
.
.
0
0
–
#
.
.
#
0
–
#
.
.
#
0
–
#
.
.
#
1
–
#
.
.
#
0
–
#
.
.
#
0
–
#
.
.
#
#
–
#
.
.
#
#
–
# Write display RAM
.
.
#
# (5) Set MR and TC
C
0
0
1
1
0
0
#
#
#
# (15) Set LCD Mapping
C
C
Comments
CB1, CB1, CLCD discharged.
Extended display OFF
Zzzz...
System waking up
Set up display image (Image
update is optional. Data in
the RAM is retained through
the RESET state.)
Set up LCD specific
parameters such as format,
MX, MY, MSF, etc.
0
0
1 1 1 0 1 0 # # (18) Set Bias Ratio
0
0
1 0 0 0 0 0 0 1
(9) Set Gain & PM
0
0
# # # # # # # #
R
0
0
1 0 1 0 1 1 1 1 (13) Set Display Disable
* The sequence is basically the same as the power up sequence, except Power-ON RESET is replaced by
System RESET command, and an extended idle time in between.
26
UC1608
128x240 Matrix LCD Controller-Drivers
ABSOLUTE MAXIMUM RATINGS
In accordance with IEC134, note 1,2 and 3.
Symbol
Min.
Max.
Unit
VDD
Logic Supply voltage
-0.3
+4.0
V
VDD2
LCD Generator Supply voltage
-0.3
+4.0
V
VDD3
Analog Circuit Supply voltage
-0.3
+4.0
V
VLCD
LCD Generated voltage (-30OC ~ +80OC)
-0.3
+17.0
V
Any input voltage
-0.4
VDD + 0.5
VIN
Parameter
V
TOPR
Operating temperature range
-30
+85
o
TSTR
Storage temperature
-55
+125
o
C
C
Notes
1.
VDD based on VSS = 0V
2.
Stress values listed above may cause permanent damages to the device.
(Revision 0.52 Preview)
27
ULTRACHIP
©1999~2002
High-Voltage Mixed-Signal IC
SPECIFICATIONS
DC CHARACTERISTICS
Symbol
Parameter
VDD
Supply for digital circuit
VDD2/3
Supply for bias & pump
VLCD
Charge pump output
VDD2/3 >= 2.4V, 25 C
LCD data voltage
VDD2/3 >= 2.4V, 25OC
VIL
Input logic LOW
VIH
Input logic HIGH
VOL
Output logic LOW
VOH
Output logic HIGH
Min.
Typ.
Max.
Unit
2.4
2.8
3.6
V
2.4
2.8
3.6
V
O
VD
12.5
15
V
1.2
V
0.2VDD
V
0.2VDD
V
0.8VDD
V
0.8VDD
V
IIL
Input leakage current
1.5
µA
CIN
Input capacitance
5
10
PF
Output capacitance
5
10
PF
COUT
R0(SEG)
R0(COM)
fLINE
28
Conditions
SEG output impedance
VLCD = 12.5V
1.5
3
kΩ
COM output impedance
VLCD = 12.5V
1.5
3
kΩ
Average frame rate
90
Hz
UC1608
128x240 Matrix LCD Controller-Drivers
AC CHARACTERISTICS
CD
tAH80
tAS80
CS
tCY80
tCSSA80
tPWR80, tPWW80
tCSH80
tCSSD80
tHPW80
WR0
tDH80
tDS80
Write
D[X]
tACC80
tOD80
Read
D[X]
Figure 21: Parallel Bus Timing Characteristics (for 8080 MCU)
o
(VDD=2.4V to 3.3V, Ta= –30 to +85 C)
Symbol
Signal
tAS80
tAH80
tCY80
CD
tPWR80
WR1
tPWW80
WR0
tHPW80
WR0, WR1
tDS80
tDH80
tACC80
tOD80
tCSSA80
tCSSD80
tCSH80
D0~D7
(Revision 0.52 Preview)
CS
Description
Address setup time
Address hold time
System cycle time
8 bits bus
(read)
(write)
4 bits bus
(read)
(write)
Pulse width 8 bits (read)
4 bits
Pulse width 8 bits (write)
4 bits
High pulse width
8 bits bus (read)
(write)
4 bits bus (read)
(write)
Data setup time
Data hold time
Read access time
Output disable time
Chip select setup time
Condition
Min.
Max.
Units
0
10
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
50
50
ns
140
140
80
80
65
35
65
35
CL = 100pF
65
65
35
35
30
10
–
10
10
10
20
ns
29
ULTRACHIP
©1999~2002
High-Voltage Mixed-Signal IC
CD
tAS68
tAH68
CS
tCSSA68
tCY68
tPWR68, tPWW68
tCSH68
tCSSD68
tLPW68
WR0
tDS68
tDH68
Write
D[7:0]
tACC68
tOD68
Read
D[7:0]
Figure 22: Parallel Bus Timing Characteristics (for 6800 MCU)
o
(VDD=2.4V to 3.3V, Ta= –30 to +85 C)
Symbol
Signal
Description
tAS68
tAH68
tCY68
CD
Address setup time
Address hold time
System cycle time
8 bits bus
(read)
(write)
4 bits bus
(read)
(write)
Pulse width 8 bits (read)
4 bits
Pulse width 8 bits (write)
4 bits
Low pulse width
8 bits bus (read)
(write)
4 bits bus (read)
(write)
Data setup time
Data hold time
Read access time
Output disable time
Chip select setup time
tPWR68
WR1
tPWW68
tLPW68
tDS68
tDH68
tACC68
tOD68
TCSSA68
TCSSD68
TCSH68
30
D0~D7
CS
Condition
Min.
Max.
Units
0
10
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
50
50
ns
140
140
80
80
65
35
65
35
CL = 100pF
65
65
35
35
30
10
–
10
10
10
20
ns
UC1608
128x240 Matrix LCD Controller-Drivers
tRW
RST
Figure 25: Reset Characteristics
o
(VDD=2.4V to 3.3V, Ta= –30 to +85 C)
Symbol
Signal
tRW
RST
(Revision 0.52 Preview)
Description
Reset low pulse width
Condition
Min.
Max.
Units
1000
–
ns
31
ULTRACHIP
High-Voltage Mixed-Signal IC
PHYSICAL DIMENSIONS
CHIP SIZE
12.603X 1.248mm
DIE THICKNESS:
0.5mm
AU BUMP HEIGHT:
17μm ±1μm (within die)
AU BUMP PITCH:
50μm
AU BUMP SIZE:
94 x 32μm
94 x 51μm
106 x 48μm
DUMMY BUMP SIZE:
94 x 57μm
106 x 48μm
PAD COORDINATES:
Pad center
PAD ORIGIN:
Chip center
(Drawing and coordinates are
for the Circuit/Bump view.)
32
©1999~2002
UC1608
128x240 Matrix LCD Controller-Drivers
COF INFORMATION
58.53± 0.2 (C ut-line)
D0
W R1
2
W R0
TS T4
D2
19.8(PI W indow)
2.4
5
M odified the text comment
Added Note 9.
2
New version
VLCD
VS S
D5
D7
0.7
"A"
1
CL
4
2?
IC
1.42
1
4
0
2 1
0.8 M AX.
(Include IC)
80
3
1.
SCALE 1:1
UC 1 6 0 8
2
REV
SHT 2 of 2
FA
UC 1608 CO F Package Drawing
PRO JECTION
DR AW ING NO.
TITLE
372
Alvin
U LTR AC HIPIN C.
P0.168x65=10.92
,W =0.088
34
Jack
Alvin
DFTG . CHK. AP PVL.
06/18/2002
Jack
Date
06/11/2002
NC
57.39± 0.2 (S/R)
"C"
1.27
P0.138x119=16.422
,W =0.07 0.168
D3
CS
P1.15x16=18.4,W =0.6
CD
"B"
D4
1
BM0
U N IT SH O W N FR O M C O PPER SIDE
VB 0+
19.8(PI W indow)
D6
69.95± 0.12
D1
Revise Describtion
4
3
2
1
BM1
57.39 (Alignm ent m ark)
VDD
58.53± 0.2 (C ut-line)
RS T
CL
15.56 (Resin area)
VDD2,3
47.6 (Alignm ent Hole)
NC
2
VB 1+
29.265 (IC C enter)
3
NC
3
VB1-
P0.138x119=16.422
,W =0.07
"D"
VB 2+
4
VB 3+
P1.15x16=18.4,W =0.6
VB2-
M ETAL(Cu)
NC
PO LYIM IDE
NC
SO LDER RESIST
P0.168x65=10.92
,W =0.088
0.168
1
1
NC
D
C
7.188 (IC center)
6.152 (Alignm ent hole)
1.5 (PI window)
0.914
0.362
4
4.73 (Resin area)
VB0-
4.75
1.42
15.497 (S/R)
2.353
D
C
B
A
33
(Revision 0.52 Preview)
B
A
19.85 ± 0.2 (Cut-line)
5S.Px4.75=23.75
VB3-
ULTRACHIP
D
0.088
0.09
4
1.12
1.288
0.57
0.06
Detail "A"
0.4 SQ
3
0.336
Detail "B"
0.045
0.336
CL
0.635
0.2048
0.06
0.379
0.579
0.783
0.983
0.276
0.035
372
34
0.1722
0.2408
0.3857
0.044
0.088
NC
0.7354
0.45
UNIT SHOW N FROM COPPER SIDE
3
0.3857
0.175
NC
0.07
Com127
0.3024
0.1024
0.225
Detail "D"
Com125
0.025(Space)
Com5
0.09
0.025(W idth)
Seg240
2
UC1608 IC
Com1
Com3
0.27
0.09
0.025
0.025
0.585
Detail "C"
Com122
1.155
Com4
Com2
Seg1
0.050(Pitch)
1
Com128
C
B
A
1
Com126
Com124
4
5
Revise Describtion
4
2
2
1
No.
Solder Resist
Copper
Base Film
Material
Component List
3
1
U LTRAC HIP INC.
1
SCALE 1:1
UC 1 6 0 8
2
REV
SHT 1 of 2
FA
UC1608 COF Package Drawing
PRO JECTION
DRAWING NO.
TITLE
Plating
Alvin
APP VL.
4
Jack
Alvin
DFTG. CHK.
06/18/2002
Jack
Date
Modified the text comment
Added Note 9.
06/11/2002
3
2
New version
2
1
D
C
B
A
34
NC
NC
NC
NC
NC
VB3VB3+
VB2VB2+
VB1VB1+
VB0VB0+
VLCD
VSS
VDD2,3
VDD
NC
NC
D7
D6
D5
D4
D3
D2
D1
D0
W R1
W R0
CD
RST
TST4
CS
BM0
BM1
NC
©1999~2002
High-Voltage Mixed-Signal IC
COF INFORMATION
UC1608
128x240 Matrix LCD Controller-Drivers
PAD COORDINATES
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Name
Dummy
COM37
COM35
COM33
COM31
COM29
COM27
COM25
COM23
COM21
COM19
COM17
COM15
COM13
COM11
COM9
COM7
COM5
COM3
COM1
Dummy
COM39
COM41
COM43
COM45
COM47
COM49
COM51
COM53
COM55
COM57
COM59
COM61
COM63
COM65
COM67
COM69
COM71
COM73
COM75
COM77
COM79
COM81
COM83
COM85
COM87
X
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6185.5
-6006.1
-5946.6
-5896.6
-5846.6
-5796.6
-5746.6
-5696.6
-5646.6
-5596.6
-5546.6
-5496.6
-5446.6
-5396.6
-5346.6
-5296.6
-5246.6
-5196.6
-5146.6
-5096.6
-5046.6
-4996.6
-4946.6
-4896.6
-4846.6
-4796.6
(Revision 0.52 Preview)
Y
-509.5
-450.0
-400.0
-350.0
-300.0
-250.0
-200.0
-150.0
-100.0
-50.0
0.0
50.0
100.0
150.0
200.0
250.0
300.0
350.0
400.0
450.0
509.5
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
W
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
51
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
H
57
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
57
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
Pin
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Name
COM89
COM91
COM93
COM95
COM97
COM99
COM101
COM103
COM105
COM107
COM109
COM111
COM113
COM115
COM117
COM119
COM121
COM123
COM125
COM127
TST2
TST3
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
X
-4746.6
-4696.6
-4646.6
-4596.6
-4546.6
-4496.6
-4446.6
-4396.6
-4346.6
-4296.6
-4246.6
-4196.6
-4146.6
-4096.6
-4046.6
-3996.6
-3946.6
-3896.6
-3846.6
-3796.6
-3746.6
-3687.1
-3351.9
-3226.9
-3102.0
-2977.0
-2852.0
-2727.0
-2602.1
-2477.1
-2352.1
-2227.1
-2102.2
-1977.2
-1852.2
-1727.2
-1602.3
-1477.3
-1352.3
-1227.3
-1102.4
-977.4
-852.4
-727.4
-602.5
-477.5
Y
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
W
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
51
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
H
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
35
ULTRACHIP
©1999~2002
High-Voltage Mixed-Signal IC
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
36
Name
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
BM1
BM0
CS
TST4
RST
CD
WR0
WR1
D0
D1
D2
D3
D4
D5
D6
D7
VDD
VDD2
VDD3
VSS2
VSS
TP1
TP2
TP3
VLCDOUT
VLCDIN
TST1
VB0+
SB0+
VB0SB0VB1+
SB1+
VB1SB1VB2+
SB2+
VB2SB2VB3+
SB3+
X
-352.5
-227.5
-102.6
22.4
147.4
272.4
397.4
1198.7
1268.7
1338.7
1408.7
1478.7
1548.7
1618.7
1688.7
1758.7
1828.7
1898.7
1968.7
2038.7
2108.7
2178.7
2248.7
2342.0
2412.0
2482.0
2552.0
2622.0
2696.7
2746.7
2796.7
2846.7
2896.7
2946.7
2996.7
3046.7
3096.7
3146.7
3196.7
3246.7
3296.7
3346.7
3396.7
3446.7
3496.7
3546.7
3596.7
3646.7
Y
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-544.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-515.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
W
106
106
106
106
106
106
106
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
H
48
48
48
48
48
48
48
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
106
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
Name
VB3SB3COM128
COM126
COM124
COM122
COM120
COM118
COM116
COM114
COM112
COM110
COM108
COM106
COM104
COM102
COM100
COM98
COM96
COM94
COM92
COM90
COM88
COM86
COM84
COM82
COM80
COM78
COM76
COM74
COM72
COM70
COM68
COM66
COM64
COM62
COM60
COM58
COM56
COM54
COM52
COM50
COM48
COM46
COM44
COM42
COM40
Dummy
X
3696.7
3746.7
3796.7
3846.7
3896.7
3946.7
3996.7
4046.7
4096.7
4146.7
4196.7
4246.7
4296.7
4346.7
4396.7
4446.7
4496.7
4546.7
4596.7
4646.7
4696.7
4746.7
4796.7
4846.7
4896.7
4946.7
4996.7
5046.7
5096.7
5146.7
5196.7
5246.7
5296.7
5346.7
5396.7
5446.7
5496.7
5546.7
5596.7
5646.7
5696.7
5746.7
5796.7
5846.7
5896.7
5946.7
6006.2
6185.5
Y
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-521.0
-509.5
W
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
51
94
H
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
57
Product Specifications
UC1608
128x240 Matrix LCD Controller-Drivers
Pin
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
Name
COM38
COM36
COM34
COM32
COM30
COM28
COM26
COM24
COM22
COM20
COM18
COM16
COM14
COM12
COM10
COM8
COM6
COM4
COM2
Dummy
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
X
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
6185.5
5984.5
5925.0
5875.0
5825.0
5775.0
5725.0
5675.0
5625.0
5575.0
5525.0
5475.0
5425.0
5375.0
5325.0
5275.0
5225.0
5175.0
5125.0
5075.0
5025.0
4975.0
4925.0
4875.0
4825.0
4775.0
4725.0
4675.0
4625.0
(Revision 0.52 Preview)
Y
-450.0
-400.0
-350.0
-300.0
-250.0
-200.0
-150.0
-100.0
-50.0
0.0
50.0
100.0
150.0
200.0
250.0
300.0
350.0
400.0
450.0
509.5
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
W
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
51
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
H
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
57
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
Pin
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
Name
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
X
4575.0
4525.0
4475.0
4425.0
4375.0
4325.0
4275.0
4225.0
4175.0
4125.0
4075.0
4025.0
3975.0
3925.0
3875.0
3825.0
3775.0
3725.0
3675.0
3625.0
3575.0
3525.0
3475.0
3425.0
3375.0
3325.0
3275.0
3225.0
3175.0
3125.0
3075.0
3025.0
2975.0
2925.0
2875.0
2825.0
2775.0
2725.0
2675.0
2625.0
2575.0
2525.0
2475.0
2425.0
2375.0
2325.0
2275.0
2225.0
Y
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
W
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
H
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
37
ULTRACHIP
©1999~2002
High-Voltage Mixed-Signal IC
Pin
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
38
Name
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
X
2175.0
2125.0
2075.0
2025.0
1975.0
1925.0
1875.0
1825.0
1775.0
1725.0
1675.0
1625.0
1575.0
1525.0
1475.0
1425.0
1375.0
1325.0
1275.0
1225.0
1175.0
1125.0
1075.0
1025.0
975.0
925.0
875.0
825.0
775.0
725.0
675.0
625.0
575.0
525.0
475.0
425.0
375.0
325.0
275.0
225.0
175.0
125.0
75.0
25.0
-25.0
-75.0
-125.0
-175.0
Y
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
W
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
H
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
Pin
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
Name
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
SEG132
SEG133
SEG134
SEG135
SEG136
SEG137
SEG138
SEG139
SEG140
SEG141
SEG142
SEG143
SEG144
SEG145
SEG146
SEG147
SEG148
SEG149
SEG150
SEG151
SEG152
SEG153
SEG154
SEG155
SEG156
SEG157
SEG158
SEG159
SEG160
SEG161
SEG162
SEG163
SEG164
SEG165
SEG166
SEG167
SEG168
SEG169
SEG170
SEG171
SEG172
X
-225.0
-275.0
-325.0
-375.0
-425.0
-475.0
-525.0
-575.0
-625.0
-675.0
-725.0
-775.0
-825.0
-875.0
-925.0
-975.0
-1025.0
-1075.0
-1125.0
-1175.0
-1225.0
-1275.0
-1325.0
-1375.0
-1425.0
-1475.0
-1525.0
-1575.0
-1625.0
-1675.0
-1725.0
-1775.0
-1825.0
-1875.0
-1925.0
-1975.0
-2025.0
-2075.0
-2125.0
-2175.0
-2225.0
-2275.0
-2325.0
-2375.0
-2425.0
-2475.0
-2525.0
-2575.0
Y
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
W
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
H
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
Product Specifications
UC1608
128x240 Matrix LCD Controller-Drivers
Pin
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
Name
SEG173
SEG174
SEG175
SEG176
SEG177
SEG178
SEG179
SEG180
SEG181
SEG182
SEG183
SEG184
SEG185
SEG186
SEG187
SEG188
SEG189
SEG190
SEG191
SEG192
SEG193
SEG194
SEG195
SEG196
SEG197
SEG198
SEG199
SEG200
SEG201
SEG202
SEG203
SEG204
SEG205
SEG206
SEG207
SEG208
SEG209
SEG210
SEG211
SEG212
SEG213
SEG214
SEG215
SEG216
SEG217
SEG218
SEG219
SEG220
X
-2625.0
-2675.0
-2725.0
-2775.0
-2825.0
-2875.0
-2925.0
-2975.0
-3025.0
-3075.0
-3125.0
-3175.0
-3225.0
-3275.0
-3325.0
-3375.0
-3425.0
-3475.0
-3525.0
-3575.0
-3625.0
-3675.0
-3725.0
-3775.0
-3825.0
-3875.0
-3925.0
-3975.0
-4025.0
-4075.0
-4125.0
-4175.0
-4225.0
-4275.0
-4325.0
-4375.0
-4425.0
-4475.0
-4525.0
-4575.0
-4625.0
-4675.0
-4725.0
-4775.0
-4825.0
-4875.0
-4925.0
-4975.0
(Revision 0.52 Preview)
Y
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
W
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
H
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
Pin
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
Name
SEG221
SEG222
SEG223
SEG224
SEG225
SEG226
SEG227
SEG228
SEG229
SEG230
SEG231
SEG232
SEG233
SEG234
SEG235
SEG236
SEG237
SEG238
SEG239
SEG240
X
-5025.0
-5075.0
-5125.0
-5175.0
-5225.0
-5275.0
-5325.0
-5375.0
-5425.0
-5475.0
-5525.0
-5575.0
-5625.0
-5675.0
-5725.0
-5775.0
-5825.0
-5875.0
-5925.0
-5984.5
Y
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
521.0
W
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
51
H
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
39