ST
Sitronix
ST7558
65 x 102 Dot Matrix LCD Controller/Driver
1. INTRODUCTION
The ST7558 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 102 segment
and 65 common with 1 ICOM driver circuits. This chip is connected directly to a microprocessor, accepts 4-line serial
2
interface (SPI), I C interface or 8-bit parallel interface, display data can stores in an on-chip display data RAM of 66 x
102 bits. It performs display data RAM read/write operation with no external operating clock to minimize power
consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a display
system with the fewest components.
2. FEATURES
-
Driver Output Circuits
(external clock also possible)
102 segment outputs / 65 common outputs
On-chip Display Data Ram
-
Capacity: 66X102=6732 bits
-
Voltage converter (x2, x3, x4, x5)
-
Voltage regulator (temperature gradient
Microprocessor Interface
-
-
-0.05%/°C)
8-bit parallel bi-directional interface with
-
Voltage follower
6800-series or 8080-series
-
On-chip electronic contrast control function (128
-
2
External RESB (reset) pin
Generation of LCD supply voltage (externally
Vout voltage supply is possible)
-
Logic supply voltage range VDD -VSS
-
Generation of intermediate LCD bias voltages
6800 , 8080 , 4-Line
(without I2C interface)
ST7558i
I2C interface
1/56
1.8 to 3.3V
Temperature range: -30 to +85 degree
ST7558
Ver 2.3
Liquid crystal driving voltage :
V0 -VSS = max 12 V (external power supply)
I C (Inter-Integrated Circuit) Interface
On-chip Low Power Analog Circuit
-
stepsX2)
4-line SPI (serial peripheral interface) available
(only write operation)
-
Oscillator requires no external components
2005/10/05
ST7558
3. PAD Arrangement (COG)
Chip Size: 10,220 um × 1000 um
Bump Pitch:
PAD NO 1 ~ 148 , 250 ~ 272 : 75.5 um (com/seg)
PAD NO 248 ~ 249 : 93.5 um
PAD NO 149 ~ 248 : 75 um (I/O)
PAD NO 148 ~ 149 : 114 um
PAD NO 249 ~ 250 : 95.9 um
Bump Size:
PAD NO 1 ~ 125 , 137 ~ 248 , 250 ~ 261 : 55(x) um × 60(y) um
PAD NO 126 ~ 136
PAD NO 249 : 92(x) um × 60(y) um
, 262 ~ 272 : 60(x)um × 55(y) um
Bump Height: 17 um
Chip Thickness: 635 um
60
6
15
75
75
6
Metal area
Bump area
(-4766,410)
unit: um
15
6
6
30
30
15
30
60
15
30
(4766,410)
unit:um
Mark
1
125
126
272
Y
X
(0,0)
136
262
137
261
248 249 250
RES
30
15
30
15
55
10
15
60
55
60
30
75
Bump Size of
Top & Bottom
30
75
92
60
Bump Size of
Right & Left
(-4763,-410)
unit:um
Ver 2.3
60
Bump Size of
RES
unit: um
2/56
10
15
60
(4763,-410)
unit:um
2005/10/05
ST7558
Pad Center Coordinates(NORMAL,MY=0)
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
1
COM[42]
4681.0
389.0
36
SEG[23]
2038.5
389.0
2
COM[41]
4605.5
389.0
37
SEG[24]
1963.0
389.0
3
COM[40]
4530.0
389.0
38
SEG[25]
1887.5
389.0
4
COM[39]
4454.5
389.0
39
SEG[26]
1812.0
389.0
5
COM[38]
4379.0
389.0
40
SEG[27]
1736.5
389.0
6
COM[37]
4303.5
389.0
41
SEG[28]
1661.0
389.0
7
COM[36]
4228.0
389.0
42
SEG[29]
1585.5
389.0
8
COM[35]
4152.5
389.0
43
SEG[30]
1510.0
389.0
9
COM[34]
4077.0
389.0
44
SEG[31]
1434.5
389.0
10
COM[33]
4001.5
389.0
45
SEG[32]
1359.0
389.0
11
COM[32]
3926.0
389.0
46
SEG[33]
1283.5
389.0
12
Reserve
3850.5
389.0
47
SEG[34]
1208.0
389.0
13
SEG[0]
3775.0
389.0
48
SEG[35]
1132.5
389.0
14
SEG[1]
3699.5
389.0
49
SEG[36]
1057.0
389.0
15
SEG[2]
3624.0
389.0
50
SEG[37]
981.5
389.0
16
SEG[3]
3548.5
389.0
51
SEG[38]
906.0
389.0
17
SEG[4]
3473.0
389.0
52
SEG[39]
830.5
389.0
18
SEG[5]
3397.5
389.0
53
SEG[40]
755.0
389.0
19
SEG[6]
3322.0
389.0
54
SEG[41]
679.5
389.0
20
SEG[7]
3246.5
389.0
55
SEG[42]
604.0
389.0
21
SEG[8]
3171.0
389.0
56
SEG[43]
528.5
389.0
22
SEG[9]
3095.5
389.0
57
SEG[44]
453.0
389.0
23
SEG[10]
3020.0
389.0
58
SEG[45]
377.5
389.0
24
SEG[11]
2944.5
389.0
59
SEG[46]
302.0
389.0
25
SEG[12]
2869.0
389.0
60
SEG[47]
226.5
389.0
26
SEG[13]
2793.5
389.0
61
SEG[48]
151.0
389.0
27
SEG[14]
2718.0
389.0
62
SEG[49]
75.5
389.0
28
SEG[15]
2642.5
389.0
63
SEG[50]
0.0
389.0
29
SEG[16]
2567.0
389.0
64
SEG[51]
-75.5
389.0
30
SEG[17]
2491.5
389.0
65
SEG[52]
-151.0
389.0
31
SEG[18]
2416.0
389.0
66
SEG[53]
-226.5
389.0
32
SEG[19]
2340.5
389.0
67
SEG[54]
-302.0
389.0
33
SEG[20]
2265.0
389.0
68
SEG[55]
-377.5
389.0
34
SEG[21]
2189.5
389.0
69
SEG[56]
-453.0
389.0
35
SEG[22]
2114.0
389.0
70
SEG[57]
-528.5
389.0
Ver 2.3
3/56
2005/10/05
ST7558
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
71
SEG[58]
-604.0
389.0
107
SEG[94]
-3322.0
389.0
72
SEG[59]
-679.5
389.0
108
SEG[95]
-3397.5
389.0
73
SEG[60]
-755.0
389.0
109
SEG[96]
-3473.0
389.0
74
SEG[61]
-830.5
389.0
110
SEG[97]
-3548.5
389.0
75
SEG[62]
-906.0
389.0
111
SEG[98]
-3624.0
389.0
76
SEG[63]
-981.5
389.0
112
SEG[99]
-3699.5
389.0
77
SEG[64]
-1057.0
389.0
113
SEG[100]
-3775.0
389.0
78
SEG[65]
-1132.5
389.0
114
SEG[101]
-3850.5
389.0
79
SEG[66]
-1208.0
389.0
115
COMS1
-3926.0
389.0
80
SEG[67]
-1283.5
389.0
116
COM[0]
-4001.5
389.0
81
SEG[68]
-1359.0
389.0
117
COM[1]
-4077.0
389.0
82
SEG[69]
-1434.5
389.0
118
COM[2]
-4152.5
389.0
83
SEG[70]
-1510.0
389.0
119
COM[3]
-4228.0
389.0
84
SEG[71]
-1585.5
389.0
120
COM[4]
-4303.5
389.0
85
SEG[72]
-1661.0
389.0
121
COM[5]
-4379.0
389.0
86
SEG[73]
-1736.5
389.0
122
COM[6]
-4454.5
389.0
87
SEG[74]
-1812.0
389.0
123
COM[7]
-4530.0
389.0
88
SEG[75]
-1887.5
389.0
124
COM[8]
-4605.5
389.0
89
SEG[76]
-1963.0
389.0
125
COM[9]
-4681.0
389.0
90
SEG[77]
-2038.5
389.0
126
COM[10]
-4998.5
381.5
91
SEG[78]
-2114.0
389.0
127
COM[11]
-4998.5
306.0
92
SEG[79]
-2189.5
389.0
128
COM[12]
-4998.5
230.5
93
SEG[80]
-2265.0
389.0
129
COM[13]
-4998.5
155.0
94
SEG[81]
-2340.5
389.0
130
COM[14]
-4998.5
79.5
95
SEG[82]
-2416.0
389.0
131
COM[15]
-4998.5
4.0
96
SEG[83]
-2491.5
389.0
132
COM[16]
-4998.5
-71.5
97
SEG[84]
-2567.0
389.0
133
COM[17]
-4998.5
-147.0
98
SEG[85]
-2642.5
389.0
134
COM[18]
-4998.5
-222.5
99
SEG[86]
-2718.0
389.0
135
COM[19]
-4998.5
-298.0
100
SEG[87]
-2793.5
389.0
136
COM[20]
-4998.5
-373.5
101
SEG[88]
-2869.0
389.0
137
COM[21]
-4694.5
-389.0
102
SEG[89]
-2944.5
389.0
138
COM[22]
-4619.0
-389.0
103
SEG[90]
-3020.0
389.0
139
COM[23]
-4543.5
-389.0
104
SEG[91]
-3095.5
389.0
140
COM[24]
-4468.0
-389.0
105
SEG[92]
-3171.0
389.0
141
COM[25]
-4392.5
-389.0
106
SEG[93]
-3246.5
389.0
142
COM[26]
-4317.0
-389.0
Ver 2.3
4/56
2005/10/05
ST7558
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
143
COM[27]
-4241.5
-389.0
179
D2
-1500.0
-389.0
144
COM[28]
-4166.0
-389.0
180
D1
-1425.0
-389.0
145
COM[29]
-4090.5
-389.0
181
D1
-1350.0
-389.0
146
COM[30]
-4015.0
-389.0
182
D0
-1275.0
-389.0
147
COM[31]
-3939.5
-389.0
183
D0
-1200.0
-389.0
148
Reserve
-3864.0
-389.0
184
VDD
-1125.0
-389.0
149
T9
-3750.0
-389.0
185
T0
-1050.0
-389.0
150
VDD
-3675.0
-389.0
186
T1
-975.0
-389.0
151
VDD
-3600.0
-389.0
187
T2
-900.0
-389.0
152
VDD
-3525.0
-389.0
188
T3
-825.0
-389.0
153
VDD
-3450.0
-389.0
189
T4
-750.0
-389.0
154
VDD
-3375.0
-389.0
190
T5
-675.0
-389.0
155
VDD
-3300.0
-389.0
191
T6
-600.0
-389.0
156
VDD2
-3225.0
-389.0
192
T7
-525.0
-389.0
157
VDD2
-3150.0
-389.0
193
T8
-450.0
-389.0
158
VDD2
-3075.0
-389.0
194
VRS
-375.0
-389.0
159
VDD2
-3000.0
-389.0
195
ERD
-300.0
-389.0
160
VDD2
-2925.0
-389.0
196
ERD
-225.0
-389.0
161
VDD2
-2850.0
-389.0
197
RWR
-150.0
-389.0
162
VDD2
-2775.0
-389.0
198
RWR
-75.0
-389.0
163
VDD2
-2700.0
-389.0
199
A0
0.0
-389.0
164
VDD2
-2625.0
-389.0
200
A0
75.0
-389.0
165
VDD2
-2550.0
-389.0
201
CS
150.0
-389.0
166
VDD2
-2475.0
-389.0
202
CS
225.0
-389.0
167
VDD2
-2400.0
-389.0
203
IMS
300.0
-389.0
168
D7
-2325.0
-389.0
204
VDD
375.0
-389.0
169
D7
-2250.0
-389.0
205
PS
450.0
-389.0
170
D6
-2175.0
-389.0
206
T11
525.0
-389.0
171
D6
-2100.0
-389.0
207
T10
600.0
-389.0
172
D5
-2025.0
-389.0
208
VDD
675.0
-389.0
173
D5
-1950.0
-389.0
209
OSC
750.0
-389.0
174
D4
-1875.0
-389.0
210
OSC
825.0
-389.0
175
D4
-1800.0
-389.0
211
V0
900.0
-389.0
176
D3
-1725.0
-389.0
212
V0
975.0
-389.0
177
D3
-1650.0
-389.0
213
V0
1050.0
-389.0
178
D2
-1575.0
-389.0
214
V0
1125.0
-389.0
Ver 2.3
5/56
2005/10/05
ST7558
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
215
V1
1200.0
-389.0
244
VLCDOUT
3375.0
-389.0
216
V2
1275.0
-389.0
245
VLCDOUT
3450.0
-389.0
217
V3
1350.0
-389.0
246
VLCDOUT
3525.0
-389.0
218
V4
1425.0
-389.0
247
VLCDOUT
3600.0
-389.0
219
VSS2
1500.0
-389.0
248
VLCDOUT
3675.0
-389.0
220
VSS2
1575.0
-389.0
249
RES
3768.5
-389.0
221
VSS2
1650.0
-389.0
250
COMS2
3864.5
-389.0
222
VSS2
1725.0
-389.0
251
COM[64]
3940.0
-389.0
223
VSS2
1800.0
-389.0
252
COM[63]
4015.5
-389.0
224
VSS2
1875.0
-389.0
253
COM[62]
4091.0
-389.0
225
VSS2
1950.0
-389.0
254
COM[61]
4166.5
-389.0
226
VSS2
2025.0
-389.0
255
COM[60]
4242.0
-389.0
227
VSS2
2100.0
-389.0
256
COM[59]
4317.5
-389.0
228
VSS2
2175.0
-389.0
257
COM[58]
4393.0
-389.0
229
VSS2
2250.0
-389.0
258
COM[57]
4468.5
-389.0
230
VSS2
2325.0
-389.0
259
COM[56]
4544.0
-389.0
231
VSS
2400.0
-389.0
260
COM[55]
4619.5
-389.0
232
VSS
2475.0
-389.0
261
COM[54]
4695.0
-389.0
233
VSS
2550.0
-389.0
262
COM[53]
4998.5
-373.5
234
VSS
2625.0
-389.0
263
COM[52]
4998.5
-298.0
235
VSS
2700.0
-389.0
264
COM[51]
4998.5
-222.5
236
VSS
2775.0
-389.0
265
COM[50]
4998.5
-147.0
237
VLCDIN
2850.0
-389.0
266
COM[49]
4998.5
-71.5
238
VLCDIN
2925.0
-389.0
267
COM[48]
4998.5
4.0
239
VLCDIN
3000.0
-389.0
268
COM[47]
4998.5
79.5
240
VLCDIN
3075.0
-389.0
269
COM[46]
4998.5
155.0
241
VLCDIN
3150.0
-389.0
270
COM[45]
4998.5
230.5
242
VLCDIN
3225.0
-389.0
271
COM[44]
4998.5
306.0
243
VLCDOUT
3300.0
-389.0
272
COM[43]
4998.5
381.5
Ver 2.3
6/56
2005/10/05
ST7558
Pad Center Coordinates(REVERSE,MY=1)
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
1
COM[22]
4681.0
389.0
36
SEG[23]
2038.5
389.0
2
COM[23]
4605.5
389.0
37
SEG[24]
1963.0
389.0
3
COM[24]
4530.0
389.0
38
SEG[25]
1887.5
389.0
4
COM[25]
4454.5
389.0
39
SEG[26]
1812.0
389.0
5
COM[26]
4379.0
389.0
40
SEG[27]
1736.5
389.0
6
COM[27]
4303.5
389.0
41
SEG[28]
1661.0
389.0
7
COM[28]
4228.0
389.0
42
SEG[29]
1585.5
389.0
8
COM[29]
4152.5
389.0
43
SEG[30]
1510.0
389.0
9
COM[30]
4077.0
389.0
44
SEG[31]
1434.5
389.0
10
COM[31]
4001.5
389.0
45
SEG[32]
1359.0
389.0
11
Reserve
3926.0
389.0
46
SEG[33]
1283.5
389.0
12
Reserve
3850.5
389.0
47
SEG[34]
1208.0
389.0
13
SEG[0]
3775.0
389.0
48
SEG[35]
1132.5
389.0
14
SEG[1]
3699.5
389.0
49
SEG[36]
1057.0
389.0
15
SEG[2]
3624.0
389.0
50
SEG[37]
981.5
389.0
16
SEG[3]
3548.5
389.0
51
SEG[38]
906.0
389.0
17
SEG[4]
3473.0
389.0
52
SEG[39]
830.5
389.0
18
SEG[5]
3397.5
389.0
53
SEG[40]
755.0
389.0
19
SEG[6]
3322.0
389.0
54
SEG[41]
679.5
389.0
20
SEG[7]
3246.5
389.0
55
SEG[42]
604.0
389.0
21
SEG[8]
3171.0
389.0
56
SEG[43]
528.5
389.0
22
SEG[9]
3095.5
389.0
57
SEG[44]
453.0
389.0
23
SEG[10]
3020.0
389.0
58
SEG[45]
377.5
389.0
24
SEG[11]
2944.5
389.0
59
SEG[46]
302.0
389.0
25
SEG[12]
2869.0
389.0
60
SEG[47]
226.5
389.0
26
SEG[13]
2793.5
389.0
61
SEG[48]
151.0
389.0
27
SEG[14]
2718.0
389.0
62
SEG[49]
75.5
389.0
28
SEG[15]
2642.5
389.0
63
SEG[50]
0.0
389.0
29
SEG[16]
2567.0
389.0
64
SEG[51]
-75.5
389.0
30
SEG[17]
2491.5
389.0
65
SEG[52]
-151.0
389.0
31
SEG[18]
2416.0
389.0
66
SEG[53]
-226.5
389.0
32
SEG[19]
2340.5
389.0
67
SEG[54]
-302.0
389.0
33
SEG[20]
2265.0
389.0
68
SEG[55]
-377.5
389.0
34
SEG[21]
2189.5
389.0
69
SEG[56]
-453.0
389.0
35
SEG[22]
2114.0
389.0
70
SEG[57]
-528.5
389.0
Ver 2.3
7/56
2005/10/05
ST7558
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
71
SEG[58]
-604.0
389.0
107
SEG[94]
-3322.0
389.0
72
SEG[59]
-679.5
389.0
108
SEG[95]
-3397.5
389.0
73
SEG[60]
-755.0
389.0
109
SEG[96]
-3473.0
389.0
74
SEG[61]
-830.5
389.0
110
SEG[97]
-3548.5
389.0
75
SEG[62]
-906.0
389.0
111
SEG[98]
-3624.0
389.0
76
SEG[63]
-981.5
389.0
112
SEG[99]
-3699.5
389.0
77
SEG[64]
-1057.0
389.0
113
SEG[100]
-3775.0
389.0
78
SEG[65]
-1132.5
389.0
114
SEG[101]
-3850.5
389.0
79
SEG[66]
-1208.0
389.0
115
COMS1
-3926.0
389.0
80
SEG[67]
-1283.5
389.0
116
COM[64]
-4001.5
389.0
81
SEG[68]
-1359.0
389.0
117
COM[63]
-4077.0
389.0
82
SEG[69]
-1434.5
389.0
118
COM[62]
-4152.5
389.0
83
SEG[70]
-1510.0
389.0
119
COM[61]
-4228.0
389.0
84
SEG[71]
-1585.5
389.0
120
COM[60]
-4303.5
389.0
85
SEG[72]
-1661.0
389.0
121
COM[59]
-4379.0
389.0
86
SEG[73]
-1736.5
389.0
122
COM[58]
-4454.5
389.0
87
SEG[74]
-1812.0
389.0
123
COM[57]
-4530.0
389.0
88
SEG[75]
-1887.5
389.0
124
COM[56]
-4605.5
389.0
89
SEG[76]
-1963.0
389.0
125
COM[55]
-4681.0
389.0
90
SEG[77]
-2038.5
389.0
126
COM[54]
-4998.5
381.5
91
SEG[78]
-2114.0
389.0
127
COM[53]
-4998.5
306.0
92
SEG[79]
-2189.5
389.0
128
COM[52]
-4998.5
230.5
93
SEG[80]
-2265.0
389.0
129
COM[51]
-4998.5
155.0
94
SEG[81]
-2340.5
389.0
130
COM[50]
-4998.5
79.5
95
SEG[82]
-2416.0
389.0
131
COM[49]
-4998.5
4.0
96
SEG[83]
-2491.5
389.0
132
COM[48]
-4998.5
-71.5
97
SEG[84]
-2567.0
389.0
133
COM[47]
-4998.5
-147.0
98
SEG[85]
-2642.5
389.0
134
COM[46]
-4998.5
-222.5
99
SEG[86]
-2718.0
389.0
135
COM[45]
-4998.5
-298.0
100
SEG[87]
-2793.5
389.0
136
COM[44]
-4998.5
-373.5
101
SEG[88]
-2869.0
389.0
137
COM[43]
-4694.5
-389.0
102
SEG[89]
-2944.5
389.0
138
COM[42]
-4619.0
-389.0
103
SEG[90]
-3020.0
389.0
139
COM[41]
-4543.5
-389.0
104
SEG[91]
-3095.5
389.0
140
COM[40]
-4468.0
-389.0
105
SEG[92]
-3171.0
389.0
141
COM[39]
-4392.5
-389.0
106
SEG[93]
-3246.5
389.0
142
COM[38]
-4317.0
-389.0
Ver 2.3
8/56
2005/10/05
ST7558
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
143
COM[37]
-4241.5
-389.0
179
D2
-1500.0
-389.0
144
COM[36]
-4166.0
-389.0
180
D1
-1425.0
-389.0
145
COM[35]
-4090.5
-389.0
181
D1
-1350.0
-389.0
146
COM[34]
-4015.0
-389.0
182
D0
-1275.0
-389.0
147
COM[33]
-3939.5
-389.0
183
D0
-1200.0
-389.0
148
COM[32]
-3864.0
-389.0
184
VDD
-1125.0
-389.0
149
T9
-3750.0
-389.0
185
T0
-1050.0
-389.0
150
VDD
-3675.0
-389.0
186
T1
-975.0
-389.0
151
VDD
-3600.0
-389.0
187
T2
-900.0
-389.0
152
VDD
-3525.0
-389.0
188
T3
-825.0
-389.0
153
VDD
-3450.0
-389.0
189
T4
-750.0
-389.0
154
VDD
-3375.0
-389.0
190
T5
-675.0
-389.0
155
VDD
-3300.0
-389.0
191
T6
-600.0
-389.0
156
VDD2
-3225.0
-389.0
192
T7
-525.0
-389.0
157
VDD2
-3150.0
-389.0
193
T8
-450.0
-389.0
158
VDD2
-3075.0
-389.0
194
VRS
-375.0
-389.0
159
VDD2
-3000.0
-389.0
195
ERD
-300.0
-389.0
160
VDD2
-2925.0
-389.0
196
ERD
-225.0
-389.0
161
VDD2
-2850.0
-389.0
197
RWR
-150.0
-389.0
162
VDD2
-2775.0
-389.0
198
RWR
-75.0
-389.0
163
VDD2
-2700.0
-389.0
199
A0
0.0
-389.0
164
VDD2
-2625.0
-389.0
200
A0
75.0
-389.0
165
VDD2
-2550.0
-389.0
201
CS
150.0
-389.0
166
VDD2
-2475.0
-389.0
202
CS
225.0
-389.0
167
VDD2
-2400.0
-389.0
203
IMS
300.0
-389.0
168
D7
-2325.0
-389.0
204
VDD
375.0
-389.0
169
D7
-2250.0
-389.0
205
PS
450.0
-389.0
170
D6
-2175.0
-389.0
206
T11
525.0
-389.0
171
D6
-2100.0
-389.0
207
T10
600.0
-389.0
172
D5
-2025.0
-389.0
208
VDD
675.0
-389.0
173
D5
-1950.0
-389.0
209
OSC
750.0
-389.0
174
D4
-1875.0
-389.0
210
OSC
825.0
-389.0
175
D4
-1800.0
-389.0
211
V0
900.0
-389.0
176
D3
-1725.0
-389.0
212
V0
975.0
-389.0
177
D3
-1650.0
-389.0
213
V0
1050.0
-389.0
178
D2
-1575.0
-389.0
214
V0
1125.0
-389.0
Ver 2.3
9/56
2005/10/05
ST7558
PAD NO.
PIN Name
X
Y
PAD NO.
PIN Name
X
Y
215
V1
1200.0
-389.0
244
VLCDOUT
3375.0
-389.0
216
V2
1275.0
-389.0
245
VLCDOUT
3450.0
-389.0
217
V3
1350.0
-389.0
246
VLCDOUT
3525.0
-389.0
218
V4
1425.0
-389.0
247
VLCDOUT
3600.0
-389.0
219
VSS2
1500.0
-389.0
248
VLCDOUT
3675.0
-389.0
220
VSS2
1575.0
-389.0
249
RES
3768.5
-389.0
221
VSS2
1650.0
-389.0
250
COMS2
3864.5
-389.0
222
VSS2
1725.0
-389.0
251
COM[0]
3940.0
-389.0
223
VSS2
1800.0
-389.0
252
COM[1]
4015.5
-389.0
224
VSS2
1875.0
-389.0
253
COM[2]
4091.0
-389.0
225
VSS2
1950.0
-389.0
254
COM[3]
4166.5
-389.0
226
VSS2
2025.0
-389.0
255
COM[4]
4242.0
-389.0
227
VSS2
2100.0
-389.0
256
COM[5]
4317.5
-389.0
228
VSS2
2175.0
-389.0
257
COM[6]
4393.0
-389.0
229
VSS2
2250.0
-389.0
258
COM[7]
4468.5
-389.0
230
VSS2
2325.0
-389.0
259
COM[8]
4544.0
-389.0
231
VSS
2400.0
-389.0
260
COM[9]
4619.5
-389.0
232
VSS
2475.0
-389.0
261
COM[10]
4695.0
-389.0
233
VSS
2550.0
-389.0
262
COM[11]
4998.5
-373.5
234
VSS
2625.0
-389.0
263
COM[12]
4998.5
-298.0
235
VSS
2700.0
-389.0
264
COM[13]
4998.5
-222.5
236
VSS
2775.0
-389.0
265
COM[14]
4998.5
-147.0
237
VLCDIN
2850.0
-389.0
266
COM[15]
4998.5
-71.5
238
VLCDIN
2925.0
-389.0
267
COM[16]
4998.5
4.0
239
VLCDIN
3000.0
-389.0
268
COM[17]
4998.5
79.5
240
VLCDIN
3075.0
-389.0
269
COM[18]
4998.5
155.0
241
VLCDIN
3150.0
-389.0
270
COM[19]
4998.5
230.5
242
VLCDIN
3225.0
-389.0
271
COM[20]
4998.5
306.0
243
VLCDOUT
3300.0
-389.0
272
COM[21]
4998.5
381.5
Ver 2.3
10/56
2005/10/05
ST7558
4. BLOCK DIAGRAM
DB0
DB1
DB2
DB3
DB4
DB5
DB6(SI)
DB7(SCL)
WR(R/W)
RD(E)
A0
/CS
/RES
Fig.1 block diagram
Ver 2.3
11/56
2005/10/05
ST7558
5. PINNING DESCRIPTIONS
Pin Name
I/O
Description
No. of Pins
Lcd driver outputs
LCD segment driver outputs
This display data and the M signal control the output voltage of segment
driver.
Segment driver output voltage
Display data M (Internal) Normal display Reverse display
SEG0 to SEG101
O
H
H
H
L
L
H
L
L
Power save mode
VLCD
V2
VSS
V2
V3
VSS
V3
VLCD
VSS
VSS
COM0 to COM64
O
LCD column driver outputs
This internal scanning data and M signal control the output voltage of
common driver.
Common driver output voltage
Display data M(Internal)
Normal display Reverse display
H
H
VSS
H
L
VLCD
L
H
V1
L
L
V4
Power save mode
VSS
COMS
O
Common output for the icons
The output signals of two pins are same. When not used, this pin should
be left open.
102
65
2
MICROPROCESSOR INTERFACE
Microprocessor interface select input pin
P/S
I
P/S= " H “: parallel data input.
P/S= " L “: serial data input.
When P/S=" L ",D0 to D5 are fixed to " H ".
RD (E) and WR(R/W) are fixed to " H ".
1
Input mode select
Ver 2.3
IMS
I
CSB
I
RESB
I
A0
I
P/S
IMS
State
"H"
" H " 6800-series parallel MPU interface
"H"
" L " 8080-series parallel MPU interface
"L"
" H " 4 Pin-SPI MPU interface
" L " I2C interface
"L"
Chip select input pins
Data/instruction I/O is enabled only when CSB is " L ". When chip select
is non-active, DB0 to DB7 is high impedance.
When CSB pin in two line interface, this pin should fix to ” H”
Reset input pin
When RESET is " L ", initialization is executed.
It determines whether the data bits are data or a command.
A0=" H “: Indicates that D0 to D7 are display data.
A0=" L “: Indicates that D0 to D7 are control data.
2
A0 pin in I C interface, this pin should fix to ” H”
12/56
1
2
1
2
2005/10/05
ST7558
Read/Write execution control pin
/WR(R/W)
IMS
MPU type
/WR(R/W)
H
6800-series
R/W
I
L
8080-series
/WR
Description
Read/Write control input pin
R/W=" H “: read
R/W=" L”: write
Write enable clock input pin
The data on D0 to D7 are latched
at the rising edge of the /WR
signal
2
When in the serial interface must fixed to " H ".
Read/Write execution control pin
IMS
/RD (E)
I
MPU Type
/RD (E)
H
6800-series
E
L
8080-series
/RD
Description
Read/Write control input pin
R/W=" H “: When E is " H ", D0 to D7
are in an output status.
R/W=" L “: The data on D0 to D7 are
latched at the falling edge of the E
signal.
Read enable clock input pin
When /RD is " L ", D0 to D7 are in an
output status.
2
When in the serial interface must fixed to " H ".
D5 to D0
D6 (SI)
D7 (SCL)
I/O
D0 to D1 (SA)
D2 to D3 (SDA_OUT)
D4 to D6 (SDA_IN)
D7 (SCL)
Ver 2.3
When the parallel interface selected (P/S=" H " ): 8-bit interface
8-bit bi-directional data bus that is connected to the standard 8-bit
microprocessor data bus.
When chip select is not active, D0 to D7 is high impedance.
When the serial interface selected (P/S=" L " & IMS=”H”):4-line
D7: serial input clock (SCL)
D6: serial input data (SI)
D5, D4, D3, D2, D1, D0: must fix to “H”..
When chip select is not active, D0 to D7 is high impedance.
2
When the serial interface selected (P/S=" L " & IMS=”L”): I C
D7: serial clock input (SCL)
D6 , D5 , D4: serial input data (SDA_IN)
2
D3, D2: (SDA_OUT) serial data acknowledge for the I C interface. By
connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully
2
I C interface compatible. Having the acknowledge output separated
from the serial data line is advantageous in chip on glass (COG)
applications. In COG application where the track resistance from the
SDA_OUT pad to the system SDA line can be significant, a potential
divider is generated by the bus pull-up resistor and the ITO track
resistance. It is possible the during the acknowledge cycle the ST7558
will not be able to create a valid logic 0 level. By splitting the SDA_IN
input from the SDA_OUT output the device could be used in a mode
that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track
resistance from the SDA_OUT pad to the system SDA line to guarantee
a valid low level.
D6, D5, ….D2 must be connected together (SDA)
D1, D0: Is slave address (SA) bit1, 0, must fix to “H” or “L”
Chip select input pins “CSB” not used must fix to “H”
13/56
16
2005/10/05
ST7558
LCD DRIVER SUPPLY
OSC
I
When the on-chip oscillator is used, this input must be connected
to VDD. An external clock signal, if used, is connected to this input. If
the oscillator and external clock are both inhibited by connecting the
OSC pin to VSS the display is not clocked and may be left in a DC state.
To avoid this, the chip should always be put into Power Down Mode
before stopping the clock.
2
Power Supply Pins
VSS1
VSS2
VDD
VDD2
VLCDOUT
VLCDIN
V0,V1, V2, V3, V4
VRS
Power
Supply
Power
Supply
Power
Supply
Power
Supply
Power
Supply
Power
Supply
Power
Supply
Power
Digital Ground.
The 2 supply rails VSS1 and VSS2 must be connected together.
6
Analog Ground.
The 2 supply rails VSS1 and VSS2 must be connected together.
12
Digital Supply voltage.
The 2 supply rails VDD and VDD2 could be connected together.
If Digital Option pin is high, must be this level
Analog Supply voltage.
The 2 supply rails VDD and VDD2 could be connected together.
9
12
If the internal voltage generator is used, the VLCDIN & VLCDOUT must be
connected together and series one capacitor to VSS2.
If an external supply is used this pin must be left open.
If the internal voltage generator is used, the VLCDIN & VLCDOUT must be
connected together. An external supply voltage can be supplied using
the VLCDIN pad. This pad is for external multiple voltage input. In this
case, VLCDOUT has to be left open,
This is a multi-level power supply for the liquid crystal.
VLCDIN ≥V0 ≥V1≥V2≥V3≥V4≥VSS
6
6
8
Monitor Voltage Regulator level, must be left open.
1
Supply
Test Pin
Test0~Test11
T
Reserve Pin
To test used.
Test0~Test8 must floating
Test9 could be connected out for monitor the VLCD(V0) voltage
Test10 must connect to VSS
Test11 must connect to VDD
11
ALL Reserve Pin must floating
ST7558 I/O PIN ITO Resister Limitation
PIN Name
ITO Resister
PS,IMS,OSC
No Limitation
T1~T8, VRS, V1 , V2 , V3 , V4
Floating
VDD, Vdd2, Vss1, Vss2 , Vlcdin , Vlcdout
<100Ω
T9,V0
<500Ω
A0,/WR,/RD,CSB, D0 …D7(68/80, 4L-SPI interface)
<1KΩ
RESB
<10KΩ
In IIC interface: SDA , SCL ITO resister recommend to less than 100 ohm
Ver 2.3
14/56
2005/10/05
ST7558
6. FUNCTIONS DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There is CSB pin for chip selection. The ST7558 can interface with an MPU when CSB is "L". When CSB is “H”, these pins
are set to any other combination, A0, /RD(E), and /WR(R/W) inputs are disabled and D0 to D7 are to be high impedance.
And, in case of serial interface, the internal shift register and the counter are reset.
Parallel / Serial Interface
ST7558 has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial
interface is determined by P/S pin as shown in table 1.
Type
Parallel
Serial
Table 1. Parallel/Serial Interface Mode
P/S
IMS
CSB
Interface mode
H
6800-series MPU interface
H
CSB
L
8080-series MPU interface
H
CSB 4-pin SPI interface
L
2
L
--I C interface
Parallel Interface (P/S = "H")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by IMS as shown in table 2.
The type of data transfer is determined by signals at A0, /RD (E) and /WR(R/W) as shown in table 3.
IMS
H
L
Common
RS
H
H
L
L
Table 2. Microprocessor Selection for Parallel Interface
CSB
A0
/RD (E) /WR (R/W) DB0 to DB7
MPU bus
CSB
A0
E
R/W
DB0 to DB7 6800-series
CSB
A0
/RD
/WR
DB0 to DB7 8080-series
Table 3. Parallel Data Transfer
8080-series
Description
/RD
/WR
(E)
(R/W)
L
H
Display data read out
H
L
Display data write
L
H
Register status read
H
L
Writes to internal register (instruction)
6800-series
E
R/W
(/RD)
(/WR)
H
H
H
L
H
H
H
L
NOTE: When /RD (E) pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case,
interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0, /WR(R/W)
as in case of 6800-series mode.
Serial Interface (P/S=" L ")
Serial Mode
4-line SPI interface
2
I C interface
P/S
IMS
CSB
A0
Description
L
H
L
Used
Not Used
Fix to “H”
Write only
L
CSB
Not Used
Fix to “H”
Write only
IMS=” L “, P/S=” H “: 4-line SPI interface
When the ST7558 is active (CSB=”L”), serial data (D6) and serial clock (D7) inputs are enabled. And not active, the internal
8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either via
software or the Register Select (A0) Pin, based on the setting of P/S. When the A0 pin is used (IMS = “H”), data is display
data when A0 is high, and command data when A0 is low. When A0 is not used (IMS = “L”), the LCD Driver will receive
command from MCU by default. If messages on the data pin are data rather than command, MCU should send Data
direction command to control the data direction and then one more command to define the number of data bytes will be
write. After these two continuous commands are sending, the following messages will be data rather than command. Serial
data can be read on the rising edge of serial clock going into D7 and processed as 8-bit parallel data on the eighth serial
clock. And the DDRAM column address pointer will be increased by one automatically. The next bytes after the display
data string are handled as command data.
Ver 2.3
15/56
2005/10/05
ST7558
CSB
SDA
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
SCL
A0
Fig. 2 4-line SPI Timing
2
IMS=” L “, P/S=” L “: I C Interface
It could not read Data or Instruction from ST7558 (except Acknowledge signal).
SCL: serial clock input
SDA_IN: serial data input
SDA_OUT: acknowledge response output
Slave address could set from “0111100” to “0111111”.
2
2
The I C interface send RAM data and executes the commands sent via the I C Interface. It could send data in to the RAM.
2
The I C Interface is two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA)
and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be
initiated only when the bus is not busy.
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of
the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated
in Fig.3.
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock
is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined
as the STOP condition (P). The START and STOP conditions are illustrated in Fig.4.
SYSTEM CONFIGURATION
The system configuration is illustrated in Fig.5.
· Transmitter: the device, which sends the data to the bus
· Master: the device, which initiates a transfer, generates clock signals and terminates a transfer
· Slave: the device addressed by a master
· Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message
· Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed
to do so and the message is not corrupted
· Synchronization: procedure to synchronize the clock signals of two or more devices.
ACKNOWLEDGE
Acknowledge signal (ACK) is not BF signal in parallel interface.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a
2
STOP condition. Acknowledgement on the I C Interface is illustrated in Fig.6.
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ST7558
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Fig .3 Bit transfer
SDA
SCL
S
P
START condition
STOP condition
Fig .4 Definition of START and STOP conditions
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER (1)
0111100
SLAVE
RECEIVER (2)
0111101
SLAVE
RECEIVER (3)
0111110
SLAVE
RECEIVER (4)
0111111
SDA
SCL
Fig .5 System configuration
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ST7558
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
S
9
clock pulse for
acknowledge ment
START
condition
Fig .6 Acknowledgement on the I2C Interface
2
I C Interface protocol
The ST7558 supports command, data write addressed slaves on the bus.
2
Before any data is transmitted on the I C Interface, the device, which should respond, is addressed first. Four 7-bit slave
addresses (0111100 to 0111111) are reserved for the ST7558. The R/W is assigned to 0 for Write only.
2
The I C Interface protocol is illustrated in Fig.7.
2
The sequence is initiated with a START condition (S) from the I C Interface master, which is followed by the slave address.
2
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I C Interface transfer. After
acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of a control byte, which defines Co and RS, plus a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a
cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a
command or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last
control byte, depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the
RS bit is set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The
data pointer is automatically updated and the data is directed to the intended ST558 device. If the RS bit of the last control
byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the
received commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the
2
transmission the I C INTERFACE-bus master issues a STOP condition (P).If the R/W bit is set to logic 1 the chip will output
data immediately after the slave address if the RS bit, which was sent during the last write access, is set to logic 0. If no
acknowledge is generated by the master after a byte, the driver stops transferring data to the master.
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ST7558
Write mode
acknowledgement
from ST7558
S 0 1 1 1 1 1 0 0 A 1
slave address
R
S
acknowledgement
from ST7558
control byte
acknowledgement
from ST7558
data byte
A
A 0
control byte
1 byte
R/W
2n>=0bytes
command word
Co
0 1 1 1 1 1 0
R
S
acknowledgement
from ST7558
acknowledgement
from ST7558
data byte
A
A P
n>=0bytes
MSB.......................LSB
Co
R
/
W
Co
slave address
R
S
D D D D D D D D
7 6 5 4 3 2 1 0
0 0 0 0 0 0
data byte
control byte
Fig .7 I2C Interface protocol
Co
0
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by a STOP condition.
Busy Flag
The Busy Flag indicates whether the ST7558 is operating or not. When D7 is "H" in read status operation, this device is in
busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check
this flag before each instruction, which improves the MPU performance.
Data Transfer
The ST7558 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU
to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 8. And when reading
data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU
reads this stored data from bus holder for the next data read cycle as shown in figure 9. This means that a dummy read
cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the
data of the specified address cannot be output with the read display data instruction right after the address sets, but can be
output at the second read of data.
MPU signal
A0
/WR
D0 to D7
N
D(N)
D(N+1) D(N+2)
D(N+3)
N
D(N)
D(N+1)
D(N+2)
D(N+3)
N
N+1
N+2
N+3
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
Fig.8 Write Timing
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ST7558
MPU signal
A0
/W R
/RD
D0 to D7
N
Dummy
D(N)
D(N+1)
Internal signals
/W R
/RD
BUS HOLDER
COLUMN ADDRESS
N
N
D(N)
D(N+1)
D(N+2)
D(N)
D(N+1)
D(N+2)
Fig.9 Read Timing
DISPLAY DATA RAM (DDRAM)
The ST7558 contains a 65X102 bit static RAM that stores the display data. The display data RAM store the dot data for the
LCD. It has a 65(8 pageX8 +1) X102, and extra ICOM. There is a direct correspondence between X-address and column
output number. It is 65-row by 102-column addressable array. Each pixel can be selected when the page and column
addresses are specified. The 65 rows are divided into 8 pages of 8 lines and 1 page of 1 line. Data is read from or written to
the 8 lines of each page directly through D0 to D7. The display data of D0 to D7 from the microprocessor correspond to the
LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller
operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD
flicker.
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ST7558
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM shown in figure 10. It incorporates 4-bit Page
Address register changed by only the “Set Page” instruction. Page Address 9 is a special RAM area for the icons and
display data D0 is only valid.
Column Address Circuit
Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as shown in
figure10. The display data RAM column address is specified by the Column Address Set command. The specified column
address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed
continuously.
Register MX and MY selection instruction makes it possible to invert the relationship between the Column Address and the
segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing MX select instruction.
SEG Output
SEG Output
MX
SEG0
SEG101
“0”
seg0 Æ Segment Address Æ seg101
“1”
seg101 Å Segment Address Å seg0
Com Output
COM Output
MY
“0”
“1”
Com0
Com64
com0 Æ Common Address Æ com64
com64 Å Common Address Å com0
ADDRESSING
Data is downloaded in bytes into the RAM matrix of ST7558 as indicated in Figs.10, 11,12. The display RAM has a matrix
of 65 by 102 bits. The address pointer addresses the columns. The address ranges are: X 0 to 101 (1100101), Y 0 to 8
(1000). Addresses outside these ranges are not allowed.
In vertical addressing mode (V=1) the Y address increments after each byte (see Fig.11). After the last Y address (Y = 8) Y
wraps around to 0 and X increments to address the next column.
In horizontal addressing mode (V=0) the X address increments after each byte (see Fig.12). After the last X address
(X = 101) X wraps around to 0 and Y increments to address the next row.
After the very last address (X = 101, Y = 8) the address pointers wrap around to address (X = 0, Y =0)
Data structure
LSB
0
1
2
3
4
5
6
7
8
9
D7
MSB
D0
D7
D0
1 bit
1 bit
Page 8
Page 9
0
X-address
101
ICOM
D7
1 bit
Fig.10 RAM format, addressing
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Y-address
D0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
0
X-address
917
101
0
1
2
3
4
5
6
7
8
Y-address
ST7558
0 1 2
102103104
204205206
306307308
408409410
510511512
612613614
714715716
816817818
0
X-address
917
101
0
1
2
3
4
5
6
7
8
Y-address
Fig.11 Sequence of writing data bytes into RAM with vertical addressing (V=1)
Fig.12 sequence of writing data bytes into RAM with horizontal addressing (V=0)
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ST7558
Page Address
Data
D3 D2 D1 D0
Line
Address
64
65
0
00
1
S101
MX
Column
address
63
01
S100
D0
62
02
S99
D0
61
ICON(COMS)
03
43H
S98
D0
60
1
04
0
COM64
S97
0
40H
5F
1
Page
8
Page
9
05
D0
S96
0
5E
0
06
0
S95
1
Page
7
5D
1
07
1
08
1
S94
0
Page
6
S93
0
08
1
07
1
5D
0
Page
5
S8
1
06
0
5E
1
S7
0
Page
4
05
0
5F
0
S6
1
04
0
Page
3
60
1
S5
1
03
0
61
0
Page
2
S4
0
02
1
62
0
S3
0
Page
1
01
1
63
0
S2
0
00
0
Page
0
64
0
65
0
S1
0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
S0
0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
LCD
Out
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
COM Output
Display Data RAM Map (65 Duty + ICOM)
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ST7558
Oscillator
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC
input must be connected to VDD. An external clock signal, if used, is connected to this input.
Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL (internal), generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is
generated in synchronization with the display clock and the display data latch circuit latches the 102-bit display data in
synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the
access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M) which
enables the LCD driver to make a AC drive waveform, and also generates an internal common timing signal and start
signal to the common driver. Driving waveform and internal timing signal are shown in Figure 13.
64
65
1
2
3
4
5
6
7
8
9
10
11
12
57
58
59
60
61
62
63
64
65
1
2
3
4
5
CL(Internal)
FR(Internal)
M(Internal)
COM0
VLCD
V1
V2
V3
V4
VSS
COM1
VLCD
V1
V2
V3
V4
VSS
SEGn
VLCD
V1
V2
V3
V4
VSS
Fig.13 2-frame AC Driving Waveform (Duty Ratio: 1/65)
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ST7558
LCD DRIVER CIRCUIT
65-channel common drivers and 102-channel segment drivers configure this driver circuit. This LCD panel driver voltage
depends on the combination of display data and M signal.
V DD
V SS
V LCD
V1
V2
V3
V4
V SS
V LCD
V1
V2
V3
V4
V SS
V LCD
V1
V2
V3
V4
V SS
V LCD
V1
V2
V3
V4
V SS
V LCD
V1
V2
V3
V4
V SS
V LCD
V4
V3
V2
V1
V SS
-V 1
-V 2
-V 3
-V 4
-V LCD
V L2
V1
V2
V3
V4
V SS
-V 1
-V 2
-V 3
-V 4
-V LCD
M
COM0
COM1
COM0
COM2
COM3
COM4
COM5
COM6
COM1
COM7
COM8
COM9
COM2
COM10
COM11
COM12
COM13
COM14
SEG0
SEG 0
1
2
3
4
SEG1
COM0 to
SET0
COM0 to
SET1
Fig.15 Typical LCD driver waveforms
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ST7558
7. RESET CIRCUIT
Setting RESB to “L” or Reset instruction can initialize internal function.
When RESB becomes “L”, following procedure is executed
Page address: 0
Column address: 0
COM Scan Direction MY: 0
SEG Select Direction MX: 0
Oscillator: OFF
Power down mode (PD = 1)
Horizontal addressing (V = 0)
normal instruction set (H = 0)
Display OFF (D = E = 0)
Address counter X [6:0] = 0, Y [2:0] = 0
Bias system (BS [2:0] = 0)
VLCD is equal to 0; the HV generator is switched off (VOP [6:0] = 0)
After power-on, RAM data are undefined
While RESB is “L” or reset instruction is executed, no instruction except read status can be accepted. Reset status
appears at DB6. After DB6 becomes ”L”, any instruction can be accepted. RESB must be connected to the reset pin of
the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESB is essential before used.
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ST7558
8. INSTRUCTION TABLE
COMMAND BYTE
D4
D3
D2
A0
WR
(R/W)
D7
D6
D5
H=0 or 1
NOP
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function set
0
0
0
0
1
0
Ext. display control
0
0
0
0
1
Read status byte
Read data
Write data
0
1
1
1
1
0
PD
D7
D7
RST
D6
D6
BUSY
D5
D5
INSTRUCTION
A0
WR
(R/W)
D7
D6
D5
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
X6
X5
Loading Control
0
0
0
0
0
0
H=1
Booster stages
S/W Internal register
initial
Bias system
Reserved
Set VOP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
INSTRUCTION
H=0
Set VLCD range
Display control
Set Y address of
RAM
Set X address of
RAM
Ver 2.3
DESCRIPTION
D1
D0
0
0
0
1
0
1
0
PD
V
H
0
1
MX
MY
0
Mirror X, Mirror Y
D
D4
D4
E
D3
D3
1
D2
D2
0
D1
D1
1
D0
D0
Read status byte
Read data from RAM
Write data to RAM
COMMAND BYTE
D4
D3
D2
D1
D0
0
D
0
0
PRS
E
Y3
Y2
Y1
Y0
VLCD range L/H select
Set display configuration
Sets Y address of RAM
0≦Y≦9
X4
X3
X2
X1
X0
Sets X address of RAM
0≦X≦101
0
0
0
0
1
1
1
0
1
0
1
1
Loading Control
0
0
0
0
1
0
0
0
0
X
0
0
1
1
X
1
1
0
0
X
VOP6
VOP5
VOP4
VOP3
0
1
0
BS2
X
VOP2
PC1
1
1
BS1
X
VOP1
PC0
0
0
BS0
X
VOP0
27/56
No operation
Internal reset
Power-down; entry mode;
Extended instruction control
DESCRIPTION
booster voltage multiplication
S/W Internal register initial
Sets bias system (BSx)
Do not use
Write VOP to register
2005/10/05
ST7558
9. INSTRUCTION DESCRIPTION
H=”0” or “1”
Reset
This instruction resets initial display line, column address, page address, and common output status select to their initial
status. This instruction cannot initialize the LCD power supply, which is initialized by the RESB pin.
A0
D7
D6
D5
D4
D3
WR(R/W)
0
0
0
0
0
0
0
2
!!!caution: this instruction cannot be used when using I C interface
Function Set
A0
WR(R/W)
0
0
Flag
PD
V
H
MX
MY
D6
0
D5
1
D4
0
D3
0
D1
1
D0
1
D2
PD
D1
V
D0
H
Description
All LCD outputs at VSS (display off), bias generator and VLCD generator off, VLCD can be
disconnected, oscillator off (external clock possible), RAM contents not cleared; RAM data
can be written.
PD=0:chip is active
PD=1:chip is in power down mode
When V = 0, the horizontal addressing is selected. The data is written into the DDRAM as
shown in Fig13.
When V = 1, the vertical addressing is selected. The data is written into the DDRAM as
shown in Fig12
When H = 0 the commands ‘display control’, ‘set Y address’ and ‘set X address’
can be performed, when H = 1 the others can be executed. The commands ‘write data’
and ‘function set’ can be executed in both cases.
H=0:use basic instruction set
H=1:use extended instruction set
Ext. display control
A0
WR(R/W)
0
0
Flag
D7
0
D2
0
D7
0
D6
0
D5
1
D4
0
D3
1
D2
MX
D1
MY
D0
0
Description
SEG bi-direction selection
MX=0:normal direction (SEG0ÆSEG101)
MX=1:reverse direction (SEG101ÆSEG0)
COM bi-direction selection
See Pad Center Coordinates at page 3~10 when using this register
!!!Caution:the common output pad should be care.
The normal direction of common and reverse direction of common have different pad location, only one can be
used. On the other hand, you must choose one kind, NORMAL or REVERSE, and these two have different ITO
layout. Moreover, using the NORMAL layout, must set MY=0; using the REVERSE layout ,must set MY=1.
PS. The NORMAL and REVERSE pad location table are at page3 ~ page10
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ST7558
Read status byte
Indicates the internal status of the ST7558
A0
0
Flag
PD
RST
BUSY
D,E
D2~D0
WR(R/W)
1
D7
PD
D6
RST
D5
BUSY
D4
D
D3
E
D2
1
D1
0
D0
1
Description
PD=0:chip is active
PD=1:chip is in power down mode
Indicates the initialization is in progress by RESET signal
0: chip is active,1:chip is being reset
The device is busy when internal operation or reset. Any instruction is rejected until BUSY
goes LOW.
0:chip is active
1:chip is being busy
D E The bits D and E select the display mode.
0 0 Display blank
0 1 All display segments on
1 0 Normal mode
1 1 Inverse video mode
ST7558 will return the fix data “101” as identification bit
Write data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and
page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data
to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written.
A0
1
WR(R/W)
D7
D6
D5
D4
D3
Write data
D2
D1
D0
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
0
D0
PRS
D5
0
D4
0
D3
1
D2
D
D1
0
D0
E
0
H=”0”
Set VLCD range
VLCD range L/H select
A0
0
WR(R/W)
0
PRS=0:VLCD programming range LOW
PRS=1: VLCD programming range HIGH
Display Control
This bits D and E selects the display mode.
A0
0
Flag
D,E
Ver 2.3
WR(R/W)
0
D7
0
D6
0
Description
D E The bits D and E select the display mode.
0 0 Display off
1 0 Normal display
0 1 All display segments on
1 1 Inverse video mode
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Set Y address of RAM
Y [3:0] defines the Y address vector address of the display RAM.
A0
0
WR(R/W)
0
X/Y Address range
Y3 Y2 Y1 Y0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
D7
0
D6
1
D5
0
D4
0
D3
Y3
CONTENT
Page0 (display RAM)
Page1 (display RAM)
Page2 (display RAM)
Page3 (display RAM)
Page4 (display RAM)
Page5 (display RAM)
Page6 (display RAM)
Page7 (display RAM)
Page8 (display RAM)
Page9 (display RAM)
D2
Y2
D1
Y1
D0
Y0
ALLOWED X-RANGE
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
Set X address of RAM
The X address points to the columns. The range of X is 0…101.
A0
0
X6
0
0
0
0
:
1
1
1
1
WR(R/W)
0
X5
0
0
0
0
:
1
1
1
1
D7
1
X4
0
0
0
0
:
0
0
0
0
D6
X6
X3
0
0
0
0
:
0
0
0
0
D5
X5
X2
0
0
0
0
:
0
0
1
1
D4
X4
D3
X3
X1
0
0
1
1
:
1
1
0
0
X0
0
1
0
1
:
0
1
0
1
D2
X2
D1
X1
D0
X0
Column address
0
1
2
3
:
98
99
100
101
Set Loading Control
Improve Out Put Driving in Heavy Loading
A0
0
WR(R/W)
0
D7
0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
1
0
0
0
0
0
0
1
0
0
1
Ver 2.3
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H=”1”
Booster stages
The ST7558 incorporates a software configurable voltage multiplier. After reset (RESB), the default voltage multiplier is set
to 2*VDD2. Other voltage multiplier factors are set via the command “Set Booster stages”.
A0
0
D5
0
D4
0
D3
1
D2
0
D1
PC1
D0
PC0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
1
D0
0
System Bias
Select LCD bias ratio of the voltage required for driving the LCD.
A0
D7
D6
D5
D4
D3
WR(R/W)
0
0
0
0
0
1
0
D2
BS2
D1
BS1
D0
BS0
WR(R/W)
0
D7
0
D6
0
Flag
Description
PC1 PC0
0
0 2*voltage multiplier
PC1, PC0 0
1 3*voltage multiplier
1
0 4*voltage multiplier
1
1 5*voltage multiplier
S/W initial Internal register
st
The 1 Instruction
A0
D7
WR(R/W)
0
0
0
nd
The 2 Instruction
A0
D7
WR(R/W)
0
0
0
BS2
0
0
0
0
1
1
1
1
LCD bias voltage
Symbol
VLCDIN
V1
V2
Ver 2.3
BS1
0
0
1
1
0
0
1
1
BS0
0
1
0
1
0
1
0
1
Bias
11
10
9
8
7
6
5
4
Bias voltage for 1/8 bias
VLCDIN
7/8 X VLCDIN
6/8 X VLCDIN
Recommend Duty
1:100
1:80
1:65/1:68
1:48
1/40:1/34
1/24
1:18/1:16
1:10/1:9/1:8
Symbol
V3
V4
VSS
31/56
Bias voltage for 1/8 bias
2/8 X VLCDIN
1/8 X VLCDIN
VSS
2005/10/05
ST7558
Set VOP value:
The operation voltage VLCD can be set by software.
V0=( a + VOP×b )
(1)
The parameters are explained in table 4.The maximum voltage that can be generated is depending on the VDD voltage
and the display load current. Two overlapping VLCD ranges are selectable via the command “Booster control”. For the
LOW (PS=0) range a=a1 and for the HIGH (PRS=1) range a=a2 with steps equal to “b” in both ranges. Note that the
charge pump is turned off if VOP [6;0] and the bit PRS are all set to zero.
Table 4 Typical values for parameter for the HV-Generator programming
SYMBOL
VALUE
UNIT
a1
2.94(PRS=0)
V
a2
6.75(PRS=1)
V
b
0.03
V
VL2
Charge pump off
b
00
a2
a1+b
01
02
03
04
05
06
.....
7D
7E
7F
00
01
02
03
LOW(PRS=0)
04
05
06
.....
7D
7E
7F
HIGH(PRS=1)
VOP [6:0](programmed) {00 hex… 7F hex}
Fig.19 VOP programming of ST7558
Caution
As the programming range for the internally generated VLCDIN allows values above the max allowed VLCDIN, the
customer has to ensure while setting the VOP register that under all condition and including all tolerances the
VLCD limit of max. 13V will never be exceeded. As VLCDIN increases with lower temperatures, care must be taken
not to set a Vop generating a VLCDIN voltage that will exceed the maximum of 10.6V when operating at –40 ℃.
Ver 2.3
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10. COMMAND DESCRIPTION
Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON(VDD-VSS) Keeping the /RES Pin="L"
Waiting for Stabilizing the Power
Release the reset state. (/RESB pin="H")
Waiting reset circuit stablized(>1ms)
Function set PD=0 ,V=0 , H=1
SET Bias system
S/W Internal register initial (2-byte)
SET Booster 2X
Delay 50ms
SET VOP
HV_gen stages
SET Booster 4X / 5X
Function set PD=0 , V=0 , H=0
Ext.display control
Set VLCD Range(PRS)
Display control D=1 E=0 (Normal)
Set X , Y address
End of Initialization
Fig.20 Initializing with the Built-in Power Supply Circuits
Ver 2.3
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Referential Instruction Setup Flow: Initializing without the built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON(VDD-VSS) Keeping the /RES Pin="L"
Waiting for Stabilizing the Power
Release the reset state. (/RESB pin="H")
Waiting reset circuit stablized(>1ms)
Set Power Save
Function set PD=0 ,V=0 , H=1
SET Bias system
S/W Internal register initial
Function set PD=0 , V=0 , H=0
Ext.display control
Display control D=1 E=0 (Normal)
Set X , Y address
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Fig.21 Initializing without Built-in Power Supply Circuits
Ver 2.3
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ST7558
Referential Instruction Setup Flow: Data Displaying
End of Initialization
Display Data RAM Addressing by Instruction
[Set Page Address]
[Set Column Address]
Write Display Data by Instruction
[Display Data Write]
Turn Display ON/OFF Instruction
[Display ON/OFF]
End of Data Display
Fig.22 Data Displaying
Referential Instruction Setup Flow: Power OFF
Optional Status
Set Power Save by Instruction
Power OFF(VDD-VSS)
End of Power OFF
Fig.23 Power OFF
Ver 2.3
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11. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2.
Parameter
Symbol
Conditions
Unit
Power Supply Voltage
VDD
–0.5 ~ +5.0
V
Power supply voltage
V0
3.0 ~ 12
V
Power supply voltage
VLCDIN
–0.3 ~ +13.5
V
Power supply voltage
V1, V2, V3, V4
0.3 to VLCDIN
V
Input voltage
VIN
–0.5 to VDD+0.5
V
Output voltage
VO
–0.5 to VDD+0.5
V
Operating temperature
TOPR
–30 to +85
°C
Storage temperature
TSTR
–65 to +150
°C
VLCD
V1 to V4
VDD
VDD
VSS
VSS
System (MPU) side
VSS
ST7558 chip side
Notes
1. Stresses above those listed under Limiting Values may cause permanent damage to the device.
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.
3. Insure that the voltage levels of V1, V2, V3, and V4 are always such that
Vout ≧ V0 ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ Vss
Ver 2.3
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12. DC CHARACTERISTICS
VDD = 1.8 V to 3.3V; VSS = 0 V; VLCD = 3.0 to 13.0V; Tamb = -30℃ to +85℃; unless otherwise specified.
Item
Symbol Condition
Operating Voltage (1)
VDD
Operating Voltage (2)
VDD2
High-level Input Voltage
VIHC
Low-level Input Voltage
Rating
Units
Applicable
Pin
Min.
Typ.
Max.
1.8
—
3.3
V
Vss*1
1.8
—
3.3
V
VSS2
0.7 x VDD —
VDD
V
*2
VILC
VSS
0.3 x VDD V
*2
High-level Output Voltage
VOHC
0.7 x VDD —
VDD
V
*3
Low-level Output Voltage
VOLC
VSS
—
0.3 x VDD V
*3
Input leakage current
ILI
VIN = VDD or VSS
–1.0
—
1.0
μA
*4
Output leakage current
ILO
VIN = VDD or VSS
–3.0
—
3.0
μA
*5
—
2.0
3.5
Liquid Crystal Driver ON
Resistance
RON
(Relative to VSS)
Ta =
VLCDIN =
25°C
13.0 V
(Relative VLCDIN = 8.0
To VSS) V
Internal Oscillator fOSC
Oscillator
External
Frequency Input
fCL
1/65 duty
Ta = 25°C
Frame frequency fFRAME
Item
Internal Power
Input voltage
Supply Step-up output
voltage Circuit
Symbol
Condition
VDD
—
KΩ
SEGn
COMn *6
—
3.2
5.4
—
80
84
kHz
*7
—
80
84
kHz
OSC
—
77
80.3
Hz
Rating
Units
Applicable Pin
Min.
Typ.
Max.
(Relative To VSS)
1.8
—
3.3
V
VLCDOUT
(Relative To VSS)
—
—
13.5
V
VLCDOUT
VLCDIN
(Relative To VSS)
—
—
13.5
V
VLCDIN
Voltage regulator
Circuit Operating
Voltage
Ver 2.3
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ST7558
Bare Dice Consumption Current : During Display, with the Internal Power Supply, Current consumed by total ICs when an
external power supply(VDD,VDD2) is used .
Test pattern
Symbol
Rating
Condition
Units
Notes
400
μA
*8
2
μA
Min.
Typ.
Max.
—
300
—
0.01
VDD,VDD2 = 3.0 V,
Display Pattern
SNOW
ISS
V0 – VSS = 9.0 V
4X Booster
1/9 Bias
Power Down
ISS
VDD=3.0V
Ta = 25°C
Notes to the DC characteristics
1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load.
2. Internal clock
3. Power-down mode. During power down all static currents are switched off.
4. If external VLCDIN, the display load current is not transmitted to IDD.
5. VOUT external voltage applied to VLCDIN pin; VLCDIN disconnected from VLCDOUT (no connect)
References for items market with *
*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden
fluctuations to the voltage while the MPU is being accessed.
*2 The A0, D0 to D5, D6 (SI), D7 (SCL), /RD (E), /WR ,/(R/W), CSB, IMS, OSC, P/S, /DOF, RESB ,and MODE terminals.
*3 The D0 to D7, and OSC terminals.
*4 The A0,/RD (E), /WR ,/(R/W), CSB, IMS, OSC, P/S, /DOF, RESB ,and MODE terminals.
*5 Applies when the D0 to D5, D6 (SI), D7 (SCL) terminals are in a high impedance state.
*6 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the
various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage range.
RON = 0.1 V /∆I (Where ∆I is the current that flows when 0.1 V is applied while the power supply is ON.)
*7 The relationship between the oscillator frequency and the frame rate frequency.
*8,9It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
Ver 2.3
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13. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8
tAH8
/CS
tCYC8
tCCLR,tCCLW
WR,RD
tCCHR,tCCHW
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Fig 24.
(VDD = 3.3V , Ta =-30~85°C)
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
Ver 2.3
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH8
10
—
tAW8
0
—
tCYC8
240
—
tCCLW
80
—
tCCHW
80
—
tCCLR
140
—
tCCHR
80
tDS8
40
—
tDH8
0
—
tACC8
CL = 100 pF
—
70
tOH8
CL = 100 pF
5
50
39/56
Units
ns
2005/10/05
ST7558
(VDD = 2.7 V , Ta = -30~85°C )
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Address hold time
READ access time
D0 to D7
READ Output disable time
Symbol
Condition
Rating
Min.
Max.
tAH8
15
—
tAW8
0
—
tCYC8
400
—
tCCLW
220
—
tCCHW
180
—
tCCLR
220
—
tCCHR
180
—
tDS8
40
—
tDH8
0
—
tACC8
CL = 100 pF
—
140
tOH8
CL = 100 pF
10
100
Units
ns
(VDD = 1.8V , Ta = -30~85°C )
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH8
30
—
tAW8
0
—
tCYC8
640
—
tCCLW
360
—
tCCHW
280
—
tCCLR
360
—
tCCHR
280
tDS8
80
—
tDH8
30
—
tACC8
CL = 100 pF
—
240
tOH8
CL = 100 pF
10
200
Units
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between CSB being “L” and WR and RD being at the “L” level.
Ver 2.3
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ST7558
System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
A0
R/W
tAW6
tAH6
CS1
(CS2="1")
tCYC6
tCCLR,tCCLW
E
tCCHR,tCCHW
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Fig 25.
(VDD = 3.3 V , Ta = -30~85°C )
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
Ver 2.3
D0 to D7
Symbol
Condition
Rating
Min.
Max.
tAH6
10
—
tAW6
0
—
tCYC6
240
—
tEWLW
80
—
tEWHW
80
—
tEWLR
80
—
tEWHR
140
tDS6
40
—
tDH6
0
—
tACC6
CL = 100 pF
—
70
tOH6
CL = 100 pF
5
50
41/56
Units
ns
2005/10/05
ST7558
(VDD = 2.7V , Ta =-30~85°C )
Item
Signal
Address hold time
A0
Address setup time
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
RD
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
D0 to D7
READ Output disable time
Symbol
Rating
Condition
Min.
Max.
tAH6
15
—
tAW6
0
—
tCYC6
400
—
tEWLW
220
—
tEWHW
180
—
tEWLR
220
—
tEWHR
180
—
tDS6
40
—
tDH6
0
—
tACC6
CL = 100 pF
—
140
tOH6
CL = 100 pF
10
100
(VDD =1.8V
Item
Signal
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WR
RD
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
D0 to D7
Symbol
Condition
Units
ns
, Ta =-30~85°C )
Rating
Min.
Max.
tAH6
30
—
tAW6
0
—
tCYC6
640
—
tEWLW
360
—
tEWHW
280
—
tEWLR
360
—
tEWHR
280
—
tDS6
80
—
tDH6
30
—
tACC6
CL = 100 pF
—
240
tOH6
CL = 100 pF
10
200
Units
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CSB being “L” and E.
Ver 2.3
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ST7558
SERIAL INTERFACE(4-Line Interface)
tCCSS
tCSH
/CS1
(CS2="1")
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
Fig 26.
(VDD=3.3V,Ta=-30~85℃)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
A0
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Condition
Rating
Min.
Max.
tSCYC
50
—
tSHW
25
—
tSLW
25
—
tSAS
20
—
tSAH
10
—
tSDS
20
—
tSDH
10
—
tCSS
20
—
tCSH
140
—
Units
ns
(VDD=2.7V,Ta=-30~85℃)
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
CS-SCL time
Ver 2.3
A0
SI
CSB
Symbol
Condition
Rating
Min.
Max.
tSCYC
100
—
tSHW
50
—
tSLW
50
—
tSAS
30
—
tSAH
20
—
tSDS
30
—
tSDH
20
—
tCSS
30
—
tCSH
160
—
43/56
Units
ns
2005/10/05
ST7558
(VDD=1.8V,Ta=-30~85℃)
Item
Signal
Serial Clock Period
SCL
SCL “H” pulse width
SCL “L” pulse width
Address setup time
A0
Address hold time
Data setup time
SI
Data hold time
CS-SCL time
CSB
CS-SCL time
Symbol
Rating
Condition
Min.
Max.
tSCYC
200
—
tSHW
80
—
tSLW
80
—
tSAS
60
—
tSAH
30
—
tSDS
60
—
tSDH
30
—
tCSS
40
—
tCSH
200
—
Units
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
2
SERIAL INTERFACE(I C Interface)
SD A
tBU F
t H IG H
tLO W
SCL
t D H ;S T A
t H D ;D A T
t S U ;D A T
(VDD= 1.8V~3.3V,Ta=-30~85℃)
Item
Signal Symbol
Rating
Condition
Min.
Max.
Units
SCL clock frequency
SCL
FSCLK
-
200
kHZ
SCL clock low period
SCL
TLOW
2.5
-
us
SCL clock high period
SCL
THIGH
2.5
-
us
Data set-up time
SI
TSU;Data
0.1
-
us
Data hold time
SI
THD;Data
0
0.9
us
SCL,SDA rise time
SCL
TR
20+0.1Cb 300
ns
SCL,SDA fall time
SCL
TF
20+0.1Cb 300
ns
Cb
-
400
pF
Capacitive load represented by each bus line
Setup time for a repeated START condition
SI
TSU;SUA
0.6
-
us
Start condition hold time
SI
THD;STA
0.6
-
us
Setup time for STOP ondition
TSU;STO
0.6
-
us
Tolerable spike width on bus
TSW
-
50
ns
TBUF
2.5
BUS free time between a STOP and StART condition
Ver 2.3
SCL
44/56
us
2005/10/05
ST7558
14. RESET TIMING
tRW
/RES
tR
Internal
status
During reset
Reset complete
Fig 27.
(VDD = 3.3V , Ta = –30 to 85°C )
Item
Signal
Reset time
Reset “L” pulse width
RESB
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
1
us
tRW
1
—
—
us
(VDD = 2.7V , Ta = –30 to 85°C )
Item
Signal
Reset time
Reset “L” pulse width
RESB
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
1.5
us
tRW
1.5
—
—
us
(VDD = 1.8V , Ta = –30 to 85°C )
Item
Signal
Reset time
Reset “L” pulse width
Ver 2.3
RESB
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
2.0
us
tRW
2.0
—
—
us
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ST7558
15. APPLICATION INFORMATION
Table 5 programming example for ST7558
SETP
SERIAL BUS BYTE
DISPLAY
OPERATION
1
Start
CSB IS going low.
2
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Function Set.
0
PD=0,V=0,select extended
0
0
1
0
0
0
0
0
Instruction set(H=0 mode)
3
4
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Set VOP
0
VOP is set to a+16*b[V]
1
0
0
1
0
0
0
0
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Function Set.
0
PD=0,V=0,select normal
0
0
1
0
0
0
0
0
Instruction set(H=0 mode).
5
6
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Display control.
0
Set normal mode(D=1,E=0)
0
0
0
0
0
1
0
0
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Data Write.
1
Y,X are initialized to 0 by
0
0
1
0
0
1
1
0
default, so they aren’t set
here…
7
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
8
0
1
0
0
1
0
1
0
0
1
0
0
Data Write.
1
0
1
0
0
1
0
0
Data Write.
1
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
11
0
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
10
1
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
9
0
Data Write.
0
0
1
1
0
0
1
Data Write.
0
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
Ver 2.3
0
0
0
0
0
0
0
Data Write.
0
46/56
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ST7558
12
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
13
0
0
0
0
0
1
0
1
1
1
1
1
1
Data Write.
1
Data Write.
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
15
1
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
14
0
Data Write.
0
1
0
0
0
0
0
1
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Display Control.
0
Set inverse video mode
0
0
0
0
1
1
0
1
(D=1,E=1).
16
17
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Set X address of RAM.
0
Set address to “0000000”.
1
0
0
0
0
0
0
0
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
Ver 2.3
0
0
0
0
0
0
0
Data Write.
0
47/56
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ST7558
2
programming example for ST7558(Use I C Interface)
SETP
1
2
3
SERIAL BUS BYTE
DISPLAY
OPERATION
2
I C INTERFACE Start
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Slave address for write
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Control byte with cleared Co bit
0
0
0
0
0
0
0
0
and A0 set to logic 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
4
0
0
1
0
0
0
0
Function Set.
1
PD=0,V=0,select extended
Instruction set(H=1 mode)
5
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
0
0
1
Set bias system
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
6
1
0
0
1
0
0
0
Set VOP
VOP is set to a+16*b[V]
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
7
0
0
1
0
0
0
0
Function Set.
0
PD=0,V=0,select normal
Instruction set(H=0 mode).
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
8
9
10
11
0
0
0
0
0
1
0
Display control.
0
Set normal mode(D=1,E=0)
2
I C INTERFACE Start
restart
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Slave address for write
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Control byte with set Co bit and
1
1
0
0
0
0
0
0
A0 set to logic 1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
12
0
0
1
0
0
1
1
Y,X are initialized to 0 by
0
default, so they aren’t set
here…
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
13
0
1
0
0
1
0
0
Data Write.
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
14
Ver 2.3
0
1
0
0
1
0
0
Data Write.
1
48/56
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ST7558
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
15
1
0
0
1
0
0
Data Write.
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
16
0
1
1
0
0
1
Data Write.
0
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
17
0
0
0
0
0
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
18
1
0
0
0
0
0
Data Write.
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
19
1
1
1
1
1
1
Data Write.
1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
20
21
22
23
1
0
0
0
0
0
1
2
I C INTERFACE start
restart
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Slave address for write
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Control byte with cleared Co bit
1
0
0
0
0
0
0
0
and A0 set to logic 1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
24
25
0
0
0
1
1
0
Display Control.
1
Set inverse video mode
(D=1,E=1).
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Ver 2.3
1
0
0
0
0
0
0
Control byte with cleared Co bit
0
and A0 set to logic 1
49/56
2005/10/05
ST7558
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
26
27
0
0
0
0
0
0
Set X address of RAM.
0
Set address to “0000000”.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
0
0
0
0
Control byte with set Co bit and
0
A0 set to logic 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Write.
2
I C INTERFACE start
restart
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Slave address for write
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Control byte with set Co bit and
1
1
0
0
0
0
0
0
A0 set to logic 1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
32
33
0
0
0
0
0
0
Set X address of RAM.
0
Set address to “0000000”.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Ver 2.3
1
0
0
0
0
0
0
Control byte with cleared Co bit
0
and A0 set to logic 0
50/56
2005/10/05
ST7558
The pinning of the ST7558 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size:
65x102 pixels.
Display 102X 65 pixels
102
33
VLCDOUT
VLCDIN
32
VDD2
VDD
VSS1
VSS2
ST7558
VDD
VSS
8
CLVCD
I/O
CVDD
Fig 28. Application diagram: internal charge pump is used and single VDD
Display 102 X 65 pixels
102
33
VLCDOUT
VLCDIN
32
8
VSS1
VSS2
VDD2
VDD
ST7558
VDD CVDD
CLVCD
I/OVDD2
CVDD2
VSS
Fig 29. Application diagram: Internal charge pump is used and two
separate VDD(VDD2)
Ver 2.3
51/56
2005/10/05
ST7558
Display 102 X 65 pixels
102
33
VSS1
VSS2
VDD2
VDD
ST7558
VLCDOUT
VLCDIN
32
8
VL2
I/O VDD2
CVDD VSS
Fig 30. application diagram : External high voltage generation is used
The required minimum value for the external capacitors in an application with the ST7558 are:
CVLCD = min. 100nF
CVDD,2= min. 1.0 μF
Higher capacitor values are recommended for ripple reduction.
Ver 2.3
52/56
2005/10/05
ST7558
16.THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7558 Series can be connected to either 80X86 Series MPUs or to 6800 Series MPUs. Moreover, using the serial
interface it is possible to operate the ST7558 series chips with fewer signal lines.
The display area can be enlarged by using multiple ST7558 Series chips. When this is done, the chip select signal can be
used to select the individual Ics to access.
(1) 8080 Series MPUs
VDD
VCC
A0
/CS
Decoder
ST7558
A1 to A7
IORQ
MPU
VDD
IMS
A0
D0 to D7
E (/RD)
R/W (/WR)
/RES
DO to D7
RD
WR
RES
GND
PS
VSS
RESET
VSS
(2) 6800 Series MPUs
VDD
VCC
A0
/CS
Decoder
ST7558
A1 to A7
IORQ
MPU
VDD
IMS
A0
D0 to D7
/RD (E)
/WR (R/W)
/RES
DO to D7
RD
WR
RES
GND
PS
VSS
RESET
VSS
(3) Using the Serial Interface (4-line interface)
VDD
VCC
A0
VDD
IMS
ST7558
/CS
Decoder
MPU
A1 to A7
A0
Port 1
Port 2
RES
GND
SI
SCL
/RES
PS
VSS
RESET
VSS
Ver 2.3
53/56
2005/10/05
ST7558
2
(4) Using the Serial Interface (I C interface)
VDD
MPU
Port 1
Port 2
RES
ST7558
VDD
IMS
VCC
SDA
SCL
/RES
PS
RESET
GND
VSS
VSS
Ver 2.3
54/56
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ST7558
65-duty/serial-4Line/VLCDIN-internal/VDD2=VDD/internal-OSC
C
O
M
1
0
C
O
M
1
1
C
O
M
1
9
………
C
O
M
2
0
C
C
O
M
5
2
………
C
O
M
5
3
C
O
M
4
4
C
O
M
4
3
65-duty/serial-I2C/VLCDIN-internal/VDD2=VDD/internal-OSC
Ver 2.3
55/56
2005/10/05
ST7558
C C
O O
C
O
M
1
0
C
O
M
1
1
………
1
0
1
T11
PS
T10
OS C
-- VSS
-- VDD
-- VSS
-- V S S (default)
-- VDD (internal)
……… …… ……… ……… ……… ……
( serial )
( I2C )
IMS
S S
C
C C C
E E
O
O O O
G G
M
M M M
1 1
S
0 0
1 0
2
CS
A0
RWR
ERD
D0 ~ D1
D2 ~ D6
D7
ST7558
-------S
e
s
e
r
v
e
R
VDD
VDD
VDD
VDD
VSS
SDA
SCL
S
0
E E
G G
1
C
O
M
2
0
R
C
L
S
C C C
3 4
O O O
M M M
3 3 3
2
D
D
V
S
S
V
S
R
E
… ……
V
L
C
D
O
U
N T
V
L
C
D
I
O
U
T
V
S 6
2 4
C C
O O
M M
4 4
1 2
C C
5
5
5
4
O O
O O
MM…M M
C C
(no used)
(no used)
(no used)
(no used)
(addr ess)
(need exter nal pull u pr esister)
(need exter nal pull up resister)
S
D
A
V V VV
V V
T T V O
V
VE R
I V
D D DD
S S V V
T D D DD D D DD D DD DD T T T T T T T T T RR W A C M D P 1 1 D S VV V VV S S S S
9
2 2 7 6 5 4 3 2 1 0 D 0 1 2 3 4 5 6 7 8 S D R 0 S S D S 1 0 D C 0 1 2 3 4 2 2 S S
R
E
S
………
C
O
M
1
9
C
e
r
v
e
R
e
s
……
C C
O
M
M M
9 8
O O
M M …
3
1
R
VD D
C
O
M
4
3
C
O
M
4
4
C
O
M
5
2
C
O
M
5
3
2005/10/05
56/56
Ver 2.3
2 2
1 2
ITO Pad for mo nit or V 0 te st
V DD
C