SITRONIX ST7571

Sitronix
ST7571
4 Gray Scale Dot Matrix LCD Controller/Driver
1. INTRODUCTION
ST7571 is a driver & controller LSI for 4-level gray scale graphic dot-matrix liquid crystal display systems. This chip is
2
connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI), I C or 8-bit parallel display data and
stores in an on-chip display data RAM of 128 x 129 x 2 bits. It performs display data RAM write operation with no external
operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive
liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
4-level (White, Light Gray, Dark Gray, Black) Gray Scale Display with PWM Method
DDRAM Data [ 2n : 2n+1 ]
Gray Scale
2n
2n + 1
0
0
White
0
1
Light gray
1
0
Dark gray
1
1
Black
(Accessible column address, n = 0, 1, 2, ……, 125, 126, 127)
Driver Output Circuits
On-chip Low Power Analog Circuits
-
-
On-chip oscillator circuit
Applicable Duty Ratios
-
Build-in Voltage converter ( x8)
-
Various partial display
-
Voltage regulator (temperature gradient: -0.13%/°C)
-
Partial window moving & data scrolling
128 segment outputs / 128+1 common outputs
-
On-chip contrast control function (64 steps x 8)
On-chip Display Data RAM
-
Voltage follower (LCD bias : 1/5 to 1/12)
-
Operating Voltage Range
Capacity: 128 x 129 x 2= 33,024 bits
Microprocessor Interface
-
Digital Power (VDD1):
-
Analog Power (VDD2, VDD3):
8-bit parallel interface supports
6800-series or 8080-series MCU
-
4-line serial interface (4-Line SPI)
-
3-line serial interface (3-Line 8-bit SPI)
-
-
2
I C serial interface
1.8V~3.3V (cover 1.7V~3.4V)
2.7V~3.3V (cover 2.6V~3.4V)
Package Type
-
Application for COG
ST7571
6800 , 8080 ,
4-Line , 3-Line interface
(without I2C interface)
ST7571i
I2C interface
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
Ver 1.5a
1/76
2009/7/21
ST7571
3. PAD ARRANGEMENT (COG)
l
l
Chip Size : 7956um X 780um
Bump Pitch :
I/O PAD : 80um
COM PAD : 33um
SEG PAD : 27um
l
Bump Size :
I/O PAD : 65um X 63 um
COM/SEG PAD : 14um X 128um
l
l
Bump Height : 15um
Chip Thickness : 300 um
Fig. 1 IC Pad Arrangement
Ver 1.5a
2/76
2009/7/21
ST7571
4. PAD CENTER COORDINATES
PAD No.
Pin Name
X
Y
PAD No.
Pin Name
X
Y
1
COM[126]
3896.50
283.00
36
COM[56]
2741.50
283.00
2
COM[124]
3863.50
283.00
37
COM[54]
2708.50
283.00
3
COM[122]
3830.50
283.00
38
COM[52]
2675.50
283.00
4
COM[120]
3797.50
283.00
39
COM[50]
2642.50
283.00
5
COM[118]
3764.50
283.00
40
COM[48]
2609.50
283.00
6
COM[116]
3731.50
283.00
41
COM[46]
2576.50
283.00
7
COM[114]
3698.50
283.00
42
COM[44]
2543.50
283.00
8
COM[112]
3665.50
283.00
43
COM[42]
2510.50
283.00
9
COM[110]
3632.50
283.00
44
COM[40]
2477.50
283.00
10
COM[108]
3599.50
283.00
45
COM[38]
2444.50
283.00
11
COM[106]
3566.50
283.00
46
COM[36]
2411.50
283.00
12
COM[104]
3533.50
283.00
47
COM[34]
2378.50
283.00
13
COM[102]
3500.50
283.00
48
COM[32]
2345.50
283.00
14
COM[100]
3467.50
283.00
49
COM[30]
2312.50
283.00
15
COM[98]
3434.50
283.00
50
COM[28]
2279.50
283.00
16
COM[96]
3401.50
283.00
51
COM[26]
2246.50
283.00
17
COM[94]
3368.50
283.00
52
COM[24]
2213.50
283.00
18
COM[92]
3335.50
283.00
53
COM[22]
2180.50
283.00
19
COM[90]
3302.50
283.00
54
COM[20]
2147.50
283.00
20
COM[88]
3269.50
283.00
55
COM[18]
2114.50
283.00
21
COM[86]
3236.50
283.00
56
COM[16]
2081.50
283.00
22
COM[84]
3203.50
283.00
57
COM[14]
2048.50
283.00
23
COM[82]
3170.50
283.00
58
COM[12]
2015.50
283.00
24
COM[80]
3137.50
283.00
59
COM[10]
1982.50
283.00
25
COM[78]
3104.50
283.00
60
COM[8]
1949.50
283.00
26
COM[76]
3071.50
283.00
61
COM[6]
1916.50
283.00
27
COM[74]
3038.50
283.00
62
COM[4]
1883.50
283.00
28
COM[72]
3005.50
283.00
63
COM[2]
1850.50
283.00
29
COM[70]
2972.50
283.00
64
COM[0]
1817.50
283.00
30
COM[68]
2939.50
283.00
65
COMS1
1784.50
283.00
31
COM[66]
2906.50
283.00
66
SEG[0]
1714.50
283.00
32
COM[64]
2873.50
283.00
67
SEG[1]
1687.50
283.00
33
COM[62]
2840.50
283.00
68
SEG[2]
1660.50
283.00
34
COM[60]
2807.50
283.00
69
SEG[3]
1633.50
283.00
35
COM[58]
2774.50
283.00
70
SEG[4]
1606.50
283.00
Ver 1.5a
3/76
2009/7/21
ST7571
PAD No.
Pin Name
X
Y
PAD No.
Pin Name
X
Y
71
SEG[5]
1579.50
283.00
106
SEG[40]
634.50
283.00
72
SEG[6]
1552.50
283.00
107
SEG[41]
607.50
283.00
73
SEG[7]
1525.50
283.00
108
SEG[42]
580.50
283.00
74
SEG[8]
1498.50
283.00
109
SEG[43]
553.50
283.00
75
SEG[9]
1471.50
283.00
110
SEG[44]
526.50
283.00
76
SEG[10]
1444.50
283.00
111
SEG[45]
499.50
283.00
77
SEG[11]
1417.50
283.00
112
SEG[46]
472.50
283.00
78
SEG[12]
1390.50
283.00
113
SEG[47]
445.50
283.00
79
SEG[13]
1363.50
283.00
114
SEG[48]
418.50
283.00
80
SEG[14]
1336.50
283.00
115
SEG[49]
391.50
283.00
81
SEG[15]
1309.50
283.00
116
SEG[50]
364.50
283.00
82
SEG[16]
1282.50
283.00
117
SEG[51]
337.50
283.00
83
SEG[17]
1255.50
283.00
118
SEG[52]
310.50
283.00
84
SEG[18]
1228.50
283.00
119
SEG[53]
283.50
283.00
85
SEG[19]
1201.50
283.00
120
SEG[54]
256.50
283.00
86
SEG[20]
1174.50
283.00
121
SEG[55]
229.50
283.00
87
SEG[21]
1147.50
283.00
122
SEG[56]
202.50
283.00
88
SEG[22]
1120.50
283.00
123
SEG[57]
175.50
283.00
89
SEG[23]
1093.50
283.00
124
SEG[58]
148.50
283.00
90
SEG[24]
1066.50
283.00
125
SEG[59]
121.50
283.00
91
SEG[25]
1039.50
283.00
126
SEG[60]
94.50
283.00
92
SEG[26]
1012.50
283.00
127
SEG[61]
67.50
283.00
93
SEG[27]
985.50
283.00
128
SEG[62]
40.50
283.00
94
SEG[28]
958.50
283.00
129
SEG[63]
13.50
283.00
95
SEG[29]
931.50
283.00
130
SEG[64]
-13.50
283.00
96
SEG[30]
904.50
283.00
131
SEG[65]
-40.50
283.00
97
SEG[31]
877.50
283.00
132
SEG[66]
-67.50
283.00
98
SEG[32]
850.50
283.00
133
SEG[67]
-94.50
283.00
99
SEG[33]
823.50
283.00
134
SEG[68]
-121.50
283.00
100
SEG[34]
796.50
283.00
135
SEG[69]
-148.50
283.00
101
SEG[35]
769.50
283.00
136
SEG[70]
-175.50
283.00
102
SEG[36]
742.50
283.00
137
SEG[71]
-202.50
283.00
103
SEG[37]
715.50
283.00
138
SEG[72]
-229.50
283.00
104
SEG[38]
688.50
283.00
139
SEG[73]
-256.50
283.00
105
SEG[39]
661.50
283.00
140
SEG[74]
-283.50
283.00
Ver 1.5a
4/76
2009/7/21
ST7571
PAD No.
Pin Name
X
Y
PAD No.
Pin Name
X
Y
141
SEG[75]
-310.50
283.00
176
SEG[110]
-1255.50
283.00
142
SEG[76]
-337.50
283.00
177
SEG[111]
-1282.50
283.00
143
SEG[77]
-364.50
283.00
178
SEG[112]
-1309.50
283.00
144
SEG[78]
-391.50
283.00
179
SEG[113]
-1336.50
283.00
145
SEG[79]
-418.50
283.00
180
SEG[114]
-1363.50
283.00
146
SEG[80]
-445.50
283.00
181
SEG[115]
-1390.50
283.00
147
SEG[81]
-472.50
283.00
182
SEG[116]
-1417.50
283.00
148
SEG[82]
-499.50
283.00
183
SEG[117]
-1444.50
283.00
149
SEG[83]
-526.50
283.00
184
SEG[118]
-1471.50
283.00
150
SEG[84]
-553.50
283.00
185
SEG[119]
-1498.50
283.00
151
SEG[85]
-580.50
283.00
186
SEG[120]
-1525.50
283.00
152
SEG[86]
-607.50
283.00
187
SEG[121]
-1552.50
283.00
153
SEG[87]
-634.50
283.00
188
SEG[122]
-1579.50
283.00
154
SEG[88]
-661.50
283.00
189
SEG[123]
-1606.50
283.00
155
SEG[89]
-688.50
283.00
190
SEG[124]
-1633.50
283.00
156
SEG[90]
-715.50
283.00
191
SEG[125]
-1660.50
283.00
157
SEG[91]
-742.50
283.00
192
SEG[126]
-1687.50
283.00
158
SEG[92]
-769.50
283.00
193
SEG[127]
-1714.50
283.00
159
SEG[93]
-796.50
283.00
194
COM[1]
-1784.50
283.00
160
SEG[94]
-823.50
283.00
195
COM[3]
-1817.50
283.00
161
SEG[95]
-850.50
283.00
196
COM[5]
-1850.50
283.00
162
SEG[96]
-877.50
283.00
197
COM[7]
-1883.50
283.00
163
SEG[97]
-904.50
283.00
198
COM[9]
-1916.50
283.00
164
SEG[98]
-931.50
283.00
199
COM[11]
-1949.50
283.00
165
SEG[99]
-958.50
283.00
200
COM[13]
-1982.50
283.00
166
SEG[100]
-985.50
283.00
201
COM[15]
-2015.50
283.00
167
SEG[101]
-1012.50
283.00
202
COM[17]
-2048.50
283.00
168
SEG[102]
-1039.50
283.00
203
COM[19]
-2081.50
283.00
169
SEG[103]
-1066.50
283.00
204
COM[21]
-2114.50
283.00
170
SEG[104]
-1093.50
283.00
205
COM[23]
-2147.50
283.00
171
SEG[105]
-1120.50
283.00
206
COM[25]
-2180.50
283.00
172
SEG[106]
-1147.50
283.00
207
COM[27]
-2213.50
283.00
173
SEG[107]
-1174.50
283.00
208
COM[29]
-2246.50
283.00
174
SEG[108]
-1201.50
283.00
209
COM[31]
-2279.50
283.00
175
SEG[109]
-1228.50
283.00
210
COM[33]
-2312.50
283.00
Ver 1.5a
5/76
2009/7/21
ST7571
PAD No.
Pin Name
X
Y
PAD No.
Pin Name
X
Y
211
COM[35]
-2345.50
283.00
246
COM[105]
-3500.50
283.00
212
COM[37]
-2378.50
283.00
247
COM[107]
-3533.50
283.00
213
COM[39]
-2411.50
283.00
248
COM[109]
-3566.50
283.00
214
COM[41]
-2444.50
283.00
249
COM[111]
-3599.50
283.00
215
COM[43]
-2477.50
283.00
250
COM[113]
-3632.50
283.00
216
COM[45]
-2510.50
283.00
251
COM[115]
-3665.50
283.00
217
COM[47]
-2543.50
283.00
252
COM[117]
-3698.50
283.00
218
COM[49]
-2576.50
283.00
253
COM[119]
-3731.50
283.00
219
COM[51]
-2609.50
283.00
254
COM[121]
-3764.50
283.00
220
COM[53]
-2642.50
283.00
255
COM[123]
-3797.50
283.00
221
COM[55]
-2675.50
283.00
256
COM[125]
-3830.50
283.00
222
COM[57]
-2708.50
283.00
257
COM[127]
-3863.50
283.00
223
COM[59]
-2741.50
283.00
258
COMS2
-3896.50
283.00
224
COM[61]
-2774.50
283.00
259
PS0
-3858.00
-315.50
225
COM[63]
-2807.50
283.00
260
VSS1
-3778.00
-315.50
226
COM[65]
-2840.50
283.00
261
PS1
-3698.00
-315.50
227
COM[67]
-2873.50
283.00
262
VDD1
-3618.00
-315.50
228
COM[69]
-2906.50
283.00
263
PS2
-3538.00
-315.50
229
COM[71]
-2939.50
283.00
264
VSS1
-3458.00
-315.50
230
COM[73]
-2972.50
283.00
265
CSB
-3378.00
-315.50
231
COM[75]
-3005.50
283.00
266
RST
-3298.00
-315.50
232
COM[77]
-3038.50
283.00
267
A0
-3218.00
-315.50
233
COM[79]
-3071.50
283.00
268
RWR
-3138.00
-315.50
234
COM[81]
-3104.50
283.00
269
ERD
-3058.00
-315.50
235
COM[83]
-3137.50
283.00
270
D0
-2978.00
-315.50
236
COM[85]
-3170.50
283.00
271
D1
-2898.00
-315.50
237
COM[87]
-3203.50
283.00
272
D2
-2818.00
-315.50
238
COM[89]
-3236.50
283.00
273
D3
-2738.00
-315.50
239
COM[91]
-3269.50
283.00
274
D4
-2658.00
-315.50
240
COM[93]
-3302.50
283.00
275
D5
-2578.00
-315.50
241
COM[95]
-3335.50
283.00
276
D6
-2498.00
-315.50
242
COM[97]
-3368.50
283.00
277
D7
-2418.00
-315.50
243
COM[99]
-3401.50
283.00
278
RST
-2338.00
-315.50
244
COM[101]
-3434.50
283.00
279
CSB
-2258.00
-315.50
245
COM[103]
-3467.50
283.00
280
VDD1
-2178.00
-315.50
Ver 1.5a
6/76
2009/7/21
ST7571
PAD No.
Pin Name
X
Y
PAD No.
Pin Name
X
Y
281
VDD1
-2098.00
-315.50
316
V0I
702.00
-315.50
282
VDD1
-2018.00
-315.50
317
V0I
782.00
-315.50
283
VDD2
-1938.00
-315.50
318
V0S
862.00
-315.50
284
VDD2
-1858.00
-315.50
319
V0O
942.00
-315.50
285
VDD2
-1778.00
-315.50
320
V0O
1022.00
-315.50
286
VDD2
-1698.00
-315.50
321
XV0O
1102.00
-315.50
287
VDD3
-1618.00
-315.50
322
XV0O
1182.00
-315.50
288
VDD3
-1538.00
-315.50
323
XV0S
1262.00
-315.50
289
VSS3
-1458.00
-315.50
324
XV0I
1385.00
-315.50
290
VSS3
-1378.00
-315.50
325
XV0I
1465.00
-315.50
291
VSS2
-1298.00
-315.50
326
XV0I
1545.00
-315.50
292
VSS2
-1218.00
-315.50
327
XV0I
1625.00
-315.50
293
VSS2
-1138.00
-315.50
328
VDD1
1705.00
-315.50
294
VSS2
-1058.00
-315.50
329
VEXT
1785.00
-315.50
295
VSS1
-978.00
-315.50
330
OSC1
1865.00
-315.50
296
VSS1
-898.00
-315.50
331
DCPS
1945.00
-315.50
297
VSS1
-818.00
-315.50
332
VSS1
2025.00
-315.50
298
VSS1
-738.00
-315.50
333
CSEL
2105.00
-315.50
299
VDD2
-658.00
-315.50
334
VD1I
2185.00
-315.50
300
VDD2
-578.00
-315.50
335
VD1I
2265.00
-315.50
301
VDD2
-498.00
-315.50
336
VD1O
2345.00
-315.50
302
VDD2
-418.00
-315.50
337
VGO
2425.00
-315.50
303
VDD3
-338.00
-315.50
338
VGO
2505.00
-315.50
304
VDD3
-258.00
-315.50
339
VGS
2585.00
-315.50
305
MF2
-178.00
-315.50
340
VGI
2665.00
-315.50
306
MF1
-98.00
-315.50
341
VGI
2745.00
-315.50
307
MF0
-18.00
-315.50
342
VGI
2825.00
-315.50
308
DS0
62.00
-315.50
343
VGI
2905.00
-315.50
309
DS1
142.00
-315.50
344
VPP
2985.00
-315.50
310
VMO
222.00
-315.50
345
VPP
3065.00
-315.50
311
VMO
302.00
-315.50
346
VPP
3145.00
-315.50
312
VMO
382.00
-315.50
347
VE
3225.00
-315.50
313
VSS2
462.00
-315.50
348
DUMMY1
3341.00
-315.50
314
V0I
542.00
-315.50
349
DUMMY2
3421.00
-315.50
315
V0I
622.00
-315.50
350
DUMMY3
3501.00
-315.50
Ver 1.5a
7/76
2009/7/21
ST7571
PAD No.
Pin Name
X
Y
351
DUMMY4
3581.00
-315.50
352
DUMMY5
3661.00
-315.50
353
DUMMY6
3741.00
-315.50
354
DUMMY7
3821.00
-315.50
Note:
1.
CSEL=H.
2.
Unit: um.
Ver 1.5a
8/76
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ST7571
5. BLOCK DIAGRAM
DB0
DB1
DB2
DB3
DB4
DB5
DB6(SI)
DB7(SCL)
ERD
RWR
A0
CSB
RST
PS0
PS1
PS2
2009/7/21
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Ver 1.5a
DS0
DS1
MF0
MF1
MF2
Fig.2 Block diagram
ST7571
6. PIN DESCRIPTION
6.1 POWER SUPPLY
Power Supply Pin Description
Name
I/O
Description
VDD1
Power
VDD2
Power
VDD3
Power
VSS1
Power
Ground for digital circuit. VSS1, VSS2 & VSS3 should be connected together by FPC.
VSS2
Power
Ground for analog circuit (booster), it should be connected together by FPC.
VSS3
Power
Ground for sensitive circuit (Vref regulator), it should be connected together by FPC.
Power supply for digital circuit.
If VDD1 is the same level as VDD2, they can be connected together by FPC.
Power supply for analog circuit (booster).
Power supply for sensitive circuit (internal Vref regulator).
VDD3 is the same level as VDD2, and they should be connected together by FPC.
6.2 LCD DRIVER SUPPLY
LCD Driver Supply Pin Description
Name
I/O
Description
V0 is the LCD driving voltage for common circuits at negative frame.
V0O
V0I
V0O is the output of V0 regulator. V0S is the feedback of V0 regulator.
Power
V0I is the V0 input of common circuits.
Be sure that: V0 ≥ VG > VM > VSS ≥ XV0 (under operation).
V0S
V0O, V0I & V0S should be connected together by FPC.
XV0 is the LCD driving voltage for common circuits at positive frame.
XV0O
XV0I
Power
XV0S
XV0O is the output of XV0 regulator. XV0S is the feedback of XV0 regulator.
XV0I is the XV0 input of common circuits.
XV0O, XV0I & XV0S should be connected together by FPC.
VG is the LCD driving voltage for segment circuits.
A storage capacitor on FPC or system for VG is required.
VGO
VGI
Power
VGS
VGO is the output of VG regulator. VGS is the feedback of VG regulator.
VGI is the VG input of segment circuits.
VGO, VGI & VGS should be connected together by FPC.
Be aware that: 1.8V ≤ VG < VDD2.
VMO is the output of VM, which is the LCD driving voltage for common circuits.
A storage capacitor on FPC or system for VM is required.
Be aware that: 0.7V < VM < VDD2.
VMO
Power
When the internal power circuit is active, the VG and VM are generated according to the bias
setting as shown below:
LCD bias
VG
VM
1/N bias
(2/N) x V0
(1/N) x V0
NOTE: N = 5 to 12
Ver 1.5a
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ST7571
6.3 SYSTEM CONTROL
System Control Pin Description
Name
I/O
VEXT
O
OSC1
I
Description
Reserved for testing, must set with floating.
Connect OSC1 to VDD1.
This pin selects the supply voltage source of the digital circuit.
DCPS
I
If system VDD1 is 3.0V ~ 3.3V, set DCPS=L to select Internal Regulator as digital circuit power.
If system VDD1 is 1.8V ~ 2.8V, set DCPS=H to select VDD1 as digital circuit power.
Select COM output sequence.
CSEL
I
Fix CSEL=H to enable “Interlace” mode (recommended).
In interlace mode, COM2n (even number) is in the one side, COM(2n+1) (odd number) is in the
opposite side.
Short VD1I with VD1O externally by ITO or FPC.
VD1I
VD1O
O
VD1I is the power supply pin of the internal digital circuits.
When DCPS=L, VD1O is the output of the internal digital power regulator.
When DCPS=H, VD1O is provided by VDD1.
VE
I
When writing EEPROM, VE should be pull-high externally.
VPP
I
When writing EEPROM, it needs external power supply voltage.
MF[2:0]
I
Reserve for testing only, recommend setting to [ MF2,MF1,MF0 = 0,0,0 ].
DS[1:0]
I
Reserve for testing only, recommend setting to [ DS1,DS0 = 0,0 ].
Notes:
1.
When system control pin set to “H”, it should be connected to VDD1.
2.
When system control pin set to “L”, it should be connected to VSS1.
3.
CSEL function is illustrated as the figure below:
COM127
COM126
COM125
COM124
CSEL=“H”
COM5
COM4
COM3
COM2
COM1
COM0
1
2
62
63
64
65
194
195
196
256
257
258
Gold Bump Face Up
Ver 1.5a
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2009/7/21
ST7571
6.4 MICROPROCESSOR INTERFACE
Microprocessor Interface Pin Description
Name
I/O
RST
I
Description
Reset input pin.
When RST is “L”, initialization is executed.
PS[2:0] select the microprocessor interface:
PS[2:0]
I
PS2
PS1
PS0
Selected Interface Mode
L
L
H
Parallel 8080 MPU Interface
L
H
H
Parallel 6800 MPU Interface
L
L
L
Serial 3-Line Interface
L
H
L
Serial 4-Line Interface
H
L
L
Serial I C Interface
2
* NOTE: It is impossible to read data from the on-chip DDRAM.
For detailed interface connection, please refer to Section 7.1 and Application Circuits.
Chip select input pin.
2
CSB
I
The interface is enabled only when CSB is "L" (except I C Interface).
When CSB is non-active, DB[7:0] are high impedance.
2
CSB is not used in I C interface; it is recommended to fix CSB at “H” by VDD1.
Register select input pin.
A0
I
A0 = “H”: DB0 to DB7 are display data.
A0 = “L”: DB0 to DB7 are control command.
2
A0 is not used in serial 3-Line and I C interface; it is recommended to fix A0 at “H” by VDD1.
Write execution control pin.
RWR
I
PS2
PS1
PS0
MPU Type
RWR
L
H
H
6800-series
R/W
L
L
H
8080-series
/WR
Description
Write control input pin.
Keep this pin at “L” level.
The data on DB[7:0] are latched at the rising
edge of the /WR signal.
Read / Write execution control pin.
ERD
Ver 1.5a
I
PS2
PS1
PS0
MPU Type
ERD
L
H
H
6800-series
E
L
L
H
8080-series
/RD
12/76
Description
The data on DB[7:0] are latched at the falling
edge of the E signal.
Keep this pin at “H” level.
2009/7/21
ST7571
Name
I/O
Description
When using parallel interface:
I
DB[7:0] are 8-bit data bus.
DB[7:0] are connected to the 8-bit data bus of a standard microprocessor.
When chip select is not active (CSB=H), DB[7:0] are high impedance.
When using 3-Line/4-Line serial interface:
DB7: serial input data (SID).
I
DB6: serial input clock (SCLK).
DB[5:0] are high impedance and must be fixed to “H”.
DB[7:0]
When chip select is not active (CSB=H), DB[7:0] are high impedance.
2
When using I C interface:
DB7: SCL, serial clock input.
I/O
DB[6:4]: SDA_IN, serial input data.
2
DB[3:2]: SDA_OUT, output the acknowledge signal of the I C interface protocol.
DB[6:2] must be connected together (SDA).
*1
2
DB[1:0]: SA[1:0], I C slave address bits of ST7571. Must connect to VDD1 or VSS1.
1.
2
By connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully I C interface compatible. Separating
acknowledge-output from serial data input is advantageous for chip-on-glass (COG) applications. In COG
applications, the ITO resistance and the pull-up resistor will form a voltage divider, which affects acknowledge-signal
level. Larger ITO resistance will raise the acknowledged-signal level and system cannot recognize this level as a valid
logic “0” level. By separating SDA_IN from SDA_OUT, the IC can be used in a mode that ignores the acknowledge-bit.
For applications which check acknowledge-bit, it is necessary to minimize the ITO resistance of the SDA_OUT trace
to guarantee a valid low level.
2.
After VDD1 is turned ON, any MPU interface pins cannot be left floating.
Ver 1.5a
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ST7571
6.5 LCD DRIVER OUTPUTS
LCD Driver Output Pin Description
Name
I/O
Description
LCD segment driver outputs. The display data and frame signal control the output .
Display Data
SEG0
to
O
SEG127
Frame
Segment Driver Output Voltage
Normal Display
Reverse Display
H
Positive
VG
VSS
H
Negative
VSS
VG
L
Positive
VSS
VG
L
Negative
VG
VSS
VSS
VSS
Display off / Power save mode
LCD common driver outputs. The internal scan signal and frame signal control the output voltage.
COM0
to
O
COM127
Scan Signal
Frame
Common Driver Output Voltage
H
Positive
XV0
H
Negative
V0
L
Positive
VM
L
Negative
VM
Display off / Power save mode
COMS2
O
COMS1
VSS
Common output for the icons.
The outputs at COMS1 and COMS2 are the same. When not used, these pins should be left open.
Recommend I/O Resistance
PIN Name
ITO Resister
PS[2:0], OCS1, VEXT, DCPS, MF[2:0], DS[1:0]
<5KΩ
VDD1, VDD2, VDD3, VSS1, VSS2, VSS3, VPP, VD1I, VD1O
<100Ω
CSB , ERD, RWR, A0, DB[7:0], VE
<1KΩ
V0, VG, VM, XV0, VD1
<500Ω
RST
<10KΩ
Note:
1.
These Limitations include the bottleneck of ITO layout.
2.
Keep the ITO resistance of COM0 ~ COM127 be equal, and so it is of SEG0 ~ SEG127.
3.
If using I C interface mode, the resistance of SDA signal is recommended to be lower than 300Ω
2
(if the system pull up resistor is 4.7KΩ).
4.
If LCD panel size is larger than 1.5”, the resistance limitations will be lower.
5.
To avoid the noise in different power system affect other power system, please separate different power source on
ITO layout. Please refer to the ITO Layout Reference.
6.
The V0, XV0 and VG power circuits have output pins, input pins and a sensor input. To avoid the power noise affects
the sensor of the power circuits. The trace should be separated by ITO and should be connected together by FPC.
Ver 1.5a
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ST7571
ITO Layout Reference
VSS 1
VSS1
VSS1
VSS1
VSS2
VSS 2
VSS2
VSS2
VSS3
VSS3
VDD3
VDD3
VDD2
VDD 2
VDD2
VDD2
VDD1
VDD1
VDD1
VG I
VG I
VG I
VG I
VGS
VGO
VGO
XV 0 I
XV 0 I
XV 0 I
XV 0 I
XV0S
XV0O
XV0O
V0O
V0O
V0S
V0 I
V0 I
V0 I
V0 I
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Ver 1.5a
ST7571
7. FUNCTIONAL DESCRIPTION
7.1 MICROPROCESSOR INTERFACE
Chip Select Input
CSB pin is used for chip selection. ST7571 can interface with an MPU when CSB is “L”. When CSB is “H”, the inputs of A0,
ERD and RWR with any combination will be ignored and DB[7:0] are high impedance. In 3-Line and 4-Line serial interface,
the internal shift register and serial counter are reset when CSB is “H”.
Parallel / Serial Interface
ST7571 has types of interface for kinds of MPU. The MPU interface is selected by PS[2:0] pins as shown in Table 1. The
read-function is not available.
Table 1 Parallel / Serial Interface Mode
PS2
PS1
PS0
Type
CSB
A0
ERD
RWR
L
L
/RD
/WR
H
Parallel
CSB
A0
L
H
E
R/W
L
L
--L
CSB
----Serial
L
H
A0
H
L
L
--------Note: The un-used pins are marked as “---” and should be fixed to “H” by VDD1.
MPU Interface
8080-series parallel interface
6800-series parallel interface
3-Line SPI interface
4-Line SPI interface
2
I C Interface
Parallel Interface (PS2 = “L” & PS0 = “H”)
The 8-bit data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in Table 2. The type of data
transfer is determined by signals at A0, ERD and RWR as shown in Table 3.
Table 2 Microprocessor Selection for Parallel Interface
PS1
L
H
Common
A0
L
H
CSB
CSB
CSB
A0
A0
A0
ERD
RWR
/RD
/WR
E
R/W
Table 3 Parallel Data Transfer
6800-series
ERD (E)
H
H
DB[7:0]
DB[7:0]
DB[7:0]
8080-series
RWR (R/W)
L
L
ERD (/RD)
H
H
MPU bus
8080-series
6800-series
Description
RWR (/WR)
L
L
Writes to internal register (instruction)
Display data write
Serial Interface Selection
By setting PS[2:0], one of the Serial Interfaces can be selected. In 3-Line or 4-Line SPI mode, the internal 8-bit shift register
and 3-bit counter are reset when IC is not active (CSB=“H”).
Serial mode
PS[2:0]
CSB
A0
ERD
RWR
DB[7:0]
3-Line SPI
L, L, L
CSB
---
---
---
DB7=SID, DB6=SCLK
4-Line SPI
L, H, L
CSB
A0
---
---
DB[5:0]= ---
H, L, L
---
---
---
---
2
2
I C SPI
Refer to I C Interface. DB7=SCL, DB[6:4]=SDA_IN,
DB[3:2]=SDA_OUT, DB[1:0]=SA[1:0]
Note: The un-used pins are marked as “---” and should be fixed to “H” by VDD1.
Note:
1.
The pin setting to be “H” should connect to VDD1.
2.
The pin setting to be “L” should connect to VSS1.
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ST7571
4-Line SPI Mode (PS0 = “L”, PS1 = “H”, PS2 = “L”)
When IC is active (CSB=“L”), serial data (SID) and serial clock (SCLK) inputs are enabled. When ST7571 is not active
(CSB=“H”), the internal 8-bit shift register and 3-bit counter are reset. The display data/command indication is controlled by
the register selection pin (A0). The signals transferred on data bus will be display data when A0 is high and will be
instruction when A0 is low. The read feature is not supported. Serial data on SID is latched at the rising edge of serial clock
th
on SCLK. After the 8 serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address
pointer will be increased by one automatically after each byte of DDRAM access.
Fig. 3
4-line SPI Timing
3-Line SPI Mode (PS0 = “L”, PS1 = “L”, PS2= “L”)
In 3-Line mode, default message from MCU is command. The Display Data Length command (2 bytes command) must be
set before writing display data into Display Data RAM, after the display data is sent over, the next message is turned to be
command. Signals on SID are latched at the rising edge of SCLK. After receiving 8-bit display data, the column address
pointer of DDRAM will be increased by one automatically.
(1)
Set Page and Column Address.
Command
(2)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Set Page Address
1
0
1
1
P3
P2
P1
P0
Set Column Address MSB
0
0
0
1
0
X7
X6
X5
Set Column Address LSB
0
0
0
0
X4
X3
X2
X1
Set Display Data Length (DDL) command and No. of Data Bytes.
Command
Set Display Data Length (DDL)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
1
0
1
0
0
0
Set No. of Data Bytes
(3)
Display Data Length (bytes)
This figure is an example for 104 Data bytes to be transferred.
Fig. 4
3-Line SPI Timing (A0 is not used)
“Set Display Data Length” is used in 3-Line SPI mode only. It is 2-byte instruction: the first one informs the LCD driver and
the second one sets the counter of input data (in bytes). After these two commands, the following messages will be data, till
the data counter is cleared. If data is stopped during transmitting, it is not a valid data. A new data (8 bits) must write again.
NOTE: If CSB is “H” before the end of a transmission, it stops this transfer and the next access should be re-initialized.
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ST7571
2
I C Interface (PS0= “L”, PS1= “L”, PS2= “H”)
2
The I C Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial
Data line (SDA) and a Serial Clock line (SCLK). Both lines must be connected with a pull-up resistor which drives SDA and
SCLK to high when the bus is not busy. Data transfer can be initiated only when the bus is not busy.
2
2
The I C interface of ST7571 supports write access and read of acknowledge-bit. The I C interface receives and executes
2
the commands sent via the I C Interface. It also receives RAM data and sends it to the Display RAM.
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of
the clock pulse because changes of SDA line at this time will be interpreted as START or STOP. Bit transfer is illustrated in
Fig 5.
Fig 5.
Bit transfer
START AND STOP CONDITIONS
Both SDA and SCLK lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of SDA, while SCLK is HIGH
is defined as the START condition (S). A LOW-to-HIGH transition of SDA while SCLK is HIGH is defined as the STOP
condition (P). The START and STOP conditions are illustrated in Fig 6.
Fig 6.
Ver 1.5a
Definition of START and STOP conditions
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ST7571
SYSTEM CONFIGURATION
The system configuration is illustrated in Fig 7 and some word-definitions are explained below:
- Transmitter: the device which sends the data to the bus.
- Receiver: the device which receives the data from the bus.
- Master: the device which initiates a transfer, generates clock signals and terminates a transfer.
- Slave: the device which is addressed by a master.
- Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message.
- Arbitration: the procedure to ensure that, if more than one master tries to control the bus simultaneously, only one is
allowed to do so and the message is not corrupted.
- Synchronization: procedure to synchronize the clock signals of two or more devices.
Fig 7.
System configuration
ACKNOWLEDGEMENT
Each byte of eight bits is followed by an acknowledge-bit. The acknowledge-bit is a HIGH signal put on SDA by the
transmitter during the time when the master generates an extra acknowledge-related clock pulse. A slave receiver which is
addressed must generate an acknowledge-bit after the reception of each byte. A master receiver must also generate an
acknowledge-bit after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull-down the SDA line during the acknowledge-clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end-of-data to the slave transmitter by not generating a acknowledge-bit on the last byte that has
been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a
2
STOP condition. Acknowledgement on the I C Interface is illustrated in Fig 8.
2
Fig 8. Acknowledgement of I C Interface
2
I C INTERFACE PROTOCOL
ST7571 supports command/data write to addressed slaves on the bus.
2
Before any data is transmitted on the I C Interface, the device, which should respond, is addressed first. Four 7-bit slave
addresses (0111100, 0111101, 0111110 and 0111111) are reserved for ST7571. The least significant 2 bits of the slave
address is set by connecting SA0 and SA1 to either logic 0 (VSS1) or logic 1 (VDD1).
2
The I C Interface protocol is illustrated in Fig 9.
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ST7571
2
The sequence is initiated with a START condition (S) from the I C Interface master, which is followed by the slave address.
2
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I C Interface transfer. After
acknowledgement, one or more command words are followed and define the status of the addressed slaves. A command
word consists of a control byte, which defines Co and A0, and a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a
cleared Co bit, only data byte(s) will follow. The state of the A0 bit defines whether the following data bytes are interpreted
as commands or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last
control byte either a series of display data bytes or command data bytes may follow (depending on the A0 bit setting).
If the A0 bit of the last control byte is set to logic 1, these data bytes (display data bytes) will be stored in the display RAM at
the address specified by the internal data pointer. The data pointer is automatically updated and the data is directed to the
intended ST7571 device.
If the A0 bit of the last control byte is set to logic 0, these data bytes (command data byte) will be decoded and the setting of
ST7571 will be changed according to the received commands.
Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the bus master
issues a STOP condition (P). If no acknowledge is generated by the master after a byte, the driver stops transferring data to
A0
Co
Co=0
A0
Co=1
A0
SA1
SA0
R/W
Co
R/W
A0
SA1
SA0
the master.
Fig 9.
Co
0
1
Ver 1.5a
2
I C Interface protocol
Last control byte. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by a STOP or RE-START condition.
Another control byte will follow the data byte.
20/76
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ST7571
Data Transfer
ST7571 uses bus holder and internal data bus for data transfer by the MPU. When writing data from the MPU to on-chip
RAM, data is automatically transferred from the bus holder to the RAM as shown in Fig. 10 and Fig. 11.
Fig. 10
External Timing from MPU
Fig. 11
Ver 1.5a
Internal Timing of IC
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ST7571
7.2 DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 129-row by 128-column addressable array. Each pixel can be
selected when the page and column addresses are specified. The 129 rows are divided into 16 pages of 8 lines and the 17
th
page with a single line (DB0 only). Data is written to the 8 lines of each page directly through DB0 to DB7. The display data
of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The LCD controller and MPU interface
operate independently, data can be written into RAM at the same time when data is being displayed without flicker on LCD.
Page Address Circuit
It incorporates 4-bit Page Address register changed by only the “Set Page” instruction. Page Address 16 is a special RAM
area for the icons and display data DB0 is only valid. The page address is set from 0 to 15, and Page 16 is for Icon page.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line
Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of
on-chip RAM. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter
circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL
signal and generates the line address for transferring the 128-bit RAM data to the display data latch circuit. When icon is
enabled by setting icon control register, display data of icons are not scrolled because the MPU can not access Line
Address of icons.
Column Address Circuit
When set Column Address MSB / LSB instruction is issued, 7-bit (X[7:1]) are set and lowest bit (X0) is set to “0”. The
internal column address (X[7:0]) is increased by 1 automatically after each byte of data access (write data). After sequential
access twice, the column address (X[7:1]) will point to the next column address. Please refer to Fig. 12.
Segment Control Circuit
This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF
instructions without changing the data in the Display Data RAM.
SEG Output
Column Address
X[7:1]
Internal column
address
X[7:0]
Display Data
(MX=0)
LCD panel
display
Display data
(MX=1)
LCD panel
display
SEG
0
SEG
1
SEG
2
SEG
3
…
SEG
124
SEG
125
SEG
126
SEG
127
00H
01H
02H
03H
…
7CH
7DH
7EH
7FH
00
01
02
03
04
05
06
07
…
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
0
0
1
0
0
…
1
1
1
0
0
1
0
0
0
0
0
1
1
0
1
1
…
0
0
0
1
1
0
1
1
…
…
Fig. 12 The Relationship between the Column Address and The Segment Outputs
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7.3 LCD DISPLAY CIRCUITS
Oscillator
This is on-chip Oscillator without external resistor. When the internal oscillator is used, this pin must connect to VDD1; when
the external oscillator is used, this pin could be input pin. This oscillator signal is used in the voltage converter and display
timing generation circuit.
Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL (internal), generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is
generated in synchronization with the display clock and the display data latch circuit latches the 128-bit display data in
synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the
access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (FR) which
enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start
signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving
waveform and internal timing signal are shown in Fig. 13.
127 128 0
1
2 3
4 5
6 7
8 9
126
120
122 124
128
121 123
125
127
0
10 11
1 2
3 4
CL(Internal)
FR(Internal)
Frame
COM0
COM10
SEGn
Fig. 13 Frame AC Driving Waveform (Duty Ratio: 1/129)
Fig. 14
Ver 1.5a
N-Line Inversion Driving Waveform (N=5,Duty Ratio=1/129)
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Partial Display on LCD
The ST7571 realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing
the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the
instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages. The
partial display duty ratio could be set from 16 ~ 128.
If the partial display region is out of the Max. Display range, it would be no operation.
-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Fig. 15
Reference Example for Partial Display
-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Fig. 16 Partial Display (Partial Display Duty=16, initial COM0=0)
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-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Fig. 17 Moving Display (Partial Display Duty=16, initial COM0=8)
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7.4 POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power
consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage
follower circuits. They are controlled by power control instruction.
Voltage Regulator Circuits
The internal Voltage Regulator circuit provides the liquid crystal operating voltage (V0) by adjusting resistors (SRR and EV).
The parameter “SRR” can be set by “Select Regulator Register”.
The parameter “EV” can be set by “Set Electronic Volume Register”, and the range of EV is 0~63.
(63- EV)
V0 = SRR x (1 - ——————) x 2.1
210
Table 5 Internal Regulator Ratio depending on 3-bit Data (R2 R1 R0)
3-bit data settings (R2 R1 R0)
000
001
010
011
100
101
110
111
2.3
3.0
3.7
4.4
5.1
5.8
6.5
7.2
SRR
(Select Regulator Ratio)
Fig. 18 shows V0 voltage measured by adjusting regulator register ratio and 6-bit electronic registers for each temperature
coefficient at Ta = 25°C. The recommended range of EV setting is level 16 ~ 47.
16
14
12
000
001
10
010
011
8
100
101
6
110
111
4
2
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
9
12
6
3
0
0
Fig. 18 Electronic Volume Level (25°C)
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Voltage Follower Circuits
V0 is resistively divided into two voltage levels (VG, VM), and those output impedance are converted by the Voltage
Follower for increasing drive capability. Table 6 shows the relationship between VG to VM level and each duty ratio.
Table 6 The Relationship between V1 to V4 Level and Each Duty Ratio
LCD Bias
VG
VM
Remarks
1/N
2/N x V0
1/N x V0
N = 5 to 12
Booster Efficiency
The Booster Efficiency Command could be used to choose the best Booster performance. Booster Efficiency (Level1~4)
can easily set the best Booster performance with suitable current consumption. If the Booster Efficiency is set to a higher
level (level2 is higher than level1), the Boost Efficiency is better than lower level, and it just needs few more power
consumption current. When the LCD Panel loading is heavier, the performance of Booster Efficiency will be lower. We could
select higher BE level to improve the efficiency with just few more current increased.
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7.5 RESET CIRCUITS
Setting RST to “L” can initialize internal function. RST pin is connected to the reset pin of MPU and initialization by RST pin
is essential before operating. Please note the hardware reset is not same as the software reset. When RST becomes “L”,
the hardware reset procedure will start. When RESET instruction is executed, the software reset procedure will start. The
procedure is listed below:
Procedure
Hardware Reset
Software Reset
Clear Serial Counter and Shift Register (if using Serial Interface)
V
V
Page Address, P[3:0]=0 (Page 0)
V
V
Column Address, X[7:0]=00h (Column 0)
V
V
Display ON/OFF, D=0 (Display OFF)
V
X
Reverse Display, REV=0 (Normal)
V
X
Entire Display ON, EON=0 (Normal)
V
X
Icon Control, ION=0 (OFF)
V
X
Start Line, S[6:0]=0 (1 line of DDRAM)
V
V
COM0, C[6:0]=0 (COM0 Pin)
V
X
Display Duty, L[7:0]=0 (1/129)
V
X
N-Line, N[4:0]=0 (N-Line OFF)
V
X
Power Control, VC=0, VR=0, VF=0 (Internal Power OFF)
V
X
Booster Efficiency, BE[1:0]=0,1 (Level 2)
V
X
Regulator Resistor, R[2:0]=0,0,0
V
V
Contrast Control, EV[5:0]=20h
V
V
LCD Bias, BS[2:0]=1,1,1 (1/12 bias)
V
X
Frame Rate, FR[3:0]=0,0,0,0 (77Hz)
V
X
COM Scan Direction, MY=0 (Normal)
V
X
SEG Scan Direction, MX=0 (Normal)
V
X
Oscillator Circuit: OFF
V
X
Power-Save Mode, P=0 (Release)
V
X
Display Data Length, DL[7:0]=00h (for 3-Line serial interface only)
V
V
st
After power-on, RAM data are undefined and the display status is “Display OFF”. It’s recommended to initialize the whole
DDRAM (ex: fill all 00h or write a display pattern) before turning the Display ON (including the ICON RAM as well). Besides,
the system power is not stable at the time that the power is just turned ON. After the system power is stable, a hardware
reset is required to initialize internal registers.
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8. INSTRUCTIONS
Instruction
A0 R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
0
0
0
0
0
FR3
FR2
FR1
FR0
BE1
BE0
--
0
1
0
Set Mode
Write Display Data
Description
Section
2-byte instruction
FR[3:0]: Set frame frequency
Write data
9.1.1
BE[1:0]: Set booster efficiency
Write data into DDRAM
9.1.2
ION=0: Disable Icon function
Set Icon
0
0
1
0
1
0
0
0
1
ION
ION=1: Enable Icon function
9.1.3
and set Page Address = 16
Set Page Address
0
0
1
0
1
1
P3
P2
P1
P0
Set Page Address
9.1.4
Set Column Address (MSB)
0
0
0
0
0
1
0
X7
X6
X5
Set MSB of Column Address
9.1.5
Set Column Address (LSB)
0
0
0
0
0
0
X4
X3
X2
X1
Set LSB of Column Address
9.1.6
Display ON/OFF
0
0
1
0
1
0
1
1
1
D
D=0: Display OFF
9.1.7
D=1: Display ON
0
0
0
1
0
0
0
0
--
--
2-byte instruction. Specify Line
Address for the 1st display line
Set Display Start Line
0
0
--
S6
S5
S4
S3
S2
S1
S0
0
0
0
1
0
0
0
1
--
--
0
0
--
C6
C5
C4
C3
C2
C1
C0
0
0
0
1
0
0
1
0
--
--
2-byte instruction. Set display
0
0
L7
L6
L5
L4
L3
L2
L1
L0
duty
0
0
0
1
0
0
1
1
--
--
2-byte instruction. Set N-line
0
0
--
--
--
N4
N3
N2
N1
N0
inversion counter
Release N-line Inversion
0
0
1
1
1
0
0
1
0
0
Reverse Display
0
0
1
0
1
0
0
1
1
REV
Set COM0
9.1.8
of DDRAM (vertical scrolling).
2-byte instruction. Specify a
COM pin to be COM0 (moving
9.1.9
partial display window).
Set Display Duty
9.1.10
Set N-line Inversion
9.1.11
Exit N-line inversion mode
9.1.12
REV=0: Normal display
9.1.13
REV=1: Reverse display
EON=0: Normal display
Entire Display ON
0
0
1
0
1
0
0
1
0
EON
9.1.14
EON=1: Entire display ON
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Instruction
A0 R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Power Control
0
0
0
0
1
0
1
VC
VR
VF
Select Regulator Register
0
0
0
0
1
0
0
R2
R1
R0
Description
Section
Set internal power ON/OFF
9.1.15
Select internal Regulator
9.1.16
resistor
0
0
1
0
0
0
0
0
0
1
0
0
--
--
EV5
EV4
EV3
EV2
EV1
EV0
0
0
0
1
0
1
0
B2
B1
B0
2-byte instruction. Select EV for
Set Contrast
Select LCD bias
9.1.17
internal Regulator’s reference
Select LCD bias
9.1.18
Set COM scan direction:
Set COM Scan Direction
0
0
1
1
0
0
MY
--
--
--
MY=0: Normal direction
9.1.19
MY=1: Reverse direction
Set SEG scan direction:
Set SEG Scan Direction
0
0
1
0
1
0
0
0
0
MX
MX=0: Normal direction
9.1.20
MX=1: Reverse direction
Oscillator ON
0
0
1
0
1
0
1
0
1
1
Set Power-Save Mode
0
0
1
0
1
0
1
0
0
P
Turn ON internal Oscillator
9.1.21
P=0: Normal mode
9.1.22
P=1: Enable Power-Save mode
Release Power-Save Mode
0
0
1
1
1
0
0
0
0
1
Exit Power-Save mode
9.1.23
RESET
0
0
1
1
1
0
0
0
1
0
Software reset
9.1.24
--
--
1
1
1
0
1
0
0
0
2-byte instruction. Set the data
--
--
DL7
DL6
DL5
DL4
DL3
DL2
DL1
DL0
NOP
0
0
1
1
1
0
0
0
1
1
No operation
9.1.26
Reserved
0
0
1
1
1
0
0
0
0
0
Do NOT use
--
Reserved
0
0
1
1
1
0
1
1
1
0
Do NOT use
--
Reserved
0
0
1
1
1
1
--
--
--
--
Reserved for testing
--
Extension Command Set1
0
0
1
1
1
1
1
1
0
TE1
TE1=1: Enter extension Mode1
9.1.27
Extension Command Set2
0
0
1
1
0
1
0
0
0
TE2
TE2=1: Enter extension Mode2
9.1.28
Extension Command Set3
0
0
0
1
1
1
1
0
1
TE3
TE3=1: Enter extension Mode3
9.1.29
Set Display Data Length
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9.1.25
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counter in 3-Line SPI only
2009/7/21
ST7571
Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Description
EXTENSION COMMAND SET 1
Increase Vop offset
0
0
0
1
0
1
0
0
0
1
Increase vop offset by 1step
Decrease Vop offset
0
0
0
1
0
1
0
0
1
0
Decrease vop offset by 1 step
Return normal mode
0
0
0
0
0
0
0
0
0
0
Return normal mode
EXTENSION COMMAND SET 2
Disable autoread
0
0
1
0
1
0
1
0
1
0
Disable autoread
Enter EEPROM mode
0
0
0
0
0
1
0
0
1
1
Enter EEPROM mode
Enable read mode
0
0
0
0
1
0
0
0
0
0
Enable read mode
Set read pulse
0
0
0
1
1
1
0
0
0
1
Set read pulse width
Exit EEPROM mode
0
0
1
0
0
0
0
0
1
1
Exit EEPROM mode
Enable erase mode
0
0
0
1
0
0
1
0
1
0
Enable erase mode
Set erase pulse
0
0
0
1
0
1
0
1
0
1
Set erase pulse width
Enable write mode
0
0
0
0
1
1
0
1
0
1
Enable write mode
Set write pulse
0
0
0
1
1
0
1
0
1
0
Set write pulse width
Return normal mode
0
0
0
0
0
0
0
0
0
0
Return normal mode
EXTENSION COMMAND SET 3
Select Black/White or Gray mode
Set Color Mode
0
0
0
0
0
1
0
0
0
B/G
B/G=1: Black/White mode;
B/G=0: Gray mode (default)
Return normal mode
0
0
0
0
0
0
0
0
0
0
Return normal mode
Note: Do NOT use non-specified instructions in any extension command mode.
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9. INSTRUCTION DESCRIPTION
9.1.1 Set Mode
This 2-byte instruction specifies frame frequency (FR[3:0]) and booster efficiency (BE[1:0])
st
The 1 Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
0
0
0
nd
Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
FR3
FR2
FR1
FR0
BE1
BE0
x’
0
The 2
Frame Frequency
FR[3:0] specifies the frame frequency:
FR3
FR2
FR1
FR0
Frame Frequency
0
0
0
0
77 Hz ±10%
0
0
0
1
51 Hz ±20%
0
0
1
0
55 Hz ±20%
0
0
1
1
58 Hz ±20%
0
1
0
0
63 Hz ±20%
0
1
0
1
67 Hz ±20%
0
1
1
0
68 Hz ±20%
0
1
1
1
70 Hz ±20%
1
0
0
0
73 Hz ±20%
1
0
0
1
75 Hz ±20%
1
0
1
0
80 Hz ±20%
1
0
1
1
85 Hz ±20%
1
1
0
0
91 Hz ±20%
1
1
0
1
102 Hz ±20%
1
1
1
0
113 Hz ±20%
1
1
1
1
123 Hz ±20%
Booster Efficiency
The efficiency of internal Booster is configurable by BE[1:0]. The optimized setting is Level-3.
BE1
BE0
0
0
Booster Efficiency Level 1
0
1
Booster Efficiency Level 2
1
0
Booster Efficiency Level 3
1
1
Booster Efficiency Level 4
Ver 1.5a
Description
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9.1.2 Write Display Data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and
page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data
to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written.
A0
R/W
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write data
Write Data Flow
Set Page Address (0~15)
Set Column Address
Write Data
Column = Column +1
(Auto Increment)
Write more Data?
Yes
No
Write Data End
Fig. 20 Sequence for Writing Display Data
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9.1.3 Set Icon
This instruction makes Icon function enable or disable. After reset, the Icon function is disabled (ION=0). When ION=“1”,
Icon display is enabled and the page address is set to “16” for updating icon data (it is impossible to set page address to
“16” by Set Page Address instruction). Therefore, when writing data for icons, “Set Icon” instruction is necessary before
writing icon data. It set the page address to “16” before writing icon data. When “ION” is “0”, Icon display function is not
available.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
0
1
ION
ION
Description
0
Disable Icon function
1
Enable Icon display and set Page Address to “16”.
Fig. 20 Sequence for Writing Display Data
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9.1.4 Set Page Address
This instruction sets the Page Address of display data RAM from the microprocessor into the page address register. Any
RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address,
the Page Address defines the address of the display RAM to write display data. Changing the Page Address doesn’t affect
the display status. Set Page Address instruction can not be used to set the page address to “16”. Use ICON control register
ON/OFF instruction to set the page address to “16”.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
1
P3
P2
P1
P0
P3
P2
P1
P0
Page
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
1
1
1
0
14
1
1
1
1
15
9.1.5 & 9.1.6 Set Column Address
These instructions set the specified column address of DDRAM into the internal Column Address register. The internal
Column Address register points to the address of DDRAM for accessing display data. The Column Addresses register is
automatically increased by 1 when the microprocessor accesses the display data in DDRAM.
Set Column Address (MSB)
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
0
X7
X6
X5
Set Column Address (LSB)
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
X4
X3
X2
X1
X7
X6
X5
X4
X3
X2
X1
Column Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
1
1
1
1
1
1
0
126
1
1
1
1
1
1
1
127
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9.1.7 Display ON / OFF
This instruction turns the display ON or OFF. It has priority over Entire Display ON/OFF and Reverse Display ON/OFF.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
1
1
1
DON
DON = 1: display ON
DON = 0: display OFF
9.1.8 Set Display Start Line
This 2-byte instruction sets the line address of DDRAM to determine the first display line. The display data of the selected
line will be displayed at the top of row (COM0) on the LCD panel.
st
The 1 Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
0
0
0
x
x
nd
Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
x
S6
S5
S4
S3
S2
S1
S0
S6
S5
S4
S3
S2
S1
S0
Line address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
2
0
0
0
0
0
1
1
3
:
:
:
:
:
:
:
:
1
1
1
1
1
0
0
124
1
1
1
1
1
0
1
125
1
1
1
1
1
1
0
126
1
1
1
1
1
1
1
127
The 2
Fig.
Ver 1.5a
21
Sequence for Setting Display Start Line
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9.1.9 Set COM0
This 2-byte instruction set the initial row (COM) of the LCD panel. By using this instruction, it is possible to realize the
window moving without the change of display data.
st
The 1 Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
0
0
1
x
x
nd
Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
x
C6
C5
C4
C3
C2
C1
C0
C6
C5
C4
C3
C2
C1
C0
Initial COM0
0
0
0
0
0
0
0
COM0
0
0
0
0
0
0
1
COM1
0
0
0
0
0
1
0
COM2
0
0
0
0
0
1
1
COM3
:
:
:
:
:
:
:
:
1
1
1
1
1
0
0
COM124
1
1
1
1
1
0
1
COM125
1
1
1
1
1
1
0
COM126
1
1
1
1
1
1
1
COM127
The 2
Fig. 22 Sequence for Setting COM0
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9.1.10 Set Display Duty
This 2-byte instruction sets the display duty within the range of 1/(16+1) to 1/(128+1) to realize partial display.
st
The 1 Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
0
1
0
x
x
nd
Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
L7
L6
L5
L4
L3
L2
L1
L0
The 2
L7
L6
L5
L4
L3
L2
L1
L0
0
0
0
0
0
0
0
0
Selected Partial Duty Ratio
:
:
:
:
:
:
:
:
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
0
1/(16+1)
0
0
0
1
0
0
0
1
1/(17+1)
:
:
:
:
:
:
:
:
:
0
1
1
0
0
1
0
0
1/(100+1)
No Operation
:
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
1
1/(127+1)
1
0
0
0
0
0
0
0
1/(128+1)
1
0
0
0
0
0
0
1
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
No Operation
NOTE: The duty includes the duty for ICON.
Fig. 23
Ver 1.5a
Sequence for Setting Display Duty
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9.1.11 Set N-line Inversion (recommended 12-line inversion for full duty, 1/129 duty)
This 2-byte instruction sets the inverted line number within range of 3 to 33 to improve the display quality by controlling the
phase of the internal Frame signal. The DC bias maybe occurred if the N-line is not set well. Be sure to confirm this factor
after choosing a value of N.
st
The 1 Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
0
1
1
x
x
The 2
nd
Instruction
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
x
x
x
N4
N3
N2
N1
N0
N4
N3
N2
N1
N0
Selected n-line inversion
0
0
0
0
0
0-line inversion (frame inversion)
0
0
0
0
1
3-line inversion
0
0
0
1
0
4-line inversion
0
0
0
1
1
5-line inversion
:
:
:
:
:
:
0
1
0
1
0
12-line inversion
(Recommend)
:
1
1
1
0
1
31-line inversion
1
1
1
1
0
32-line inversion
1
1
1
1
1
33-line inversion
Fig. 24 Sequence for N-line Inversion
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9.1.12 Release N-line Inversion
This instruction makes the inversion mode back to the frame inversion from the N-line inversion.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
1
0
0
9.1.13 Reverse Display
This instruction reverses the display status on LCD panel without rewriting new contents into DDRAM.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
1
1
REV
Pixel Data in DDRAM
REV
“00” (White)
“01” (Light Gray)
“10” (Dark Gray)
“11” (Black)
0 (normal)
White
Light Gray
Dark Gray
Black
1 (reverse)
Black
Dark gray
Light gray
White
9.1.14 Entire Display ON
This instruction forces the whole LCD pixels to be turned ON, regardless of the contents in DDRAM. The contents in
DDRAM are not changed. This instruction has priority over the Reverse Display instruction.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
1
0
EON
EON
Pixel Data in DDRAM
“00” (White)
“01” (Light Gray)
“10” (Dark Gray)
“11” (Black)
0 (normal)
White
Light Gray
Dark Gray
Black
1 (entire ON)
Black
Black
Black
Black
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9.1.15 Power Control
This instruction selects one of eight power circuit functions by using 3-bit register. An external power supply and part of
internal power supply functions can be used simultaneously.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
1
VC
VR
VF
VC
VR
VF
Internal Power Supply Circuits
0
Status
OFF
Internal voltage converter circuit
1
0
ON
OFF
Internal voltage regulator circuit
1
0
ON
OFF
Internal voltage follower circuit
1
ON
9.1.16 Select Regulator Resister
This instruction selects resistance ratio of the internal regulator resistors. Refer to the voltage regulator circuits in power
supply circuit section.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
0
R2
R1
R0
Ver 1.5a
R2
R1
R0
1+ (Rb / Ra)
0
0
0
2.3
0
0
1
3.0
0
1
0
3.7
0
1
1
4.4
1
0
0
5.1
1
0
1
5.8
1
1
0
6.5
1
1
1
7.2
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9.1.17 Set Electronic Volume Register
st
nd
This is 2-byte Instruction. The 1 instruction enters Reference Voltage mode, and the 2
reference voltage register. After 2
nd
one updates the contents of the
instruction, Reference Voltage mode is released.
st
The 1 Instruction: Set Reference Voltage Select Mode
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
0
0
0
0
0
1
The 2
nd
Instruction: Set Reference Voltage Register
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
x
x
EV5
EV4
EV3
EV2
EV1
EV0
EV5
EV4
EV3
EV2
EV1
EV0
EV Value
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
0
62
1
1
1
1
1
1
63
9.1.18 Select LCD Bias
This instruction selects LCD bias ratio for the internal voltage follower to drive the LCD.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
1
0
B2
B1
B0
Ver 1.5a
B2
B1
B0
LCD bias
0
0
0
1/5
0
0
1
1/6
0
1
0
1/7
0
1
1
1/8
1
0
0
1/9
1
0
1
1/10
1
1
0
1/11
1
1
1
1/12
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9.1.19 Set COM Scan Direction
This instruction selects the COM output scanning direction and determines the LCD driver output status.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
0
0
SHL
x
x
x
SHL = 0: normal direction (COM0 ~ COM127)
SHL = 1: reverse direction (COM127 ~ COM0)
9.1.20 Set SEG Scan Direction
This instruction changes the relationship between the DDRAM column address and the segment driver. The SEG scan
direction can be reversed by this instruction. This feature makes IC layout more flexible for LCD module assembly.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
0
0
ADC
ADC = 0: normal direction (SEG0 ~ SEG127)
ADC = 1: reverse direction (SEG127 ~ SEG0)
9.1.21 Oscillator ON Start
This instruction enables the built-in oscillator circuit.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
1
0
1
1
9.1.22 & 9.1.23 Power Save
ST7571 enters Power-Save mode and reduces the power consumption to the static power consumption. It returns to the
normal operation mode by the Release Power Save Mode instruction.
Set Power Save Mode
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
1
0
0
P
P = 0: normal mode
P = 1: power-save mode (sleep mode)
Fig. 25 Internal Procedure of Power Save
Release Power Save Mode
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
0
1
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9.1.24 RESET
This is software reset. It resets internal registers. The software reset is different with a hardware reset. This instruction
cannot initialize the LCD power supply, which is initialized by a hardware reset (refer to section 7.5 RESET CIRCUITS).
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
1
0
9.1.25 Set Display Data Length (only for 8-bit 3-Line SPI Mode)
This 2-byte instruction is used in 3-Line SPI mode only. In 3-Line SPI mode, A0 is not used and “Set Display Data Length”
st
instruction is used to indicate the number of display data bytes which are going to be transmitted. The 1 byte sets the
mode, and the 2
nd
byte sets the data bytes, which will be written, into internal counter. The next byte after the display data
string is handled as instruction. The 3-Line SPI mode supports write-access only.
st
The 1 Instruction: Set Display Data Length Command (Only Write Mode)
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
x
x
1
1
1
0
1
0
0
0
The 2
nd
Instruction: Set Display Data Length Counter
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
x
x
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Display Data Length
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
1
0
3
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
0
1
254
1
1
1
1
1
1
1
0
255
1
1
1
1
1
1
1
1
256
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
1
1
9.1.26 NOP
No operation
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9.1.27 Extension Command Set1
This instruction enables the extension command set-1.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
1
1
1
0
1
9.1.28 Extension Command Set2
This instruction enables the extension command set-2.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
0
1
0
0
0
1
9.1.29 Extension Command Set3
This instruction enables the extension command set-3.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
1
1
1
0
1
1
Extension Command Set 1
After entering the extension mode-1, the extension command set-1 is enabled. These commands are valid only in this
mode. Always remember to return back to normal mode for correct operation.
Increase Vop Offset
This instruction increases the Vop offset (Vof[4:0]) by 1.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
1
0
0
0
1
Decrease Vop Offset
This instruction decreases the Vop offset (Vof[4:0]) by 1.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
1
0
0
1
0
Fine Tune Vop
The “Increase Vop Offset” and “Decrease Vop Offset” instructions fine tune the voltage of Vop. The relation is shown below:
Note:
1.
The range is limited. If continuously setting “Increase Vop Offset”, Vof[4:0] will increase. When Vof[4:0] is 0x0F and
followed by a “Increase Vop Offset” command, Vof[4:0] will become 0x10. As the result, Vop changes from +15 step
to -16 step. Software programmer should add a software protection to prevent that an operator maybe presses the
“Increase Button” too many times accidentally.
2.
EV”[5:0] = EV[5:0] + Vof[4:0] and EV”[5:0] ≤ 0x3F. If EV[5:0] + Vof[4:0] > 0x3F, EV”[5:0] will truncate the invalid bit.
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Return to Normal Mode
This instruction returns IC into normal mode and the general commands are available.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
Extension Command Set 2
After entering the extension mode-2, the extension command set-2 is enabled. These commands are valid only in this
mode. Always remember to return back to normal mode for correct operation.
Disable auto-Read
This instruction disables the EEPROM auto-read function and lets the related registers can be set manually.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
1
0
1
0
Enter EEPROM Mode
This instruction enters EEPROM mode.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
0
0
1
1
Enable Read Mode
This instruction enables the manually-read function.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
0
0
0
0
Set Read Pulse
This instruction generates one read cycle to read the contents in EEPROM.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
1
1
0
0
0
1
Exit EEPROM Mode
This instruction exits EEPROM mode.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
0
0
0
0
1
1
Enable ERASE Mode
This instruction enables manually-erase function.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
0
1
0
1
0
Set ERASE Pulse
This instruction generates one erase cycle to erase the contents in EEPROM.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
1
0
1
0
1
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Enable Write Mode
This instruction enables manually-write function.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
0
1
0
1
Set Write Pulse
This instruction generates one write cycle to write parameters into EEPROM.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
1
0
1
0
1
0
Return to Normal Mode
This instruction returns IC into normal mode and the general commands are available.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
Extension Command Set 3
After entering the extension mode-3, the extension command set-3 is enabled. These commands are valid only in this
mode. Always remember to return back to normal mode for correct operation.
Set Color Mode
This instruction controls the gray-scale mode.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
0
0
0
B/G
Flag
B/G
Description
B/G=0 : IC is in Gray-Scale mode (write 2-byte for 8-pixel).
B/G=1 : IC is in Black/White mode (write 1-byte for 8-pixel).
Return to Normal Mode
This instruction returns IC into normal mode and the general commands are available.
A0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
Ver 1.5a
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10. OPERATION FLOW
10.1 Power ON Sequence
Case 1: RST=L while Power ON (Recommended)
Case 2: RST=H while Power ON
Timing Requirement:
Item
Symbol
Requirement
Note
l
After VDDI is stable, a successful hardware reset by RST is
required.
RST input time
tON-RST
Recommend
l
RST=L can be input at any time after power is stable.
0 ≤ tON-RST ≤ 50 ms
l
tRW & tR should match the timing specification of RST.
l
The recommended time just prevents abnormal display
(customer can use Case 1 instead).
VDD2 power delay
tON-V2
0 ≤ tON-V2
l
Applying VDDI and VDDA in any order will not damage IC.
l
If VDDI and VDDA are separated, it is recommend to turn
ON VDDI first, followed by a success hardware reset, and
the VDDA is the last one.
Note:
1.
IC will NOT be damaged if either VDDI or VDDA is OFF while another is ON.
The specification listed below just wants to prevent abnormal display on LCD module.
2.
Power stable is defined as the time that the later power (VDDI or VDDA) reaches 90% of its rated voltage. The power
stable time depends on system and the time is not included in this specification (customer should consider this factor).
3.
It is recommended to keep the interface pins (A0, RWR, ERD, CSB and DB[7:0]), except RST, at “High” level before
the internal reset procedure is finished.
4.
Internal VD1 generator will generate VD1 when DCPS is set to “L”. The VD1 rising time is controlled by ITO resistance
and the external capacitor. Before VD1 is stable, internal logic state is unstable and large current maybe occurred. This
current will not damage IC. This period can be reduced by reduce the ITO resistance or the external capacitor value.
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10.2 Referential Operation Flow : Initializing with internal power system
Fig. 26 Initializing with the Built-in Power Supply Circuits
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ST7571
Referential Initial Code
The referential initial code is shown below. In order to be compatible with ST7541, some instructions are still included, such
as the instructions with gray background). These instructions will not operate in ST7571 (just like NOP).
void Initial_ST7571(void)
{
Reset( );
Delay (100);
// Delay 100ms for stable VDD1/VDD2/VDD3
Write(COMMAND, 0xAE);
// Display OFF
Write(COMMAND, 0x38);
// MODE SET
Write(COMMAND, 0xB8);
// FR=1011 => 85Hz
// BE[1:0]=1,0 => booster efficiency Level-3
Write(COMMAND, 0xA1);
// ADC select, ADC=1 =>reverse direction
Write(COMMAND, 0xC8);
// SHL select, SHL=1 => reverse direction
Write(COMMAND, 0x44);
// Set initial COM0 register
Write(COMMAND, 0x00);
//
Write(COMMAND, 0x40);
// Set initial display line register
Write(COMMAND, 0x00);
//
Write(COMMAND, 0xAB);
// OSC. ON
Write(COMMAND, 0x67);
// DC-DC step up, 8 times boosting circuit
Write(COMMAND, 0x25);
// Select regulator register(1+(Ra+Rb))
Write(COMMAND, 0x81);
// Set Reference Voltage
Write(COMMAND, 0x23);
// EV=35
Write(COMMAND, 0x54);
// Set LCD Bias=1/9 V0
Write(COMMAND, 0xF3);
// Release Bias Power Save Mode
Write(COMMAND, 0x04);
//
Write(COMMAND, 0x93);
// Set FRC and PWM mode (4FRC & 15PWM)
Write(COMMAND, 0x2C);
// Power Control, VC: ON
Delay (200);
// Delay 200ms
Write(COMMAND, 0x2E);
// Power Control, VC: ON
Delay (200);
// Delay 200ms
Write(COMMAND, 0x2F);
// Power Control, VC: ON
Delay (10);
// Delay 10ms
Write(COMMAND, 0xAF);
// Display ON
=> Vop =10.556V
VR: OFF
VR: ON
VR: ON
VF: OFF
VF: OFF
VF: ON
}
Note:
The initial code is for reference only. An optimized initial code should be checked on customer’s system and LCD module.
Ver 1.5a
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10.3 Referential Operation Flow : Displaying Data
Fig. 27 Data Displaying Flow
10.4 Referential Operation Flow : Set Color Mode (Black/White Mode)
Gray Mode (default)
Enter Test Command Set 3
Write( COMMAND, 0x7B );
Set Color Mode
Write( COMMAND, 0x11 );
Exit Test Command Set 3
Write( COMMAND, 0x00 );
Black/White Mode
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10.5 Referential Operation Flow : Power-OFF
By setting 0xA9, ST7571 will go into power save mode. The LCD driving outputs are fixed to VSS, built-in power circuits are
turned OFF and a discharge process starts.
Instruction Flow
After the built-in power circuits are turned OFF and
completely discharged, the power (VDD1 and VDD2)
can be removed.
Fig. 28 Power off instruction flow
Note:
1.
tPOFF: Internal Power discharge time. => 250ms (max).
2.
tV2OFF: Period between VDD1 and VDD2 OFF time. => 0 ms (min).
3.
It is NOT recommended to turn VDD1 OFF before VDD2. Without VDD1, the internal status cannot be guaranteed
and internal discharge-process maybe stopped. The un-discharged power maybe flows into COM/SEG output(s) and
the liquid crystal in panel maybe polarized.
4.
IC will NOT be damaged if either VDD1 or VDD2 is OFF while another is ON.
5.
The timing is dependent on panel loading and the external capacitor(s).
6.
The timing in these figures is base on the condition that: LCD Panel Size = 1.8” and C=1uF.
7.
When turning VDD2 OFF, the falling time should follow the specification:
300ms ≤ tPFall ≤ 1sec
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10.6 Referential Operation Flow : Burning EEPROM
HW Reset
Delay 120ms
( Software Coding Flow)
Initial Sequence
Key
Show Image
0x51
+
0x52
-
Disable Autoread
Read EE
Set EE Register
(for the best display quality)
Adjust Vop Offset
VE connect to VDD
VPP connect to 18V
( Software Coding Flow)
Erase EE
Write EE
Remove 18V from VPP
Remove VDD from VE
HW Reset
Delay 120ms
Check Module
Performance
Fig. 19 EE Burning flow chart
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Referential Software Functions
void Disable_autoread(void)
{
Write(COMMAND, 0xD1);
//Enter test command set 2
Write(COMMAND, 0xAA);
//Disable auto-read
Write(COMMAND, 0x00);
//Enter normal mode
}
void Read_EE (void)
{
Write(COMMAND, 0xD1);
//Enter test command set 2
Write(COMMAND, 0xAA);
//Auto-read disable
Write(COMMAND, 0x13);
//Enter EEPROM mode
Write(COMMAND, 0x20);
//Enable read mode
Delay(200);
//Delay 200ms
Write(COMMAND, 0x71);
//Set read pulse
Delay(200);
//Delay 200ms
Write(COMMAND, 0x83);
//Exit EEPROM mode
Write(COMMAND, 0x00);
//Enter normal mode
}
void Set_EE _Register (void)
{
// Adjust Vop offset here
// Command 0x51 and 0x52 can be set 16 times for adjusting a suitable Vop
// Maxmum adjusting ranges are +/-16 levels.
Write(COMMAND, 0xFD);
//Enter test command set 1
Write(COMMAND, 0x8C);
//Set Vop offset highest bit Vop_j[4]=0
Write(COMMAND, 0x90);
//Set Vop offset
Write(COMMAND, 0x51);
//0x51 for increase Vop offset by 1 level
Vop_j[3:0]=0
or
Write(COMMAND, 0x52);
//0x52 for decrease Vop offset by 1 level
Write(COMMAND, 0x00);
//Enter normal mode
}
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void Erase_EE (void)
{
Write(COMMAND, 0xD1);
//Enter test command set 2
Write(COMMAND, 0x13);
//Enter EEPROM mode
Write(COMMAND, 0x4A);
//Enable erase mode
Delay(200);
//Delay 200ms
Write(COMMAND, 0x55);
//Set erase pulse
Delay(200);
//Delay 200ms
Write(COMMAND, 0x83);
//Exit EEPROM mode
Write(COMMAND, 0x00);
//Enter normal mode
}
void Write_EE (void)
{
Write(COMMAND, 0xD1);
//Enter test command set 2
Write(COMMAND, 0x13);
//Enter EEPROM mode
Write(COMMAND, 0x35);
//Enable write mode
Delay(200);
//Delay 200ms
Write(COMMAND, 0x6A);
//Set write pulse
Delay(200);
//Delay 200ms
Write(COMMAND, 0x83);
//Exit EEPROM mode
Write(COMMAND, 0x00);
//Enter normal mode
}
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11. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2.
Parameter
Symbol
Conditions
Unit
Digital Power Supply Voltage
VDD1
–0.3 ~ 3.6
V
Analog Power supply voltage
VDD2
–0.3 ~ 3.6
V
Analog Power supply voltage
VDD3
–0.3 ~ 3.6
V
LCD Power supply voltage
V0-XV0
–0.3 ~ 15
V
LCD Power supply voltage
VG, VM
–0.3 ~ VDD2
V
VIN
–0.3 ~ VDD1+0.3
V
Operating temperature
TOPR
–30 to +85
°C
Storage temperature
TSTR
–40 to +125
°C
Input Voltage
V0
VDD
VDD
VG, VM
VSS
VSS
VSS
System (MPU) side
XV0
Chip side
Fig. 30
Notes
1.
Stresses above those listed under Limiting Values may cause permanent damage to the device.
2.
Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.
3.
Insure the voltage levels of V0, VDD2, VG, VM, VSS and XV0 always match the correct relation:
V0 ≥ VDD2 > VG > VM > VSS ≥ XV0
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12. DC CHARACTERISTICS
Item
Symbol
Rating
Condition
Min.
Typ.
Max.
Units
Applicable
Pin
Digital Operating Voltage
VDD1
1.7
—
3.4
V
VDD1
Analog Operating Voltage
VDD2
2.6
—
3.4
V
*2
Analog Operating Voltage
VDD3
2.6
—
3.4
V
*2
High-level Input Voltage
VIHC
0.7 x VDD1
—
VDD1
V
*1
Low-level Input Voltage
VILC
VSS
—
0.3 x VDD1
V
*1
Input leakage current
ILI
VIN = VDD1 or VSS
–1.0
—
1.0
μA
*3
Output leakage current
ILO
VIN = VDD1 or VSS
–3.0
—
3.0
μA
*4
—
0.7
Vop=12V
LCD Driver ON Resistance
RON
Ta =25°C
ΔV=1.2V
VG=2V
ΔV=0.2V
KΩ
—
0.7
70
77
SEGn
COMn *5
VDD1~3 = 2.8V,
Frame Frequency
fFR
1/129 duty, N-line=0,
Ta = 25°C
84
Hz
FR[3:0]=0000(77Hz)
1.
VSS1 = VSS2 = VSS3 = 0 V unless otherwise specified.
Bare Dice Current Consumption
Using Internal Power Circuits and applying external operating voltage (VDD1, VDD2 & VDD3).
Item
Symbol
Condition
Rating
Units
Notes
600
μA
*6
10
μA
*6
Min.
Typ.
Max.
—
450
—
5
VDD1=1.8V, VDD2=VDD3=2.8V
Display ON
Pattern: SNOW
ISS
Ta = 25°C, Vop=10.5V, 8X booster,
1/9 Bias, N-Line=0x01, 1/129 duty,
FR[3:0]=0000(77Hz)
Power Save
ISS
VDD1=1.8V, VDD2=VDD3=2.8V ,
Ta = 25°C
Note:
1.
The A0, D0 to D5, D6 (SI), D7 (SCL), /RD (E), /WR (R/W), CSB, IMS, OSC, P/S, /DOF, RESB, and MODE terminals.
2.
Used by internal analog circuits.
3.
The A0, /RD (E), /WR, /(R/W), CSB, IMS, OSC, P/S, /DOF, RESB and MODE terminals.
4.
Applies when the D0 to D5, D6 (SI), D7 (SCL) terminals are in a high impedance state.
5.
These are the resistance values for when a specified voltage difference is applied between the output terminals
(SEGn/COMn) and the various power supply terminals (V0, XV0, VG & VM).
RON = ΔV / ΔI
6.
(ΔV is the specified voltage difference; ΔI is the current when applying ΔV between output and power)
It indicates the current consumed by Bare Chip alone.
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Internal Power Circuits
The operation ranges of the internal power circuits are shown below:
Item
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
V0-XV0
—
—
15
V
Voltage follower output voltage
VM
0.7
VG/2
VDD2-0.7
V
VG output voltage range
VG
1.8
—
VDD2
V
Vop
Applicable
Pin
Internal Power Application Notes
l
Positive Booster: (VDD2 x 8 x BE) ≥ V0 or (VDD2 x 8 x BE) ≥ Vop;
l
Negative Booster: [–VDD2 x (8 – 1) x BE] ≤ XV0 or [VDD2 x (8 – 1) x BE] ≥ (Vop – VG),
l
Vop requirement: [VDD2 x (8 – 1) x BE] ≥ [Vop x (N – 2) / N] or [Vop ≤ VDD2 x (8 – 1) x BE x N / (N – 2)].
l
“8” is the booster stage and BE is the booster efficiency. Actual BE should be determined by module loading and ITO
where VG = Vop x 2 / N;
resistance value.
l
1.8V ≤ VG < VDD2. Recommend VG setting is: (VDD2-VG) = 0.5~0.8V.
l
VM=VG/2 and 0.7V ≤ VM < VDD2.
l
The worse condition should be considered. Furthermore, it should reserve some range for the temperature
compensation and the contrast control (for end-customer).
Internal Power Application Summary (Recommend LCD Module Setting)
For quick reference, the following table lists some recommended settings for LCD module.
VDD1=1.8V, VDD2=2.8V, N-Line=12 (0x0A), Panel Size=1.5”
Duty
Vop
Bias
1/129
10V ~ 12V
1/9
1/81
9V ~ 11V
1/9
1/65
8.5V ~ 10.5V
1/9
Note:
1.
It is recommended to reserve some range for user adjustment and temperature effect.
2.
The value listed above is in the IC point of view. The liquid crystal display status should be checked by customer.
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13. TIMING CHARACTERISTICS
System Bus Write Characteristics
8080 Series MPU
Fig. 31
(VDD1 = 1.8V~3.3V, Ta =-30~85°C )
Item
Address hold time
Address setup time
Signal
A0
System cycle time
Write L pulse width
/WR
Write H pulse width
WRITE Data setup time
WRITE Data hold time
l
DB[7:0]
Symbol
Condition
Rating
Min.
Max.
tAH8
0
—
tAW8
0
—
tCYC8
500
—
tCCLW
250
—
tCCHW
250
—
tDS8
80
—
tDH8
30
—
Units
ns
The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr + tf) ≤ (tCYC8 – tCCLW – tCCHW) is specified.
l
All timing is specified using 20% and 80% of VDD1 as the reference.
l
tCCLW is specified as the overlap between CSB being “L” and /WR being at the “L” level.
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6800 Series MPU
Fig. 32
(VDD1 = 1.8V~3.3V, Ta =-30~85°C )
Item
Address hold time
Address setup time
Signal
A0
System cycle time
Enable L pulse width (Write)
E
Enable H pulse width (Write)
WRITE Data setup time
WRITE Data hold time
DB[7:0]
Symbol
Condition
Rating
Min.
Max.
tAH6
0
—
tAW6
0
—
tCYC6
500
—
tEWLW
250
—
tEWHW
250
—
tDS6
80
—
tDH6
30
—
Units
ns
l
The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
l
All timing is specified using 20% and 80% of VDD1 as the reference.
l
tEWLW is specified as the overlap between CSB being “H” and E being “L”.
l
R/W signal is always “H”.
(tr + tf) ≤ (tCYC6 – tEWLW – tEWHW) is specified.
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Serial 4-Line Interface
First bit
Last bit
Fig. 33
(VDD1 = 1.8V~3.3V, Ta =-30~85°C )
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
Symbol
Condition
Rating
Min.
Max.
tSCYC
200
—
tSHW
80
—
SCL “L” pulse width
tSLW
80
—
Address setup time
tSAS
60
—
tSAH
30
—
tSDS
60
—
tSDH
30
—
tCSS
40
—
tCSH
100
—
Address hold time
Data setup time
Data hold time
CS-SCL time
CS-SCL time
A0
SID
CSB
l
The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
l
All timing is specified using 20% and 80% of VDD1 as the standard.
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Units
ns
2009/7/21
ST7571
Serial 3-Line Interface
Fig. 34
(VDD1 = 1.8V~3.3V, Ta =-30~85°C )
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
Data hold time
CS-SCL time
CS-SCL time
SID
CSB
Symbol
Condition
Min.
Max.
tSCYC
200
—
tSHW
80
—
tSLW
80
—
tSDS
60
—
tSDH
30
—
tCSS
40
—
tCSH
100
—
l
The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
l
All timing is specified using 20% and 80% of VDD1 as the standard.
Ver 1.5a
Rating
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Units
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ST7571
2
Serial I C Interface
Fig. 35
(VDD1 = 3.3V, Ta =-30~85°C )
Item
Signal
Symbol
SCL clock frequency
SCL
SCL clock low period
Condition
Rating
Units
Min.
Max.
FSCLK
-
400
kHZ
SCL
TLOW
1.3
-
us
SCL clock high period
SCL
THIGH
0.6
-
us
Data set-up time
SDA
TSU;Data
100
-
ns
Data hold time
SDA
THD;Data
0
0.9
us
SCL,SDA rise time
SCL
TR
20+0.1Cb
300
ns
SCL,SDA fall time
SCL
Capacitive load represented by each bus line
TF
20+0.1Cb
300
ns
Cb
-
400
pF
Setup time for a repeated START condition
SDA
TSU;SUA
0.6
-
us
Start condition hold time
SDA
THD;STA
0.6
-
us
TSU;STO
0.6
-
us
TSW
-
50
ns
TBUF
1.3
Setup time for STOP condition
Tolerable spike width on bus
BUS free time between a STOP and START condition
SCL
us
Note:
l
All timing is specified using 20% and 80% of VDD1 as the standard.
l
It is recommended to operate the I C interface with VDD1 higher than 2.6V.
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2
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Reset Timing
tRW
RST
tR
Internal
Status
During Reset ...
Reset Finished
Fig. 36
(VDD1 = 1.8V~3.3V, Ta =-30~85°C )
Item
Signal
Reset time
Reset “L” pulse width
Ver 1.5a
RST
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
120
—
—
ms
tRW
2.0
—
—
us
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14. EXTERNAL COMPONENTS
The pinning of the ST7571 is optimized for single plane wiring e.g. for chip-on-glass display modules.
For VDD1 = 3.0V ~ 3.3V
For VDD1 = 1.8V ~ 2.8V
Fig. 37
External Components
Note:
1.
The resistors are reserved only. Please reserve the space for them on FPC (or system).
2.
The capacitors in these 2 cases are not same. C4 is not used if VDD1 is 1.8V ~ 2.8V.
Recommend Value: (for typical 1.6” LCD panel)
l
C1~C3: 1uF ~ 4.7uF
l
C4: 0.1uF ~ 1uF
Components selection notes:
l
Higher capacitor values are recommended for ripple reduction.
l
In order to avoid the characteristic differences of the LCD panel. The capacitor values should be verified according to
the display performance on LCD panel.
l
If the display panel is larger (> 2”), higher capacitor (C1~C3) values are recommended.
l
If the display panel is smaller (< 1”), lower capacitor (C1~C3) values can be used.
l
The resistor is reserved for discharge in the worse case, when VDD suddenly drops to 0.
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15. APPLICATION PROGRAM EXAMPLE
Programming example for displaying data with ST7571:
Step
Bus Status
A0
1
2
3.a
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
x’
0
A0
0
A0
0
A0
3.b
0
0
3.c
LCD Display
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
A0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
1
0
1
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
0
0
R2
R1
R0
Operation Description
Mode Set:
FR[3:0]=0000; BE[1:0]=10
OSC ON
Set Ra/Rb (R[2:0])
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
x’
x’
0
0
0
0
0
1
EV5 EV4 EV3 EV2 EV1 EV0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
Set contrast (EV[5:0])
0
1
0
B2
B1
B0
Set Bias (B[2:0])
Set Power Control
4.a
A0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
0
1
1
1
1
Booster=ON,
Regulator=ON,
Follower=ON
4.b
A0
0
A0
5
Ver 1.5a
1
1
1
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Display ON
Write Data
0
0
1
1
0
X, Y are default 0 after reset.
1
0
0
1
0
0
1
1
0
Skip setting X & Y here.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
Write Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
Write Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
Write Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
1
0
A0
10
0
1
A0
9
1
0
A0
8
0
0
A0
7
1
Display Control
1
A0
6
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
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ST7571
Step
Bus Status
A0
11
0
1
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
13
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
14
0
1
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
A0
15
Ver 1.5a
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
0
1
1
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
A0
16
Write Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
A0
Write Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
A0
Operation Description
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
A0
12
LCD Display
Write Data
Display Control:
Set Reverse display mode
(REV=1)
Set Column Address
Set address to “00000000”
X[7:0]=0x00
(X0 default is 0)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
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Write Data
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ST7571
2
Programming example for displaying data with ST7571 (for I C Interface):
Step
1
2
3
Bus Status
6.a
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
x’
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
0
1
0
1
1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
0
R2
R1
R0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
1
x’
x’
EV5
EV4
EV3
EV2
EV1
EV0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
0
B2
B1
B0
6.b
6.c
Operation Description
I C Interface Start
4
5
LCD Display
2
Slave address for write
Set Control Byte
Co=0; A0=0
Mode Set:
FR[3:0]=0000; BE[1:0]=10
OSC ON
Set Ra/Rb (R[2:0])
Set contrast (EV[5:0])
Set Bias (B[2:0])
Set Power Control
7.a
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
1
1
1
Booster=ON,
Regulator=ON,
Follower=ON
7.b
8
9
10
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
0
1
1
1
1
2
I C Interface Start
Display Control
Display ON
Re-start
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
0
0
0
0
0
Co=0; A0=1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write Data
0
0
1
0
0
1
1
0
X, Y are default 0 after reset.
0
0
1
0
0
1
1
0
Skip setting X & Y here.
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
11
12
13
14
Ver 1.5a
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Slave address for write
Set Control Byte
Write Data
Write Data
Write Data
2009/7/21
ST7571
Step
Bus Status
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
15
16
17
18
19
20
21
22
23
24
2
I C Interface Start
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
0
0
1
1
1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
0
0
0
0
0
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
27
28
2
Write Data
Write Data
Write Data
Write Data
Write Data
Slave address for write
Set Control Byte
Co=1; A0=0
Display Control:
Set Reverse display mode
(REV=1)
Set Control Byte
Co=1; A0=0
Set Column Address
Set address to “00000000”
X[7:0]=0x00
(X0 default is 0)
Set Control Byte
Co=1; A0=1
Write Data
2
I C Interface Stop
Ver 1.5a
Operation Description
Re-start
DB7
25
26
LCD Display
STOP I C transmission
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16. APPLICATION NOTES
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Ver 1.5a
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Ver 1.5a
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Ver 1.5a
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ST7571 Specification Revision History
Version
Date
1.0
2008/01/29
1.1
1.2
2008/04/02
2008/08/08
Description
1.
Official Release.
1.
Remove CSL=L setting.
2.
Modify Application note
3.
Add Initial code
4.
Modify ITO layout reference
5.
Modify 9.1.14 entire display
1.
Re-arrange sections for document format issue.
2.
Remove one of the Power OFF flow (not easy control by customer).
3.
Update recommend N-Line setting as 12-line (0x0A).
4.
Rewrite some description for easy understanding and grammar issue.
5.
Fix wrong Limiting Values.
6.
Rewrite DC Characteristics section. Separate Internal Power Application Note for
detailed description.
1.3
1.4
1.4a
1.4b
2008/12/19
2009/03/13
2009/03/16
2009/05/13
7.
Modify Recommend LCD Vop Setting: use same bias for easy use.
1.
Modify limiting voltage values.
2.
Modify 8080/6800 system cycle time.
1.
Remove reversion history before Ver. 1.0.
2.
Redraw broken figures.
3.
Rewrite Section 7.5 RESET CIRCUITS for easy understanding.
4.
Rewrite descriptions for easy understanding.
5.
Update Power ON Sequence information.
6.
Add 0x8C & 0x90 to “Set_EE_Register” at Software Function Program.
7.
Fix COM pad naming in figures.
8.
Update external components information.
9.
Match the instruction name with the instruction description.
1.
Modify drawing: RST waveform at 10.1 Power ON Sequence Section (Case 2).
2.
Fix typing mistakes.
1.
Redraw IC outline (Page 2) and use only one view direction for IC and PAD.
2.
Fix typing mistakes and rewrite descriptions for easy understanding.
3.
Add ITO limitation of I C interface signal SDA (Page 14).
4.
Fix naming issue on Page 17, 22, 35. Column Address should be X[7:0] (not Y[7:0]).
5.
The default value of FR[3:0] after reset is missing in previous version.
6.
Rearrange the operation flow information into one section:
2
“Section 10. OPERATION FLOW” (Page 48).
7.
Rename section “10. COMMAND DESCRIPTION” to be “10. OPERATION FLOW.”
8.
Add note of I C: “VDD1 higher than 2.6V”.
9.
Add notes to Section 14. EXTERNAL COMPONENTS. Modify the value to be a range.
2
10. Fix Section 15. APPLICATION PROGRAM EXAMPLE mistakes.
11. Update detailed settings into Section 16. APPLICATION NOTES:
Different circuit for different VDD1 level (C4 is not used if VDD1 is 1.8V or 2.8V).
Reserve 2 more resistors.
Ver 1.5a
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2009/7/21
ST7571
ST7571 Specification Revision History
1.5
1.5a
Ver 1.5a
2009/6/25
2009/7/21
1.
Fix typing mistakes.
2.
Add axis into Section 3. PAD ARRANGEMENT (COG).
3.
Modify referential codes: use 8-bit format, keep delay time same as description.
4.
Mark no operation instructions in initial code (Page 50).
5.
Add Test Instructions into instruction table.
6.
Reserve external components for special case.
7.
Define the VDD2 voltage range: 2.7V ~ 3.3V (cover 2.6V ~ 3.4V).
1.
Add description of Extension Command Sets.
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