ICS1726-11 PRELIMINARY INFORMATION Low EMI Clock Generator Description Features The ICS1726-11 generates a low EMI output clock from a clock or crystal input. The part is designed to dither the LCD interface clock for PDAs, printers, scanners, modems, copiers, and others. Using ICS’ proprietary mix of analog and digital Phase-Locked Loop (PLL) technology, the device spreads the frequency spectrum of the output, reducing the frequency amplitude peaks by several dB. The ICS1726-11 offers both centered and down spread from a high-speed clock input. • • • • Packaged in 8-pin SOIC/TSSOP • • • • Input frequency range of 16 to 32 MHz • • • • Low EMI feature can be disabled ICS offers many other clocks for computers and computer peripherals. Consult us when you need to remove crystals and oscillators from your board. Provides a spread spectrum output clock Supports flat panel controllers Accepts a clock or crystal input (provides same frequency dithered output) Output frequency range of 16 to 32 MHz Center and down spread Peak reduction by 8 dB to 16 dB typical on 3rd through 19th odd harmonics Includes power down Operating voltage of 3.3 V Advanced, low-power CMOS process Block Diagram VDD S1:0 2 PLL Clock Synthesis and Spread Spectrum Circuitry X1/CLK SSCLK X1 Clock Buffer/ Crystal Ocsillator X2 GND External caps required for with crystal for accurate tuning of the clock 1 MDS 1726-11 A Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 092905 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS1726-11 Low EMI Clock Generator Pin Assignment Spread Direction and Percentage Select Table X1/ICLK 1 8 X2 GND 2 7 VDD S1 3 6 NC S0 4 5 SSCLK 8 pin (150 mil) SOIC 8-pin (173 mil) TSSOP S1 Pin 3 S0 Pin 4 Spread Direction Spread Percentage 0 0 0 M M M 1 1 1 0 M 1 0 M 1 0 M 1 Center Center Center Center No Spread Down Down Down Down ±1.4 ±1.1 ±0.6 ±0.5 -1.6 -2.0 -0.7 -3.0 0 = connect to GND M = unconnected (floating) 1 = connect directly to VDD Pin Descriptions Pin Number Pin Name Pin Type 1 X1/ICLK Input Connect to a 16 to 32 MHz crystal or clock. 2 GND Power Connect to ground. 3 S1 Input Function select 1 input. Selects spread amount and direction per table above. (default-internal mid-level). 4 S0 Input Function select 0 input. Selects spread amount and direction per table above. (default-internal mid-level). 5 SSCLK Output 6 NC — 7 VDD Power 8 X2 XO Clock output with Spread spectrum. No connect. Do not connect this pin to anything. Connect to +3.3 V. Crystal connection to a 16 to 32 MHz crystal. Leave unconnected for clock. 2 MDS 1726-11 A Integrated Circuit Systems, Inc. Pin Description ● 525 Race Street, San Jose, CA 95126 Revision 092905 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS1726-11 Low EMI Clock Generator External Components 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS1726-11. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. The ICS1726-11 requires a minimum number of external components for proper operation. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between VDD and GND on pins 7 and 2, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Crystal Information The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 6) x 2 In the equation, CL is the crystal load capacitance. So, for a crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2] capacitors should be used. Tri-level Select Pin Operation Spread Spectrum Profile The S1, S0 select pins are tri-level, meaning they have three separate states to make the selections shown in the table on page 2. To select the M (mid) level, the connection to these pins must be eliminated by either floating them, or tri-stating the driver connected to the select pin. The ICS1726-11 low EMI clock generator uses an optimized frequency slew rate to facilitate down stream tracking by zero delay buffers and other PLL devices. The frequency modulation amplitude is constant despite variations of the input frequency. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Frequency Modulation Rate Time 2) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 3 MDS 1726-11 A Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 092905 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS1726-11 Low EMI Clock Generator Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS1726-11. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. Max. Units 0 +70 °C +3.0 3.6 V DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +70°C Parameter Symbol Operating Voltage VDD Supply Current IDD Conditions Min. Typ. Max. Units 3.0 3.3 3.6 V 23 30 mA 35 mA No load, at 3.3 V, Fin=24 MHz No load, at 3.3 V, Fin=32 MHz Input High Voltage VIH 0.85VDD VDD VDD V VIHM 0.4VDD 0.5VDD 0.6VDD V Input Low Voltage VIL 0.0 0.0 0.15VDD V Output High Voltage VOH CMOS, IOH = -4 mA 2.4 V Output High Voltage VOH IOH = -6 mA 2.0 V Output Low Voltage VOL IOL = -4 mA 0.4 V IOL = -10 mA 1.2 V Input middle Voltage Input Capacitance S0, S1, pins 4 6 pF CIN2 X1, X2 pins 6 9 pF 4 MDS 1726-11 A Integrated Circuit Systems, Inc. CIN1 ● 525 Race Street, San Jose, CA 95126 Revision 092905 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS1726-11 Low EMI Clock Generator AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Typ. Max. Units Input Clock Frequency 16 32 MHz Output Clock Frequency 16 32 MHz 60 % 50 55 % 200 450 ps Input Clock Duty Cycle Time above VDD/2 40 Output Clock Duty Cycle Time above 1.5 V 45 Cycle to cycle Jitter Fin=27 MHz, Fout=27 MHz Output Rise Time tR 0.4 to 2.4 V 2.4 3.2 4.0 ns Output Fall Time tF 2.4 to 0.4 V 2.4 3.2 4.0 ns EMI Peak Frequency Reduction 8 to 16 dB Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Min. Typ. Max. Units θJA Still air 150 °C/W θJA 1 m/s air flow 140 °C/W θJA 3 m/s air flow 120 °C/W 40 °C/W θJC 5 MDS 1726-11 A Integrated Circuit Systems, Inc. Conditions ● 525 Race Street, San Jose, CA 95126 Revision 092905 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS1726-11 Low EMI Clock Generator Package Outline and Package Dimensions (8-pin TSSOP) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 8 Symbol E1 A A1 A2 b C D E E1 e L α aaa E IN D E X AREA 1 2 D A 2 Min Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 2.90 3.10 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° 0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.114 0.122 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° 0.004 A A 1 c -C e S E A T IN G P LA N E b L aaa 6 MDS 1726-11 A Integrated Circuit Systems, Inc. C ● 525 Race Street, San Jose, CA 95126 Revision 092905 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS1726-11 Low EMI Clock Generator Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 8 Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D Inches* Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° *For reference only. Controlling dimensions in mm. A h x 45 A1 C -Ce SEATING PLANE B L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS1726G-11 ICS1726G-11T ICS1726G-11LF ICS1726G-11LFT ICS1726M-11 ICS1726M-11T ICS1726M-11LF ICS1726M-11LFT 26G11 26G11 26G11L 26G11L 1726M11 1726M11 1726M11L 1726M11L Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel 8-pin TSSOP 8-pin TSSOP 8-pin TSSOP 8-pin TSSOP 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 7 MDS 1726-11 A Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 092905 ● tel (408) 297-1201 ● www.icst.com