ICS94235 Integrated Circuit Systems, Inc. Recommended Application: Pin Configuration Output Features: • 1 - Differential pair open drain CPU clocks • 1 - Single-ended open drain CPU clock • 13 - SDRAM @ 3.3V • 7 - PCI @ 3.3V • 2 - AGP @ 3.3V • 1 - 48MHz, @3.3V • 1 - REF @ 3.3V, (selectable strength) through I2C Features: • Programmable ouput frequency • Programmable ouput rise/fall time • Programmable CPU, SDRAM, PCI and AGP skew • Real time system reset output • Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage • Watchdog timer technology to reset system if over-clocking causes malfunction • Uses external 14.318MHz crystal Skew Specifications: • CPUT - CPUC: <250ps • PCI - PCI: <500ps • CPU - SDRAM: <350ps • SDRAM - SDRAM: <250ps • AGP - AGP: <250ps • AGP - PCI: <750ps • CPU - PCI: <3ns Block Diagram SDATA SCLK 48MHz XTAL OSC PLL1 Spread Spectrum REF0 CPU DIVDER 2 SDRAM DIVDER Stop PCI DIVDER Stop AGP DIVDER Stop 13 6 FS (3:0) PD# PCI_STOP# MODE CPUCLKT (1:0) CPUCLKC0 SDRAM (12:0) Control Logic PCICLK (5:0) PCICLK_F Config. Reg. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CPUCLKT0 CPUCLKC0 CPUCLKT1 SDATA SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDD GND SDRAM6 SDRAM7 SDRAM8 SDRAM9 GND VDD SDRAM10(PCI_STOP#)* SDRAM11 SDRAM12 48-Pin 300mil SSOP & 240mil TSSOP package Functionality PLL2 X1 X2 RESET# *PD# GND X1 X2 AVDD **FS0/REF0 VDD **FS1/AGP0 AGP1 GND *FS2/PCICLK_F PCICLK0 PCICLK1 PCICLK2 GND VDD *MODE/PCICLK3 PCICLK4 PCICLK5 AVDD48 **FS3/48MHz GND SCLK 2 AGP (1:0) RESET# FS 3 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 FS 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Power Groups 94235 Rev A 01/17/02 Third party brands and names are the property of their respective owners. FS 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CP U S DRAM 66.66 66.66 66.66 100.00 100.00 66.66 100.00 100.00 100.00 133.33 120.00 120.00 133.33 100.00 133.33 133.33 90.00 90.00 100.90 100.90 100.00 66.66 100.00 100.00 100.00 133.33 126.00 126.00 133.33 100.00 133.33 133.33 PCI 33.33 33.33 33.33 33.33 33.33 30.00 33.33 33.33 30.00 33.63 33.33 33.33 33.33 31.50 33.33 33.33 AGP 66.66 66.66 66.66 66.66 66.66 60.00 66.66 66.66 60.00 67.27 66.66 66.66 66.66 63.00 66.66 66.66 ICS94235 Pin Descriptions PIN NUMBER PIN NAME TYPE 1 RESET# OUT 2 PD# 4 5 3, 11, 16, 23, 29, 34, 41, 48 8, 17, 28, 35, 40 6 X1 X2 IN OUT Crystal input,nominally 14.318M Hz. Crystal output, nominally 14.318M Hz. GND PWR Ground pins VDD AVDD PWR PWR Power supply pins, nominal 3.3V Analog power supply pin, nominal 3.3V FS0 REF0 2, 3 IN OUT Frequency select pin. 14.318 M Hz reference clock. 2, 3 IN OUT OUT OUT Frequency select pin. AGP outputs defined as 2X PCI. These may not be stopped. AGP outputs defined as 2X PCI. These may not be stopped. Free running PCICLK not stoped by PCI_STOP# 1, 3 IN 7 9 10 12 20, 19, 15, 14, 13 18 21 1 IN FS1 AGP0 AGP1 PCICLK_F FS2 PCICLK (5:4) (2:0) PCICLK3 1, 3 2, 3 Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Frequency select pin. OUT PCI clock outputs. OUT PCI clock output. IN M ODE AVDD48 DESCRIPTION Real time system reset signal for frequency value or watchdog timmer timeout. This signal is active low. Function select pin, 1=Desktop M ode, 0=M obile M ode. PWR Analog power supply pin, nominal 3.3V Frequency select pin. 48M Hz output clock 22 FS3 48M Hz IN OUT 24 SCLK IN 2 SDRAM 10 OUT Clock input of I C input, 5V tolerant input Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low SDRAM clock output. SDRAM (12:11, 9:0 ) OUT SDRAM clock outputs. SDATA I/O 45, 47 CPUCLKT (1:0) OUT 46 CPUCLKC0 OUT 27 25, 26, 30, 31, 32, 33, 36, 37, 38, 39, 42, 43 44 PCI_STOP# 1 IN Third party brands and names are the property of their respective owners. 2 Data pin for I C circuitry 5V tolerant "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. "Complementory" clocks of differential pair CPU outputs. This open drain output need an external 1.5V pull-up. ICS94235 General Description Mode Pin - Power Management Input Control MODE, Pin 18 (Latched Input) 0 1 Pin 27 PCI_STOP# (Input) SDRAM10 (Output) Third party brands and names are the property of their respective owners. ICS94235 General I2C serial interface information for the ICS94235 How to Write: How to Read: How to Read: How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) Controller (Host) Start Bit Address D3 (H ) ICS (Slave /Receive r) A CK Byte Count ACK Dummy Command Code ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK If 7H has been written to B8 ACK Byte 0 Dummy Byte Count Byte 1 Byte 0 Byte 2 Byte 1 Byte 3 Byte 2 Byte 4 Byte 3 Byte 5 Byte 4 Byte 6 Byte 5 Byte 6 ACK Byte 7 Byte 18 ACK Byte 19 ACK Byte 20 ACK Stop Bit Third party brands and names are the property of their respective owners. If 12H has been written to B8 ACK If 13H has been written to B8 ACK If 14H has been written to B8 ACK Stop Bit Byte18 Byte 19 Byte 20 ICS94235 Brief I2C registers description for ICS94235 Programmable System Frequency Generator Register Name Byte Description PWD Default 2 Functionality & Frequency Select Register 0 Output frequency, hardware / I C frequency select, spread spectrum & output enable control register. See individual byte description Active / inactive output control registers/latch inputs read back. See individual byte description Output Control Registers 1-6 Vendor ID & Revision ID Registers 7 Byte 11 bit[7:4] is ICS vendor id - 1001. Other bits in this register designate device revision ID of this part. See individual byte description Byte Count Read Back Register 8 Writing to this register will configure byte count and how many byte will be read back. Do not write 00H to this byte. 08 H Watchdog Timer Count Register 9 Writing to this register will configure the number of seconds for the watchdog timer to reset. 10 H Watchdog Control Registers 10 Bit [6:0] VCO Control Selection Bit 10 Bit [7] Watchdog enable, watchdog status and programmable ’safe’ frequency’ can be configured in this register. This bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. 000,0000 0 VCO Frequency Control Registers 11-12 These registers control the dividers ratio into the phase detector and thus control the VCO output frequency. Depended on hardware/byte 0 configuration Spread Spectrum Control Registers 13-14 These registers control the spread percentage amount. Depended on hardware/byte 0 configuration Group Skews Control Registers 15-16 Increment or decrement the group skew amount as compared to the initial skew. See individual byte description Output Rise/Fall Time Select Registers 17-20 These registers will control the output rise and fall time. See individual byte description Third party brands and names are the property of their respective owners. ICS94235 Serial Configuration Command Bitmap Bit Bit 2, Bit 7:4 Bit 3 Bit 1 Bit 0 Description FS3 FS2 FS1 FS0 CPUCLK SDRAM PCICLK Bit2 Bit7 Bit6 Bit5 Bit4 ( M Hz ) ( M Hz ) (MHz) 0 0 0 0 0 66.66 66.66 33.33 0 0 0 0 1 66.66 100.00 33.33 0 0 0 1 0 100.00 6 6 . 66 33.33 0 0 0 1 1 100.00 100.00 33.33 0 0 1 0 0 100.00 133.33 33.33 0 0 1 0 1 120.00 120.00 30.00 0 0 1 1 0 133.33 100.00 33.33 0 0 1 1 1 133.33 133.33 33.33 0 1 0 0 0 90.00 90.00 30.00 0 1 0 0 1 100.90 100.90 33.63 0 1 0 1 0 100.00 6 6 . 66 33.33 0 1 0 1 1 100.00 100.00 33.33 0 1 1 0 0 100.00 133.33 33.33 0 0 1 0 1 126.00 126.00 31.50 0 1 1 1 0 133.33 100.00 33.33 0 1 1 1 1 133.33 133.33 33.33 1 0 0 0 0 102.00 102.00 34.00 1 0 0 0 1 102.00 136.00 34.00 1 0 0 1 0 136.00 102.00 34.00 1 0 0 1 1 136.00 136.00 34.00 1 0 1 0 0 103.00 103.00 34.33 1 0 1 0 1 103.00 137.33 34.33 1 0 1 1 0 137.33 103.00 34.33 1 0 1 1 1 137.33 137.33 34.33 1 1 0 0 0 105.00 105.00 35.00 1 1 0 0 1 105.00 140.00 35.00 1 1 0 1 0 140.00 140.00 35.00 1 1 0 1 1 107.00 107.00 35.66 1 1 1 0 0 107.00 1 4 2 .6 6 35.66 1 1 1 0 1 133.90 133.90 33.40 1 1 1 1 0 110.00 110.00 36.66 1 1 1 1 1 146.66 146.66 36.66 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs Third party brands and names are the property of their respective owners. PWD AGP (MHz) 66.66 66.66 66.66 66.66 66.66 60.00 66.66 66.66 60.00 67.27 66.66 66.66 66.66 63.00 66.66 66.66 67.99 6 7 .9 9 6 7 .9 9 6 7 .9 9 68.66 68.66 68.66 68.66 6 9 .9 9 6 9 .9 9 6 9 .9 9 7 1 .3 3 71.33 66.95 7 3 .3 3 73.33 Spread Precentage +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 00000 Note1 0 0 0 ICS94235 BI T PI N# P WD BI T PIN # PW D Bi t 7 - X FS3# Bit 7 - X MODE# Bit 6 10 1 AGP1 Bit 6 20 1 PCICLK5 DE S CRI P T IO N DE S CR I P TI O N Bit 5 9 1 AGP0 Bi t 5 19 1 PCICLK4 Bit 4 22 1 48MHz Bit 4 18 1 PCICLK3 Bit 3 43 1 SDRAM0 Bi t 3 15 1 PCICLK2 14 1 PCICLK1 Bit 2 7 1 REF0 - 1X or 2X d ef a u l t = 1 = 1 X Bit 2 Bit 1 13 1 PCICLK0 Bi t 1 47, 46 1 CPUCLKT0, CPUCLKC0 Bit 0 12 1 PCICLK_F Bit 0 45 1 CPUCLKT1 BI T PI N # PW D Bit 7 - X D ESCRI PTI O N BIT PIN # PW D FS0# Bit 7 - 0 DE S CR I P TI ON Reserved Bit 6 - X FS1# Bi t 6 - 1 Reserved Bit 5 - X FS2# Bit 5 39 1 S DRAM2 Bit 4 31 1 SDRAM8 Bi t 4 38 1 S DRAM3 Bit 3 30 1 SDRAM9 Bit 3 37 1 S DRAM4 Bit 2 27 1 SDRAM10 Bi t 2 36 1 S DRAM5 Bit 1 26 1 SDRAM11 Bit 1 33 1 S DRAM6 Bit 0 25 1 SDRAM12 Bi t 0 32 1 S DRAM7 BI T B i t7 B it 6 B it5 B it 4 B it3 B it 2 B i t1 B it 0 PI N# - BI T P IN # P W D DE SCRI PTI ON Bit 7 - 1 Reserved Bit 6 - 1 Reserved Bi t 5 - 1 Reserved Bit 4 - 1 Reserved Bi t 3 - 1 Reserved Bit 2 - 1 Reserved Bit 1 - 1 Reserved Bit 0 42 1 SDRAM1 Third party brands and names are the property of their respective owners. P WD 0 0 0 0 0 1 1 1 DE S C RI P T IO N Res er ved (Note) Res er ved (Note) Res er ved (Note) Res er ved (Note) Res er ved (Note) Res er ved (Note) Res er ved (Note) Res er ved (Note) ICS94235 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 0 0 1 X X X X X Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 0 0 0 1 0 0 0 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PW D X X X X X X X X Description Vendor ID Vendor ID Vendor ID Revision ID Revision ID Revision ID Revision ID Revision ID Description The decimal representation of these 8 bits correspond to how many 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 16X 290ms = 4.64 seconds. Description VCO Divider Bit0 REF Divider Bit6 REF Divider Bit5 REF Divider Bit4 REF Divider Bit3 REF Divider Bit2 REF Divider Bit1 REF Divider Bit0 Third party brands and names are the property of their respective owners. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 0 0 0 0 1 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 0 0 0 1 0 0 0 0 Description 0=Hw/B0 freq / 1=B11 & 12 freq WD Enable 0=disable / 1=enable WD Status 0=normal / 1=alarm WD Safe Frequency, Byte 0 bit 2 WD Safe Frequency, FS3 WD Safe Frequency, FS2 WD Safe Frequency, FS1 WD Safe Frequency, FS0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X X X X X Description VCO Divider Bit8 VCO Divider Bit7 VCO Divider Bit6 VCO Divider Bit5 VCO Divider Bit4 VCO Divider Bit3 VCO Divider Bit2 VCO Divider Bit1 ICS94235 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X X X X X Description Spread Spectrum Bit7 Spread Spectrum Bit6 Spread Spectrum Bit5 Spread Spectrum Bit4 Spread Spectrum Bit3 Spread Spectrum Bit2 Spread Spectrum Bit1 Spread Spectrum Bit0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X X X X X Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 0 0 0 0 0 0 0 0 Description Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD Description 0 1 PCICLK (5:0, F) Skew Control 0 0 0 1 AGP (1:0) Skew Control 0 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 1 0 1 0 1 0 1 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 1 0 1 0 1 0 1 0 CPUCLKT/C0 Skew Control CPUCLKT1 SDRAM0 Skew Control SDRAM (12:1) Skew Control Description CPUCLKT/C0 Slew Rate Control CPUCLKT1 Slew Rate Control PCICLK_F Slew Rate Control PCICLK (5:0) Slew Rate Control Third party brands and names are the property of their respective owners. Description Reserved Reserved Reserved Spread Spectrum Bit12 Spread Spectrum Bit11 Spread Spectrum Bit10 Spread Spectrum Bi 9 Spread Spectrum Bit8 Description SDRAM0 Skew Control SDRAM (12:1) Skew Control AGP (1:0) Slew Rate Control 48MHz Slew Rate Control ICS94235 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X X X X X Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved VCO Frequency ...................... 150MHz to 500MHz VCO Divider Range ................ 8 to 519 REF Divider Range ................. 2 to 129 Phase Detector Stability .......... 0.3536 to 1.4142 Third party brands and names are the property of their respective owners. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X X X X X Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ICS94235 Absolute Maximum Ratings Electrical Characteristics - Input/Supply/Common Ouput Parameters. TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors Operating IDD3.3OP66 CL = 0 pF; Select @ 66MHz IDD3.3OP100 CL = 0 pF; Select @ 66MHz IDD3.3OP133 CL = 0 pF; Select @ 133MHz Input Capacitance1 PD Fi TYP VSS-0.3 Supply Current Power Down Input frequency MIN 2 VDD = 3.3 V; CIN Logic Inputs CINX X1 & X2 pins Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target Freq. Skew1 tCPU-SDRAM tAGP-PCI VT = 50% tCPU-PCI 1Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. MAX VDD+0.3 UNITS V 0.8 V 5 uA -5 uA -200 uA 12 14.318 27 180 mA 600 16 uA MHz 5 pF 45 pF 3 ms 300 750 200 350 2.67 3 ps ns ICS94235 Electrical Characteristics - CPUCLK (Open Drain) TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated). PARAMETER SYMBOL CONDITIONS Output Impedance ZO Output High Voltage VOH2B Termination to Vpull-up(external) MIN TYP MAX VO = VX Output Low Voltage VOL2B Termination to Vpull-up(external) Output Low Current IOL2B VOL = 0.3V Rise Time1 tr2B VOL = 0.3V, VOH = 1.2 V Fall Time1 tf 2B VOH = 1.2 V, VOL = 0.3 V UNITS Ohms 1 1.2 0.4 18 V V mA 0.913 0.9 ns 0.9 ns Vpullup(external) Differential Voltage- AC1 VDIF Note 2 0.4 0.6 V Vpullup(external) Differential Voltage-DC1 VDIF Note 2 0.2 Differential Crossover Voltage1 VX Note 3 550 Duty Cycle1 dt2B VT = 50% Skew1 tsk2B VT = 50% Jitter, Cycle-to-cycle1 Jitter, Absolute1 tjcyc-cyc2B tjabs2B VT = VX VT = 50% 45 53 201 -250 Notes: 1 - Guaranteed by design, not 100% tested in production. - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the TRUE input level and VCP is the "complement" input level. 3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max = (Vpullup(external)/2)+150mV. 2 Third party brands and names are the property of their respective owners. 0.6 V 1100 mV 55 % 250 ps 250 ps 250 ps ICS94235 Electrical Characteristics - PCICLK TA = 0 - 70º C VDD = 3.3V +/-5%; C = 30pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -11 mA MIN 2.6 TYP MAX UNITS V Output Low Voltage VOL1 IOL = 9.4 mA 0.4 V Output High Current IOH1 VOH = 2.0 V -16 mA Output Low Current IOL1 VOL = 0.8 V Rise Time1 tr 1 VOL = 0.4 V, VOH = 2.4 V Fall Time1 tf1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle1 Skew1 dt1 Tsk1 VT = 1.5V VT = 1.5V 19 mA 1.63 45 2 ns 1.63 2 ns 51.9 55 % 170 500 ps MAX UNITS V 1Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCICLK_F TA = 0 - 70º C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise stated). PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -11 mA MIN 2.6 TYP Output Low Voltage VOL1 IOL = 9.4 mA 0.4 V Output High Current IOH1 VOH = 2.0 V -12 mA Output Low Current IOL1 VOL = 0.8 V Rise Time1 tr1 VOL = 0.4 V, VOH =2.4 V 1.63 2 ns Fall Time1 tf1 VOH = 2.4 V, VOL = 0.4 V 1.63 2 ns Duty Cycle1 Skew1(window) dt1 Tsk1 49.7 170 55 500 % ps 1Guaranteed VT = 50% VT = 50% by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 12 45 mA ICS94235 Electrical Characteristics - 48MHz, REF0 TA = 0 - 70º C; VDD = 3.3V +/-5%, VDDL = 2.5 V +/-5%; CL = 20pF (otherwise stated). PARAMETER SYMBOL CONDITIONS MIN TYP Output High Voltage VOH5 IOH = -16 mA 2.4 Output Low Voltage VOL5 IOL = 9 mA MAX UNITS V 0.4 V Output High Current IOH5 VOH = 2.0 V Output Low Current IOL5 VOL = 0.8 V -22 Rise Time1 tr 5 VOL = 0.4 V, VOH = 2.4 V 1.23 2 ns Fall Time1 tf 5 VOH = 2.4 V, VOL = 0.4 V 1.21 2 ns Duty Cycle1 dt5 VT = 1.5 V Jitter, One Sigma1 Jitter, Absolute1 tj1s5 tjabs5 VT = 1.5 V VT = 1.5 V 16 45 mA mA 53 55 % 595 0.5 ns 1 ns -1 1Guaranteed by design, not 100% tested in production. Electrical Characteristics - SDRAM (12:0) TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH3 IOH = -11 mA Output Low Voltage VOL3 IOL = 11 mA MIN 2 TYP MAX 0.4 UNITS V V -12 mA Output High Current IOH3 VOH = 2.0 V Output Low Current IOL3 VOL = 0.8 V Rise Time1 Tr3 VOL = 0.4 V, VOH = 2.4 V 0.88 2.2 ns Fall Time1 Tf3 VOH = 2.4 V, VOL = 0.4 V 0.8 2.2 ns Duty Cycle1 Dt3 VT = 50% 51.2 55 % Skew1(window) Tsk1 VT = 50% 205 250 ps 1Guarenteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 12 45 mA ICS94235 Shared Pin Operation Input/Output Pins Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 Third party brands and names are the property of their respective owners. ICS94235 PD# Timing Diagram Third party brands and names are the property of their respective owners. ICS94235 PCI_STOP# Timing Diagram Third party brands and names are the property of their respective owners. ICS94235 SYMBOL c L E1 E INDEX AREA 1 2 h x 45° In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A 2.413 2.794 .095 A1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c D 0.127 0.254 SEE VARIATIONS .005 .010 SEE VARIATIONS E 10.033 10.668 .395 .420 E1 7.391 7.595 .291 .299 e D h 0.381 L 0.508 1.016 SEE VARIATIONS N A 0.635 BASIC 0.635 0° .110 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 8° 0° 8° MIN MAX MIN MAX 15.748 16.002 .620 .630 JEDEC MO-118 DOC# 10-0034 6/1/00 REV B A1 -Cb SEATING PLANE VARIATIONS N 48 Ordering Information ICS94235yFT ICS XXXX y F - T Third party brands and names are the property of their respective owners. D mm. D (inch) ICS94235 SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A - 1.20 - .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 SEE VARIATIONS D 8.10 BASIC E E1 6.00 e L N aaa .0035 .008 SEE VARIATIONS 0.319 6.20 .236 0.50 BASIC 0.45 0.75 SEE VARIATIONS .244 0.020 BASIC .018 .30 SEE VARIATIONS 0° 8° 0° 8° - 0.10 - .004 MIN MAX MIN 12.40 12.60 .488 .496 MO-153 JEDEC Doc.# 10-0039 7/6/00 Rev B VARIATIONS N 48 Ordering Information ICS94235yGT ICS XXXX y G - T Third party brands and names are the property of their respective owners. D mm. D (inch) MAX