ICS ICS952301

ICS952301
Integrated
Circuit
Systems, Inc.
Advance Information
Frequency Timing Generator for Transmeta Systems
Recommended Application:
Transmeta
Output Features:
• 1CPU up to 66.6MHz &
overclocking of 66MHz.
• 7 PCI (3.3V) @ 33.3MHz (all are free running
selectable) w/ 2 selectable 1X/2X.
GNDREF
X1
X2
PD#
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK21
PCICLK3
PCICLK41
GNDPCI
VDDPCI
PCICLK5
1 REF (3.3V) at 14.318MHz.
1 48MHz (3.3V).
1 24_48MHz selectable output.
Features:
• Supports Spread Spectrum modulation for CPU and
PCI clocks, default -2.0% downspread.
• Efficient Power management scheme through stop
clocks and power down modes.
• Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
• 28-pin TSSOP package, 4.40mm (173mil).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
952301AG
•
•
•
Pin Configuration
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDREF
REF/ 1X or 2X Programmable*
CPU_STOP#
VDDCPU/CORE
GNDCPU/CORE
CPUCLK0
PCI_STOP#
SCLK
VDD48
GND48
48MHz
24-48MHz/Sel 48_24#*
SDATA
PCICLK6
28-Pin 173mil TSSOP
Note: ^ Internal Pulldown Resistor
* Internal Pullup Resistor
1 1X/2X Programmable
Skew Characteristics:
• PCI – PCI < 500ps
• CPU(early) – PCI = 1.5ns – 4ns.
Block Diagram
X1
X2
XTAL
OSC
REF
STOP
CPU
STOP
PCI(6:0)
CPU
PLL
PCI DIV
SCLOCK
SDATA
PD#
PCI_STOP#
Control
Logic
SEL48_24#
CPU_STOP#
48MHz
PLL
24/48
0673—07/09/02
STOP
48MHz
STOP
24/48MHz
Power Groups
VDD_Core, GND_Core = PLL core
VDDREF, GNDREF = REF, X1, X2
VDDPCI, GNDPCI = PCICLK (6:0)
VDD48, GND48 = 48MHz (1:0)
Pentium is a trademark on Intel Corporation.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS952301
Advance Information
Pin Descriptions
1
2
3
GNDREF
X1
X2
PIN
TYPE
PWR
IN
OUT
4
PD#
IN
5
6
7
8
9
10
11
12
13
14
15
16
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
I/O
I/O
Selectable 48 or 24MHz output
18
19
20
21
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK21
PCICLK3
PCICLK41
GNDPCI
VDDPCI
PCICLK5
PCICLK6
SDATA
24-48MHz/Sel
48_24#*
48MHz
GND48
VDD48
SCLK
Ground pin.
Crystal input, nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Asynchronous active low input pin used to power down the
device into a low power state. The internal clocks are
disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
PCI clock outputs.
PCI clock outputs.
Ground pin.
Supply for PCI, nominal 3.3V.
PCI clock outputs.
PCI clock outputs.
PCI clock outputs.
Ground pin.
Supply for PCI, nominal 3.3V.
PCI clock outputs.
PCI clock outputs.
Data pin for I2C circuitry 5V tolerant
OUT
PWR
PWR
IN
48MHz output clock
Ground pin.
Power for 24 & 48MHz output buffers and fixed PLL core.
22
PCI_STOP#
IN
23
24
25
CPUCLK0
GNDCPU/CORE
VDDCPU/CORE
OUT
PWR
PWR
26
CPU_STOP#
IN
PIN # PIN
17
27
28
REF/ 1X or 2X
Programmable*
VDDREF
OUT
PWR
DESCRIPTION
Clock pin of I2C circuitry 5V tolerant
Stops all PCICLKs besides the PCICLK_F clocks at logic 0
level, when input low
CPU clock outputs.
Ground pin.
3.3V power for the PLL core.
Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0
level, when input low
14.318 MHz reference clock. Latched input select for strength
of PCICLK(4,2). Default 1X with internal pullup.
3.3V power for the REF.
0673—07/09/02
2
ICS952301
Advance Information
ICS952301 Power Management Requirements
PD#
CPU
PCI
Byte 0
STOP#
STOP#
Bit 0
PCICLK
VCO
0
X
X
X
STOP
CPUCLK
0
LOW
1
1
1
0
1
1
1
0
1
0
0
1
RUN
RUN
RUN
STOP
RUN
Tri-State
PCICLK
Not Free Free-Run
Run
24
48
MHz
MHZ
REF
LOW
LOW
LOW
LOW
LOW
RUN
STOP
Tri-State
RUN
RUN
Tri-State
RUN
RUN
Tri-State
RUN
RUN
Tri-State
RUN
RUN
Tri-State
Note: If Byte 3 bit [7:2]=0 Not Free-Run, can be controlled by PCI_STOP#
If Byte 3 bit [7:2]=1 Free-Run, cannot controlled by PCI_STOP#
0673—07/09/02
3
ICS952301
Advance Information
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ICS (Slave/Receiver)
ACK
Byte Count
ACK
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Byte 6
Byte 6
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
0673—07/09/02
4
ICS952301
Advance Information
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit
2,7:4
Bit3
Bit1
Bit0
Bit2
Bit7
Bit6
Bit5
Bit4
CPU
FS4 FS3 FS2
FS1
FS0
0
0
0
0
0
60
0
0
0
0
1
60
0
0
0
1
0
60
0
0
0
1
1
60
0
0
1
0
0
66.6
0
0
1
0
1
66.6
0
0
1
1
0
66.6
0
0
1
1
1
66.6
0
1
0
0
0
67.32
0
1
0
0
1
68.64
0
1
0
1
0
69.96
0
1
0
1
1
72.6
0
1
1
0
0
61.5
0
1
1
0
1
63
0
1
1
1
0
64
0
1
1
1
1
65
1
0
0
0
0
60
1
0
0
0
1
66.6
1
0
0
1
0
50
1
0
0
1
1
48
1
0
1
0
0
58.8
1
0
1
0
1
57.6
1
0
1
1
0
56.4
1
0
1
1
1
54
1
1
0
0
0
60
1
1
0
0
1
60
1
1
0
1
0
60
1
1
0
1
1
60
1
1
1
0
0
66.6
1
1
1
0
1
66.6
1
1
1
1
0
66.6
1
1
1
1
1
66.6
Reserved
0-Normal 1-Spread spectrun Enabled
0-Running 1-Tristate all outputs
PCI
30
30
30
30
33.3
33.3
33.3
33.3
33.66
34.32
34.98
36.3
30.75
31.5
32
32.5
30
33.3
25
24
29.4
28.8
28.2
27
30
30
30
30
33.3
33.3
33.3
33.3
Note: PWD = Power-Up Default
0673—07/09/02
5
ICS952301
Advance Information
Name
Control Function
Bit 7
-
-
Frequency select by bit 7
RW
Bit 6
-
-
Frequency select by bit 6
RW
Bit 5
-
-
Frequency select by bit 5
RW
Frequency select by bit 4
RW
R
Bit 4
0
1
PWD
See Frequency table
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
Bit 3
-
-
Reserved
-
-
Bit 2
-
-
Frequency select by bit 2
RW
Bit 1
-
-
Spread Enable
RW
Normal
Enable
0
Bit 0
-
-
Output Control
RW
Running
Tri-state
0
See Frequency table
1
18
17
23
27
9
11
-
48MHz
24_48MHz
CPUCLK0
REF
PCICLK2
PCICLK4
-
Control Function
TYPE
2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Affected Pin
Pin #
Name
Output Disable
Output Disable
Output disable
Output disable
1X or 2X
1X or 2X
PCI HW SEL Status
(Reserved)
RW
RW
RW
RW
RW
RW
R
-
Bit Control
0
1
Disable
Disable
Disable
Disable
2X
2X
2X
-
Enable
Enable
Enable
Enable
1X
1X
1X
-
BYTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
1
1
1
1
1
1
1
X
BYTE
5
BYTE
6
B it
B it
B it
B it
B it
B it
B it
B it
7
6
5
4
3
2
1
0
Name
Control Function
-
-
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Affec ted Pin
Pin #
N am e
-
C ontrol Function
(R eserved)
(R eserved)
(R eserved)
(R eserved)
(R eserved)
(R eserved)
(R eserved)
(R eserved)
Bit Control
TYPE
4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
0
1
PWD
-
-
-
X
X
X
X
X
X
X
X
TYP
E
BYTE
Affected Pin
-
B it C ontrol
0
1
-
15
14
11
10
9
6
5
-
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
-
RW
RW
RW
RW
RW
RW
RW
-
Disable
Disable
Disable
Disable
Disable
Disable
Disable
-
1
PWD
Enable
Enable
Enable
Enable
Enable
Enable
Enable
-
1
1
1
1
1
1
1
X
Enable
Enable
Enable
Enable
Enable
Enable
Enable
-
PWD
1
1
1
1
1
1
1
0
1
3
BYTE
Output disable
Output disable
Output disable
Output disable
Output disable
Output disable
Output disable
(Reserved)
1
1
Bit Control
0
1
Control Function
TYPE
Pin #
Affected Pin
Pin #
Name
B it 7
B it 6
B it 5
B it 4
B it 3
B it 2
B it 1
B it 0
PWD
0
0
0
0
0
1
1
0
0673—07/09/02
6
Affected Pin
Bit Control
Pin #
Name
Control Function
TYPE
0
BYTE
Bit Control
0
15
14
11
10
9
6
5
-
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
-
Free Run Status
Free Run Status
Free Run Status
Free Run Status
Free Run Status
Free Run Status
Free Run Status
(Reserved)
RW
RW
RW
RW
RW
RW
RW
-
Disable
Disable
Disable
Disable
Disable
Disable
Disable
-
A ffec te d Pin
Pin #
N am e
-
-
C ontrol Function
TYPE
Affected Pin
TYPE
BYTE
(R e se rved )
(R e se rved )
(R e se rved )
(R e se rved )
(R e se rved )
(R e se rved )
(R e se rved )
(R e se rved )
-
B it C ontrol
0
1
-
-
PWD
X
X
X
X
X
X
X
X
ICS952301
Advance Information
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS952301. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse)
is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency
is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PCI_STOP# (High)
PD# (High)
CPUCLK
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may
exist. This signal is synchronized to the CPUCLKs inside the ICS9248-192.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS952301. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS952301 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952301 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS952301.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
0673—07/09/02
7
ICS952301
Advance Information
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal is synchronized internally by the ICS952301 prior to its control
action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down
state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal
oscillator. The power on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK
cycles. PCI_STOP# and CPU_STOP# are don’t care signals during the power down operations.
CPUCLK
(Internal)
PCICLK
(Internal)
PD#
CPUCLK
PCICLK_F, PCICLK
REF
INTERNAL
VCOs
INTERNAL
CRYSTAL OSC.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952301 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
0673—07/09/02
8
ICS952301
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parame
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
Input High Voltage
VIH
VIL
Input Low Voltage
Input High Current
IIH
Input Low Current
IIL1
Input Low Current
IIL2
Operating Supply
IDD(op)
Current
Power Down
IDDPD
Supply Current
Input frequency
Fi
Input Capacitance1
CIN
Transition Time
Clk Stabilization 1
CINX
Ttrans
TSTAB
Skew1
TCPU-PCI
1
1
CONDITIONS
MIN
2
VSS-0.3
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors -5
VIN = 0 V; Inputs with pull-up resistors
-200
C L = 0 pF; Select @ 66MHz
C L = 0 pF; With input address to Vdd or
GND
VDD = 3.3 V;
11
TYP
MAX UNITS
VDD+0.3
V
0.8
V
0.1
5
µA
2.0
µA
-100
µA
11
180
mA
0
600
µA
14.32
16
MHz
5
pF
Logic Inputs
X1 & X2 pins
To 1st crossing of target Freq.
From VDD = 3.3 V to 1% target Freq.
27
36
45
3
3
pF
ms
ms
VT = 1.5 V
1.5
2
4
ns
Guaranteed by design, not 100% tested in production.
0673—07/09/02
9
ICS952301
Advance Information
Electrical Characteristics - CPUCLK
Output Type:
TA = 0 - 70C; VDD = 3.3 V +/-5% CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedence
SYMBOL
Rdsp
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
VOH2B
VOL2B
IOH2B
IOL2B
MIN
12
TYP
32
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
1.8
tr2B
1
Fall Time
tf2B
1
Duty Cycle
d t2B1
Rise Time
Skew
tsk2B
1
t jcyc-cyc2B
tjabs2B1
Jitter
1
CONDITIONS
VO = Vdd * 0.5
MAX
60
UNITS
Ohm
0.4
-27
27
2.1
0.15
-32
49
V
V
mA
mA
VOL = 0.4 V, VOH = 2.4 V
0.4
1.4
2
ns
VOH = 2.4 V, VOL = 0.4 V
0.4
1.6
2
ns
VT = 1.5 V
44
48
55
%
VT = 1.5 V
18
175
ps
VT = 1.5 V
VT = 1.5 V
122
250
ps
198
+250
ps
-250
Electrical Characteristics - REF
Output Type:
TA = 0 - 70C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedence
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
Jitter
1
SYMBOL
Rdsp
VOH5
VOL5
IOH5
IOL5
1
CONDITIONS
VO = Vdd * 0.5
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
12
2.6
16
TYP
32
2.9
0.3
-29
51
1
MAX UNITS
60
Ohm
V
0.4
V
-22
mA
mA
t r5
VOL = 0.4 V, VOH = 2.4 V
1.9
4
ns
t f5
VOH = 2.4 V, VOL = 0.4 V
1.9
4
ns
d t5
VT = 1.5 V
VT = 1.5 V
52
559
55
1000
%
ps
t jcyc-cyc5
45
0673—07/09/02
10
ICS952301
Advance Information
Electrical Characteristics - 48MHz & 48/24MHz
Output Type:
1
TA = 0 - 70C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedence
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
SYMBOL
Rdsp
VOH5
VOL5
IOH5
IOL5
1
1
Duty Cycle
1
MIN
20
2.6
16
TYP
30
2.9
0.3
-29
51
MAX UNITS
65
Ohm
V
0.4
V
-22
mA
mA
tr5
VOL = 0.4 V, VOH = 2.4 V
0.7
1.2
ns
tf5
VOH = 2.4 V, VOL = 0.4 V
0.7
1.2
ns
d t5
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
52
164
221
55
500
800
%
ps
ps
tjcyc-cyc5
t jabs5
1
Jitter
CONDITIONS
VO = Vdd * 0.5
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
45
Electrical Characteristics - PCICLK
Output Type: 5
PCICLK(6:0)
TA = 0 - 70C; VDD = 3.3 V,+/-5%; CL = 30 pF
PARAMETER
Output Impedence
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
1
SYMBOL
CONDITIONS
Rdsp VO = Vdd * 0.5
VOH1
VOL1
IOH1
IOL1
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
12
TYP
32
2.1
2.8
0.15
-75
44
0.4
-22
57
V
V
mA
mA
16
MAX UNITS
60
Ohm
t r1
VOL = 0.4 V, VOH = 2.4 V
1.6
2
ns
tf1
VOH = 2.4 V, VOL = 0.4 V
1.8
2
ns
d t1
VT = 1.5 V
50
55
%
Skew
t sk1
VT = 1.5 V
16
500
ps
Jitter
t jcyc-cyc1
VT = 1.5 V
VT = 1.5 V
100
210
500
500
ps
ps
Fall Time
1
Duty Cycle
1
1
t jabs1
0673—07/09/02
11
45
ICS952301
Advance Information
c
N
SYMBOL
L
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
E1
INDEX
AREA
E
1 2
α
D
-
1.20
-
.047
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.19
0.30
.007
.012
c
0.09
0.20
SEE VARIATIONS
6.40 BASIC
E
4.30
e
L
N
A1
-Ce
SEATING
PLANE
b
MAX
A
D
A
MIN
A1
E1
A2
MAX
.0035
.008
SEE VARIATIONS
0.252 BASIC
4.50
0.65 BASIC
0.45
0.75
SEE VARIATIONS
.169
.177
0.0256 BASIC
.018
.030
SEE VARIATIONS
α
0°
8°
0°
8°
aaa
-
0.10
-
.004
MIN
MAX
MIN
9.60
9.80
VARIATIONS
aaa C
N
4.40 mm. Body, 0.65 mm. pitch TSSOP
(0.0256 Inch)
(173 mil)
28
D mm.
D (inch)
.378
.386
MO-153 JEDEC
Doc.# 10-0035
7/6/00 Rev C
Ordering Information
ICS952301yGT
Example:
ICS 95XXXX y G - T
Designation for tape and reel packaging
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0673—07/09/02
12
MAX