ICSSSTUB32871A Integrated Circuit Systems, Inc. 27-Bit Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A • Optimized for DDR2 400/533/667 JEDEC 4 Rank VLP DIMMS Pin Configuration 1 2 3 4 5 A B C D E Product Features: • 27-bit 1:1 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on RESET input • 50% more dynamic driver strength than standard SSTU32864 • Low voltage operation VDD = 1.7V to 1.9V • Available in 96 BGA package F G H J K L M N P R T 96 Ball BGA (Top View) Functionality Truth Table In puts RESET DCS0 DCS1 CSGate Enable Outputs CK CK Dn, DODTn, DCK En Qn QCS QODT, QCKE H L L X ↑ ↓ L L L L H L L X ↑ ↓ H H L H H L L X L or H L or H X Q0 Q0 Q0 ↑ ↓ L L L L H L H X H L H X ↑ ↓ H H L H H L H X L or H L or H X Q0 Q0 Q0 H H L X ↑ ↓ L L H L H H L X ↑ ↓ H H H H H H L X L or H L or H X Q0 Q0 Q0 ↑ ↓ L L H L H H H L H H H L ↑ ↓ H H H H H H H L L or H L or H X Q0 Q0 Q0 H H H H ↑ ↓ L Q0 H L H H H H ↑ ↓ H Q0 H H H H H H L or H L or H X Q0 Q0 Q0 L X or floating X or floating X or floating X or floating X or floating X or floating L L L 1186G—04/16/07 6 ICSSSTUB32871A Ball Assignments 27 bit 1:1 Register A DCKE0 D0 V REF V DD QCKE0 QCKE1 B DCKE1 D1 GND GND Q0 Q1 C D2 V DD V DD Q2 DNU D DODT0 PTYERR GND GND QODT0 QODT1 E D3 D4 V DD V DD Q3 Q4 F D5 D6 GND GND Q5 Q6 G PAR_IN RESET V DD V DD NC NC H CK DCS0 GND GND QCS0 QCS1 J CK DCS1 V DD V DD NC NC K D7 D8 GND GND Q7 Q8 D10 V DD V DD Q9 Q10 M D11 D12 GND GND Q11 Q12 N D13 D14 V DD V DD Q13 Q14 P D15 D16 GND GND Q15 Q16 R D17 D18 V DD V DD Q17 Q18 T D19 D20 CSGateEN V DD Q19 Q20 L DODT1 D9 1 2 3 4 1186G—04/16/07 2 5 6 ICSSSTUB32871A General Description This 27-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The ICSSSTUB32871A operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low. The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the ICSSSTUB32871A must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high. If either DCS0 or DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs low and the PTYERR output high. If the DCS-control functionality is not desired, then the CSGateEnable input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. The ICSSSTU32871A includes a parity checking function. The ICSSSTUB32871A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). Package options include 96-ball Thin Profile Fine Pitch BGA (TFBGA, MO-TBD). Inputs * Output of inputs = H (D0-D21) RESET DCS0 DCS1 CK CK H L H ↑ ↓ Even L H L H ↑ ↓ Odd L L H L H ↑ ↓ Even H L H L H ↑ ↓ Odd H H H H L ↑ ↓ Even L H H H L ↑ ↓ Odd L L Even H L Odd H H H H L ↑ ↓ H H L ↑ ↓ PARIN* PTYERR** H H H H ↑ ↓ X X PTYERR 0 H X X L or H L or H X X PTYERR 0 L X or floating X or floating X or floating X or floating X or floating X or floating H PARIN arrives one clock cycle after the data to which it applies. ** This transition assumes PTYERR is high at the crossing of CK going high and CK going low. If PTYERR is low, it stays latched low for two clock cycles or until RESET is driven low. 1186G—04/16/07 3 ICSSSTUB32871A Ball Assignment Signal Group Signal Name Type Description Ungated inputs DCKE0, DCKE1, SSTL_18 DODT0, DODT1 DRAM function pins not associated with Chip Select. Chip Select gated inputs D0 ... D20 SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW. Chip Select inputs DCS0 , DCS1 SSTL_18 DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be low when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSGateEN high) when at least one Chip Select input is LOW. Re-driven outputs Q0...Q20, QCS0-1, QCKE0-1, QODT0-1 SSTL_18 Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock. Parity input PARIN SSTL_18 Input parity is received on pin PARIN and should maintain odd parity across the D0...D20 inputs, at the rising edge of the clock. Parity error output PTYERR Open drain When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in JEDEC definition). Program inputs CSGateEN 1.8 V LVCMOS Chip Select Gate Enable. When HIGH, the D0..D20 inputs will be latched only when at least one Chip Select input is LOW during the rising edge of the clock. When LOW, the D0...D20 inputs will be latched and redriven on every rising edge of the clock. Clock inputs CK, CK SSTL_18 Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CK). Miscellaneous inputs RESET 1.8 V LVCMOS Asynchronous reset input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal. VREF 0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability. 1186G—04/16/07 4 ICSSSTUB32871A Block Diagram (CS ACTIVE) VREF D PARIN PARITY GENERATOR AND CHECKER Q 21 R D D0 PTYERR Q Q0 Q Q20 Q QCS0 Q QCS1 R D D20 R DCS0 D R CSGateEN DCS1 D R DCKE0, DCKE1 2 2 D Q QCKE0, QCKE1 R DODT0, DODT1 2 2 D Q R RESET CK CK 1186G—04/16/07 5 QODT0, QODT1 ICSSSTUB32871A Parity Functionality Block Diagram 21 21 D Dn Qn Q D PARIN D PTYERR LATCHING AND RESET FUNCTION see Note (1) (1) This function holds the error for two cycles. See functional description and timing diagram. D CLOCK 002aaa417 1186G—04/16/07 6 ICSSSTUB32871A Register Timing RESET DCSn n n+1 n+2 n+3 n+4 CK CK tACT tsu th Dn (1) tPDM, tPDMSS CK to Q Qn tsu th PARIN tPHL CK to PTYERR PTYERR H, L, or X tPHL, tPLH CK to PTYERR H or L Figure 4 —RESET switches from L to H (1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a minimum time of t ACT (max) to avoid false error. 1186G—04/16/07 7 ICSSSTUB32871A Register Timing RESET DCSn n n+1 n+2 n+3 n+4 CK CK tsu th Dn (1) tPDM, tPDMSS CK to Q Qn tsu th PARIN tPHL, tPLH CK to PTYERR PTYERR 002aaa984 Unknown input event Output signal is dependent on the pr ior unknown event Figure 5 — RESET being held HIGH 1186G—04/16/07 8 H or L ICSSSTUB32871A Register Timing RESET tINACT DCSn CK (1) CK (1) Dn (1) tRPHL RESET to Q Qn PARIN (1) tRPLH RESET to PTYERR PTYERR H, L, or X H or L Figure 6 — RESET switches from H to L (1) After Reset is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not floating) for a minimum time of t INACT (max) 1186G—04/16/07 9 ICSSSTUB32871A Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage1, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . VDD or GND Current/Pin . . . . . . . . . . . . . . . . –65°C to +150°C -0.5V to 2.5V -0.5V to VDD +2.5V -0.5V to VDDQ + 0.5V ±50 mA ±50mA ±50mA ±100mA Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 2.5V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. Package Thermal Impedance3 . . . . . . . . . . . . . . . 36°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions PARAMETER VDDQ V REF V TT VI V IH (DC) V IH (AC) V IL (DC) VIL (AC) VIH VIL VICR V ID I OH I OL TA DESCRIPTION I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level RESET Input Low Voltage Level Common mode Input Range CK, CK Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature 1 MIN TYP 1.7 1.8 0.49 x VDD 0.5 x V DD VREF - 0.04 V REF 0 VREF + 0.125 VREF + 0.250 MAX 1.9 0.51 x VDD VREF + 0.04 VDDQ VREF - 0.125 VREF - 0.250 UNITS V 0.65 x VDDQ 0.675 0.600 0 0.35 x V DDQ 1.125 -8 8 70 mA °C Guaranteed by design, not 100% tested in production. Note: Rst and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless Rst is low. 1186G—04/16/07 10 ICSSSTUB32871A Electrical Characteristics - DC TA = 0 - 70°C; V DD = 2.5 +/-0.2V, V DDQ=2.5 +/-0.2V; (unless otherwise stated) SYMBOL PARAMETERS VOH VOL II All Inputs Standby (Static) I DD Operating (Static) Dynamic operating (clock only) CONDITIONS VDDQ 1.7V 1.7V 1.9V I OH = -8mA I OL = 8mA V I = V DD or GND RESET = GND VI = VIH(AC) or V IL(AC), RESET = VDD MIN 1.2 TYP MAX 0.5 ±5 200 1.9V 150 RESET = VDD,VI = V IH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle. UNITS V µA µA mA TBD µA/clock MHz TBD µA/ clock MHz/data IO = 0 I DDD Ci RESET = VDD, VI = V IH(AC) or VIL (AC), CLK and CLK Dynamic Operating switching 50% duty cycle. (per each data One data input switching input) at half clock frequency, 50% duty cycle Data Inputs CLK and CLK RESET 1.8V VI = VREF ±350mV VICR = 1.25V, V I(PP) = 360mV VI = V DDQ or GND 2.5 2 5 3.8 4.5 Notes: 1 - Guaranteed by design, not 100% tested in production. Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range (See figure 7) VDD = 1.8V ± 0.1V PARAMETER UNIT MIN MAX dV/dt_r 1 4 V/ns dV/dt_f 1 4 V/ns 1 dV/dt_Δ 1 V/ns 1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate) 1186G—04/16/07 11 pF pF ICSSSTUB32871A Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) V DD = 1.8V ±0.1V PARAMETERS SYMBOL MIN MAX f clock Clock frequency 410 tW Pulse duration 1 t ACT Differential inputs active time 10 t INACT Differential inputs inactive time tS Setup time Hold time tH Hold time Notes: 15 Data before CLK↑, CLK↓ DCS0, DSC1 before CLK↑, CLK↓, CSR HIGH DCS, DODT, DCKE and Dn after CLK↑, CLK↓ PAR_IN after CLK↑, CLK↓ 0.6 ns 0.5 ns Switching Characteristics 410 Propagation delay, single CLK↑ and CLK↓ to Qn bit switching Low to High propagation CLK↑ and CLK↓ to t LH delay PTYERR High to low propagation CLK↑ and CLK↓ to t HL delay PTYERR Propagation delay t PDMSS CLK↑ and CLK↓ to Qn simultaneous switching High to low propagation t PHL RESET ↓ to Qn↓ delay Low to High propagation t PLH RESET ↓ to PTYERR↑ delay 1. Guaranteed by design, not 100% tested in production. t PDM 1186G—04/16/07 12 ns ns 0.7 1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate of 1V/ns. 3 - For data signal input slew rate of 0.5V/ns and < 1V/ns. 4 - CLK/CLK signal input slew rate of 1V/ns. Max input clock frequency MHz ns ns 0.6 (over recommended operating free-air temperature range, unless otherwise noted) Measurement Symbol Parameter MIN MAX Conditions fmax UNITS Units MHz 1.25 1.9 ns 1.2 3 ns 0.9 3 ns 2 ns 3 ns 3 ns ICSSSTUB32871A VDD DUT TL=50Ω CK Inputs RL = 1000Ω TL=350ps, 50Ω CK CK Out Test Point CL = 30 pF (see Note 1) Test Point RL = 1000Ω RL = 100Ω LOAD CIRCUIT Test Point VCMOS RST Inp ut VDD VDD/2 VDD/2 t in act IDD (see Note 2) V ID 0V CK CK t PLH 90% t PHL 10% VOH Output VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES VICR V TT VTT VICR VOLTAGE WAVEFORMS – PULSE DURATION VID CK LVCMOS RST Input VIH VDD /2 VIL VICR t RPHL CK t su Inpu t VOL VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES VID tw Inpu t VICR VICR t act VREF VOH th Output VREF VIH VTT V OL VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES VIL VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES Figure 6 — Parameter Measurement Information (VDD = 1.8V ± 0.1V) Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VREF = VDD/2 6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600 mV 9. tPLH and tPHL are the same as tPDM. 1186G—04/16/07 13 ICSSSTUB32871A VDD DUT RL = 50Ω Out Test Point C L = 10 pF (see Note 1) LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT Output VOH 80% 20% dv _f VOL dt _f VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT DUT Out Test Point CL = 10 pF (see Note 1) RL = 50Ω LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT dt _r dv _r 80% VOH 20% Output VOL VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT Figure 7 — Output Slew-Rate Measurement Information (VDD = 1.8V± 0.1V) Notes: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 1186G—04/16/07 14 ICSSSTUB32871A 3 Test circuits and switching waveforms (cont’d) 3.3 Error output load circuit and voltage measurement information (VDD = 1.8 V ± 0.1 V) All input pulses are supplied by generators having the following characteristics: PRR Zo = 50 Ω ; input slew rate = 1 V/ns ± 20%, unless otherwise specified. 10 MHz; VDD DUT RL = 1K Ω Out Test Point CL = 10 pF (see Note 1) LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT (1) CL includes probe and jig capacitance. Figure 28 — Load circuit, error output measurements LVCMOS RST Input V CC V CC /2 0V t PLH V OH Output Waveform 2 V _ _ _ _ _ _ _ _ _0.15 __ 0V Figure 29 — Voltage waveforms, open-drain output low-to-high transition time with respect to reset input V I(PP) Timing Inputs V ICR VICR tPHL Output Waveform 1 ___________ V CC /2 V CC V OL Figure 30 — Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs V I(PP) Timing Inputs VICR VICR tPHL Output Waveform 2 V OH 0.15 V 0V Figure 31 — Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs 1186G—04/16/07 15 ICSSSTUB32871A 3 Test circuits and switching waveforms (cont’d) 3.4 Partial-parity-out load circuit and voltage measurement information (VDD = 1.8 V ± 0.1 V) All input pulses are supplied by generators having the following characteristics: PRR Zo = 50 Ω ; input slew rate = 1 V/ns ± 20%, unless otherwise specified. 10 MHz; DUT Test Point Out CL = 5 pF (see Note A) RL = 1 k Ω (1) CL includes probe and jig capacitance. Figure 32 — Partial-parity-out load circuit, CK VICR VICR tPLH tPHL Vi(p-p) CK VOH VTT OUTPUT VOL 002aaa375 VTT = VDD/2 tPLH and tPHL are the same as tPD. VI(PP) = 600 mV Figure 33 — Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs LVCMOS RST VIH INPUT VDD/2 VIL tPHL VOH VTT OUTPUT 002aaa376 VOL VTT = VDD/2 tPLH and tPHL are the same as tPD. VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250 mV (AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs. Figure 34 — Partial-parity-out voltage waveforms; propagation delay times with respect to reset input 1186G—04/16/07 16 ICSSSTUB32871A C Seating Plane A1 T Numeric Designations for Horizontal Grid b REF 4 3 2 1 A B C D D Alpha Designations for Vertical Grid (Letters I, O, Q & S not used) d TYP D1 - e - TYP TOP VIEW E c REF h TYP 0.12 C - e - TYP E1 ALL DIMENSIONS IN MILLIMETERS ----- BALL GRID ----Max. T e HORIZ VERT TOTAL d Min/Max Min/Max 13.50 Bsc 5.50 Bsc 1.20/1.40 0.80 Bsc 6 16 96 0.40/0.50 11.50 Bsc 5.00 Bsc 1.00/1.20 0.65 Bsc 6 16 96 0.35/0.45 Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. D E h Min/Max 0.25/0.41 0.25/0.35 REF. DIMENSIONS b c 0.75 0.875 * Source Ref.: JEDEC Publication 95, 10-0055C Ordering Information ICSSSTUB32871Az(LF)T Example: ICS XXXX y z (LF) T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type H = LFBGA (reduced size: 5.5 x 13.50) HM = TFBGA (reduced size: 5.0 x 11.50) Revision Designator (will not correlate with datasheet revision) Device Type 1186G—04/16/07 Prefix ICS = Standard Device 17 0.75 0.875 MO-205 ICSSSTUB32871A Revision History Rev. B C D E F G Issue Date Description Page # 3/20/2006 Updated Ordering Information. 17 Applications, 2nd bullet, changed ULP877 to ULPA877A, added 2/2/2007 1 IDTCSPUA877A Page 1, Applications, 3rd bullet, removed 800; page 11, Electrical table, changed Idd Operating Max from 80 to 150, changed RESET Typ from 2.5 1, 11, 12 3/1/2007 to 4.5; page 12, Timing table, changed ts (Data before...) from 0.5 to 0.6, changed th (DCS, DODT...) from 0.5 t Timing table, th hold time, changed Q to Dn; Switching Cha. Table, fixed 3/6/2007 12 typos. Page 1, Recc. List, changed 3rd bullet to "Provides complete DDR DIMM 3/13/2007 solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A"; page 1, 11 11, fixed typos. Electrical Cha. Table, changed Ci: Data Inputs max from 3.5 to 5, and 4/16/2007 11 CLK Max from 3 to 3.8. 1186G—04/16/07 18