ISSI IS41LV44002B-50J

ISSI
IS41LV44002B
4M x 4 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
®
JULY 2006
FEATURES
DESCRIPTION
• Extended Data-Out (EDO) Page Mode access cycle
• TTL compatible inputs and outputs
• Refresh Interval:
The ISSI IS41LV44002B is 4,194,304 x 4-bit high-performance CMOS Dynamic Random Access Memory. These
devices offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 2,048 random accesses within a single row with access cycle time as short
as 20 ns per 4-bit word.
•
•
•
•
•
– 2,048 cycles/32 ms
Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
Single power supply: 3.3V ± 10%
Byte Write and Byte Read operation via two CAS
Industrial Temperature Range: -40°C to +85°C
Lead-free available
IS41LV44002B
The IS41LV44002B is packaged in a 24-pin 300-mil SOJ
and 300-mil TSOP2 with JEDEC standard pinouts.
KEY TIMING PARAMETERS
PRODUCT SERIES OVERVIEW
Part No.
These features make the IS41LV44002B ideally suited for
high-bandwidth graphics, digital signal processing, highperformance computing systems, and peripheral
applications.
Refresh
Voltage
2K
3.3V ± 10%
Parameter
-50
Unit
RAS Access Time (tRAC)
50
ns
CAS Access Time (tCAC)
13
ns
Column Address Access Time (tAA)
25
ns
EDO Page Mode Cycle Time (tPC)
20
ns
Read/Write Cycle Time (tRC)
84
ns
PIN CONFIGURATION: 24-pin SOJ, TSOP2
VDD
1
24
GND
I/O0
2
23
I/O3
I/O1
3
22
I/O2
PIN DESCRIPTIONS
A0-A10
Address Inputs
WE
4
21
CAS
I/O0-3
Data Inputs/Outputs
RAS
5
20
OE
NC
6
19
A9
WE
Write Enable
OE
Output Enable
RAS
Row Address Strobe
A10
7
18
A8
A0
8
17
A7
A1
9
16
A6
CAS
Column Address Strobe
A2
10
15
A5
VDD
Power
A3
11
14
A4
VDD
12
13
GND
GND
Ground
NC
No Connection
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
1
ISSI
IS41LV44002B
®
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
CAS
WE
OE
CONTROL
LOGIC
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
ADDRESS
BUFFERS
A0-A10
ROW DECODER
REFRESH
COUNTER
DATA I/O BUFFERS
RAS
CLOCK
GENERATOR
RAS
RAS
MEMORY ARRAY
4,194,304 x 4
I/O0-I/O3
TRUTH TABLE
Function
Standby
Read
Write: Word (Early Write)
Read-Write
EDO Page-Mode Read
1st Cycle:
2nd Cycle:
EDO Page-Mode Write
1st Cycle:
2nd Cycle:
EDO Page-Mode
1st Cycle:
Read-Write
2nd Cycle:
Hidden Refresh
Read
Write(1)
RAS-Only Refresh
CBR Refresh
RAS
H
L
L
L
L
L
L
L
L
L
L→H→L
L→H→L
L
H→L
CAS
H
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L
L
H
L
WE
X
H
L
H→L
H
H
L
L
H→L
H→L
H
L
X
X
OE
X
L
X
L→H
L
L
X
X
L→H
L→H
L
X
X
X
Address tR/tC
X
ROW/COL
ROW/COL
ROW/COL
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
ROW/COL
ROW/NA
X
I/O
High-Z
DOUT
DIN
DOUT, DIN
DOUT
DOUT
DIN
DIN
DOUT, DIN
DOUT, DIN
DOUT
DOUT
High-Z
High-Z
Note:
1. EARLY WRITE only.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
ISSI
IS41LV44002B
®
Functional Description
Auto Refresh Cycle
The IS41LV44002B is a CMOS DRAMs optimized for
high-speed bandwidth, low power applications. During
READ or WRITE cycles, each bit is uniquely addressed
through the 11 address bits. These are entered 11 bits
(A0-A10) at a time for the 2K refresh device. The row
address is latched by the Row Address Strobe (RAS). The
column address is latched by the Column Address Strobe
(CAS). RAS is used to latch the first nine bits and CAS is
used the latter ten bits.
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
Memory Cycle
A memory cycle is initiated by bringing RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time
specified by tAR. Data Out becomes valid only when tRAC,
tAA, tCAC and tOEA are all satisfied. As a result, the access
time is dependent on the timing relationships between
these parameters.
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write, read-modify-write or RAS-only cycle refreshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS
refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the VDD supply, an initial pause of 200
µs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a RAS
signal).
During power-on, it is recommended that RAS track with
VDD or be held at a valid VIH to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
3
ISSI
IS41LV44002B
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
Rating
Unit
VT
Voltage on Any Pin Relative to GND
–0.5 to +4.6
V
VDD
Supply Voltage
–0.5 to +4.6
V
IOUT
Output Current
50
mA
PD
Power Dissipation
1
W
TA
Operating Temperature
-40 to +85
°C
TSTG
Storage Temperature
–55 to +125
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Supply Voltage
3.0
3.3
3.6
V
VIH
Input High Voltage
2.0
—
VDD + 0.3
V
VIL
Input Low Voltage
–0.3
—
0.8
V
TA
Commercial Ambient Temperature
Industrial Ambient Temperature
0
-40
—
—
+70
+85
°C
°C
CAPACITANCE(1,2)
Symbol
CIN1
CIN2
CIO
Parameter
Input Capacitance: A0-A10
Input Capacitance: RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O3
Max.
Unit
5
7
7
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
ISSI
IS41LV44002B
®
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
IIL
Input Leakage Current
IIO
Speed
Min.
Max.
Unit
Any input 0V ≤ VIN ≤ VDD
Other inputs not under test = 0V
–5
5
µA
Output Leakage Current
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ VDD
–5
5
µA
VOH
Output High Voltage Level
IOH = –2.0 mA, VDD = 3.3V
2.4
—
V
VOL
Output Low Voltage Level
IOL = 2 mA, VDD = 3.3V
—
0.4
V
ICC1
Standby Current: TTL
RAS, CAS ≥ VIH
—
2
mA
ICC2
Standby Current: CMOS
RAS, CAS ≥ VDD – 0.2V
—
0.5
mA
ICC3
Operating Current:
Random Read/Write(2,3,4)
Average Power Supply Current
RAS, CAS,
Address Cycling, tRC = tRC (min.)
-50
—
120
mA
ICC4
Operating Current:
EDO Page Mode(2,3,4)
Average Power Supply Current
RAS = VIL, CAS,
Cycling tPC = tPC (min.)
-50
—
90
mA
ICC5
Refresh Current:
RAS-Only(2,3)
Average Power Supply Current
RAS Cycling, CAS ≥ VIH
tRC = tRC (min.)
-50
—
120
mA
ICC6
Refresh Current:
CBR(2,3,5)
Average Power Supply Current
RAS, CAS Cycling
tRC = tRC (min.)
-50
—
120
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
5
ISSI
IS41LV44002B
®
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
Symbol
tRC
tRAC
tCAC
tAA
tRAS
tRP
tCAS
tCP
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
tRAD
tRAL
tRPC
tRSH
tRHCP
tCLZ
tCRP
tOD
tOE
tOED
tOEHC
tOEP
tOES
tRCS
tRRH
tRCH
tWCH
tWCR
tWP
tWPZ
6
Parameter
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
RAS Precharge Time
CAS Pulse Width(23)
CAS Precharge Time(9)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
Column-Address Hold Time
(referenced to RAS)
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 24)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 24)
Output Enable Time(15, 16)
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
Read Command Hold Time
(referenced to RAS)(12)
Read Command Hold Time
(referenced to CAS)(12, 17, 21)
Write Command Hold Time(17)
Write Command Hold Time
(referenced to RAS)(17)
Write Command Pulse Width(17)
WE Pulse Widths to Disable Outputs
Min.
84
—
—
—
50
30
8
9
38
12
0
8
0
8
30
Max.
—
50
13
25
10K
—
10K
—
—
37
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
25
5
8
30
0
5
3
—
12
25
—
—
—
—
—
—
15
12
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
10
5
0
0
—
—
—
—
—
ns
ns
ns
ns
ns
0
—
ns
8
40
—
—
ns
ns
8
7
—
—
ns
ns
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
ISSI
IS41LV44002B
®
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tRWL
tCWL
tWCS
tDHR
tACH
tOEH
tDS
tDH
tRWC
tRWD
tCWD
tAWD
tPC
tRASP
tCPA
tPRWC
tCOH
tOFF
tWHZ
tCSR
tCHR
tORD
tREF
tT
Parameter
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
OE Hold Time from WE during
READ-MODIFY-WRITE cycle(18)
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
EDO Page Mode READ or WRITE
Cycle Time
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
EDO Page Mode READ-WRITE
Cycle Time
Data Output Hold after CAS LOW
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 24)
Output Disable Delay from WE
CAS Setup Time (CBR REFRESH)(20, 25)
CAS Hold Time (CBR REFRESH)( 21, 25)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
Auto Refresh Period 2,048 Cycles
Transition Time (Rise or Fall)(2, 3)
-50
Min.
13
8
0
39
15
Max.
—
—
—
—
—
Units
ns
ns
ns
ns
ns
8
—
ns
0
8
108
64
—
—
—
—
ns
ns
ns
ns
26
39
20
—
—
—
ns
ns
ns
50
—
56
100K
30
—
ns
ns
ns
5
0
—
12
ns
ns
3
5
8
10
—
—
ns
ns
ns
0
—
ns
—
1
32
50
ms
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF
Input timing reference levels: VIH = 2.4V, VIL = 0.8V
Output timing reference levels: VOH = 2.0V, VOL = 0.8V
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
7
IS41LV44002B
ISSI
®
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a
monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD ≥ tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data
output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is
greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is
greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD
(MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and
OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles.
23. CAS must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
ISSI
IS41LV44002B
®
READ CYCLE
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
tRRH
CAS
tAR
tRAD
tRAH
tASR
ADDRESS
tRAL
tCAH
tASC
Row
Column
Row
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLC
I/O
tOFF(1)
Open
Open
Valid Data
tOE
tOD
OE
tOES
Don’t Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
9
ISSI
IS41LV44002B
®
EARLY WRITE CYCLE (OE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
CAS
tAR
tRAD
tRAH
tASR
ADDRESS
tRAL
tCAH
tACH
tASC
Row
Column
Row
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE
tDHR
tDS
I/O
tDH
Valid Data
Don’t Care
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
ISSI
IS41LV44002B
®
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
CAS
tAR
tRAD
tASR
tRAH
tRAL
tCAH
tASC
tACH
ADDRESS
Row
Column
Row
tRWD
tCWL
tRWL
tCWD
tRCS
tAWD
tWP
WE
tAA
tRAC
tCAC
tCLZ
I/O
tDS
Open
Valid DOUT
tOE
tOD
tDH
Valid DIN
Open
tOEH
OE
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
11
ISSI
IS41LV44002B
®
EDO-PAGE-MODE READ CYCLE
tRASP
tRP
RAS
tCSH
tCRP
tCAS,
tCLCH
tRCD
tCP
tPC(1)
tCAS,
tCLCH
tCP
tRSH
tCAS,
tCLCH
tCP
CAS
tAR
tRAD
tASR
ADDRESS
tASC
tCAH tASC
Row
Column
tRAL
tCAH
tCAH tASC
Column
Column
Row
tRAH
tRRH
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLZ
I/O
Open
tAA
tCPA
tCAC
tCOH
tCAC
tCLZ
Valid Data
tOE
tOES
tAA
tCPA
tOFF
Valid Data
tOEHC
Valid Data
Open
tOE
tOD
tOES
tOD
OE
tOEP
Don’t Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
ISSI
IS41LV44002B
®
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP
tRP
RAS
tCSH
tCRP
tPC
tCAS,
tCLCH
tRCD
tCP
tCAS,
tCLCH
tCP
tRSH
tCAS,
tCLCH
tCP
CAS
tAR
tACH
tCAH tASC
tRAD
tASR
ADDRESS
tASC
Row
Column
tRAH
tACH
tRAL
tCAH
tACH
tCAH tASC
Column
tCWL
tWCS
Column
tCWL
tWCS
tWCH
tCWL
tWCS
tWCH
tWCH
tWP
tWP
Row
tWP
WE
tWCR
tDHR
tRWL
tDS
tDS
tDH
I/O
Valid Data
tDS
tDH
Valid Data
tDH
Valid Data
OE
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
13
ISSI
IS41LV44002B
®
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
tRASP
tRP
RAS
tCSH
tCRP
tCAS, tCLCH
tRCD
tCP
tPC / tPRWC(1)
tCAS, tCLCH
tRSH
tCAS, tCLCH
tCP
tCP
CAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
tCAH
Row
tASC
tCAH
Column
tRWD
tRCS
tRAL
tCAH
tASC
Column
tCWL
tWP
Column
tRWL
tCWL
tWP
tCWL
tWP
tAWD
tCWD
Row
tAWD
tCWD
tAWD
tCWD
WE
tAA
tAA
tCPA
tDH
tDS
tRAC
tCAC
tCLZ
I/O
Open
tCAC
tCLZ
DOUT
DIN
DIN
DOUT
tOD
tOE
tDH
tDS
tCAC
tCLZ
DOUT
tOD
tOE
tAA
tCPA
tDH
tDS
Open
DIN
tOD
tOE
tOEH
OE
Don’t Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
ISSI
IS41LV44002B
®
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY WRITE)
tRASP
tRP
RAS
tCSH
tPC
tPC
tCRP
tCAS
tRCD
tCAS
tCP
tRSH
tCAS
tCP
tCP
CAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
Row
tCAH
tASC
tCAH
Column (A)
tASC
Column (B)
tRCS
tACH
tRAL
tCAH
Column (N)
Row
tRCH
tWCS
tWCH
WE
tAA
tCPA
tCAC
tRAC
tCAC
tAA
tWHZ
tCOH
I/O
Open
Valid Data (A)
tDS
Valid Data (B)
tDH
DIN
Open
tOE
OE
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
15
ISSI
IS41LV44002B
®
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
tCSH
tCRP
tRCD
tCP
tCAS
CAS
tAR
tRAD
tASR
ADDRESS
tRAH
tCAH
tASC
Row
tASC
Column
Column
tRCS
tRCH
tRCS
WE
tAA
tRAC
tCAC
tCLZ
Open
I/O
tWHZ
tCLZ
Valid Data
Open
tOE
tOD
OE
Don’t Care
RAS
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCRP
tRPC
CAS
tASR
ADDRESS
I/O
tRAH
Row
Row
Open
Don’t Care
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
ISSI
IS41LV44002B
®
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
tRP
tRAS
tRP
tRAS
RAS
tRPC
tCP
tCHR
tCHR
tRPC
tCSR
tCSR
CAS
Open
I/O
Don’t Care
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAS
tRP
tRAS
RAS
tCRP
tRCD
tRSH
tCHR
CAS
tAR
tRAD
tRAH tASC
tASR
ADDRESS
Row
tRAL
tCAH
Column
tAA
tRAC
tOFF(2)
tCAC
tCLZ
I/O
Open
Valid Data
tOE
Open
tOD
tORD
OE
Don’t Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
17
ISSI
IS41LV44002B
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
50
50
50
50
Order Part No.
IS41LV44002B-50J
IS41LV44002B-50JL
IS41LV44002B-50T
IS41LV44002B-50TL
Refresh
2K
2K
2K
2K
Package
300-mil SOJ
300-mil SOJ, Lead-free
300-mil TSOP2
300-mil TSOP2, Lead-free
Industrial Range: -40°C to +85°C
Speed (ns)
50
50
50
50
18
Order Part No.
IS41LV44002B-50JI
IS41LV44002B-50JLI
IS41LV44002B-50TI
IS41LV44002B-50TLI
Refresh
2K
2K
2K
2K
Package
300-mil SOJ
300-mil SOJ, Lead-free
300-mil TSOP2
300-mil TSOP2, Lead-free
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
07/05/06
ISSI
PACKAGING INFORMATION
®
300-mil Plastic SOJ
Package Code: J
N
E1
E
1
SEATING PLANE
D
A
B
e
A2
C
b
A1
E2
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
24/26
A
—
—
3.56
—
A1
0.64
—
—
0.025
—
—
A2
2.41
—
2.67
0.095
—
0.105
b
0.41
—
0.51
0.016
—
0.020
B
0.66
—
0.81
0.026
—
0.032
— 0.140
C
0.20
—
0.25
0.008
—
0.010
D
17.02
—
17.27
0.670
—
0.680
E
8.26
—
8.76
0.325
—
0.345
E1
7.49
—
7.75
0.295
—
0.305
E2
6.27
—
7.29
0.247
—
0.287
e
1.27 BSC
Notes:
1. Controlling dimension: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusions and should be measured from the bottom of
the package.
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/25/03
ISSI
PACKAGING INFORMATION
®
300-mil Plastic SOJ
Package Code: J
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
28
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
32
A
—
—
3.56
—
—
0.140
A
—
—
3.56
—
—
0.140
A1
0.64
—
—
0.025
—
—
A1
0.64
—
—
0.025
—
—
A2
2.41
—
2.67
0.095
—
0.105
A2
2.41
—
2.67
0.095
—
0.105
b
0.41
—
0.51
0.016
—
0.020
b
0.41
—
0.51
0.016
—
0.020
B
0.66
—
0.81
0.026
—
0.032
B
0.66
—
0.81
0.026
—
0.032
C
0.20
—
0.25
0.008
—
0.010
C
0.20
—
0.25
0.008
—
0.010
D
18.29
—
18.54
0.720
—
0.730
D
20.83
—
21.08
0.820
—
0.830
E
8.26
—
8.76
0.325
—
0.345
E
8.26
—
8.76
0.325
—
0.345
E1
7.49
—
7.75
0.295
—
0.305
E1
7.49
—
7.75
0.295
—
0.305
E2
6.27
—
7.29
0.247
—
0.287
E2
6.27
—
7.29
0.247
—
0.287
e
2
1.27 BSC
0.050 BSC
e
1.27 BSC
0.050 BSC
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/25/03
ISSI
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
E1 E
1
Notes:
1. Controlling dimension: millimeters, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protrusions and should be measured from the bottom of the
package.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
N/2
D
SEATING PLANE
A
e
Plastic TSOP (T - Type II) (MS 25)
Millimeters
Inches
Symbol Min Max
Min Max
Ref. Std.
N
24/26
A
1.20
0.0472
A1
0.05 0.15
0.002 0.0059
b
0.30 0.51
0.012 0.0201
c
0.12 0.21
0.005 0.0083
D
17.01 17.27
0.670 0.6899
E1
7.49 7.75
0.295 0.3051
e
1.27 BSC
0.050 BSC
E
9.02 9.42
0.462 0.4701
L
0.40 0.60
0.016 0.0236
α
0°
5°
0°
5°
Integrated Silicon Solution, Inc.
PK13197T40
Rev. C 08/013/99
®
b
L
A1
Plastic TSOP (T - Type II) (MS 24)
Millimeters
Inches
Symbol Min Max
Min Max
Ref. Std.
N
40/44
A
1.20
0.0472
A1
0.05 0.15
0.002 0.0059
b
0.30 0.45
0.012 0.0157
c
0.12 0.21
0.005 0.0083
D
18.31 18.51
0.721 0.7287
E1
10.06 10.26
0.396 0.4040
e
0.80 BSC
0.031 BSC
E
11.56 11.96
0.455 0.4709
L
0.40 0.60
0.016 0.0236
α
0°
8°
0°
8°
α
c
Plastic TSOP (T - Type II) (MS 24)
Millimeters
Inches
Symbol Min Max
Min Max
Ref. Std.
N
44/50
A
1.20
0.0472
A1
0.05 0.15
0.002 0.0059
b
0.30 0.45
0.012 0.0157
c
0.12 0.21
0.005 0.0083
D
20.85 21.05
0.821 0.8287
E1
10.06 10.26
0.396 0.4040
e
0.80 BSC
0.031 BSC
E
11.56 11.96
0.455 0.4709
L
0.40 0.60
0.016 0.0236
α
0°
8°
0°
8°