IS62WV1288ALL IS62WV1288BLL ISSI 128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM ® JUNE 2005 FEATURES DESCRIPTION • High-speed access time: 45ns, 55ns, 70ns The ISSI IS62WV1288ALL / IS62WV1288BLL are highspeed, 1M bit static RAMs organized as 128K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. • CMOS low power operation: 30 mW (typical) operating 15 µW (typical) CMOS standby When CS1 is HIGH (deselected) or when CS2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. • TTL compatible interface levels • Single power supply: 1.65V--2.2V VDD (62WV1288ALL) 2.5V--3.6V VDD (62WV1288BLL) • Fully static operation: no clock or refresh required • Three state outputs • Industrial temperature available Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62WV1288ALL and IS62WV1288BLL are packaged in the JEDEC standard 32-pin TSOP (TYPEI), sTSOP (TYPEI), SOP, and 36-pin mini BGA. • Lead-free available FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 CS2 CS1 OE CONTROL CIRCUIT WE Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 1 IS62WV1288ALL, PIN CONFIGURATION 36-pin mini BGA (B) (6mm x 8mm) 1 2 3 4 5 A0 A1 CS2 A3 A6 A8 B I/O4 A2 WE A4 A7 I/O0 C I/O5 NC A5 D GND VDD E VDD GND F I/O6 G I/O7 H A9 I/O1 NC NC OE CS1 A16 A15 I/O3 A10 A11 A12 A13 A14 I/O2 A0-A16 Address Inputs CS1 Chip Enable 1 Input CS2 Chip Enable 2 Input OE Output Enable Input WE Write Enable Input 32-pin TSOP (TYPE I) (T), 32-pin sTSOP (TYPE I) (H) 6 A PIN DESCRIPTIONS A11 A9 A8 A13 WE CS2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC 1 32 VDD A16 2 31 A15 A14 3 30 CS2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 Input/Output NC No Connection A5 7 26 A9 Power A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CS1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 GND Ground OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 32-pin SOP (Q) I/O0-I/O7 VDD 2 ISSI IS62WV1288BLL ® Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 IS62WV1288ALL, ISSI IS62WV1288BLL ® ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Related to GND Storage Temperature Power Dissipation Value –0.2 to VDD+0.3 –0.2 to +3.8 –65 to +150 1.0 Unit V V °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (VDD) Range Ambient Temperature IS62WV1288ALL 0°C to +70°C –40°C to +85°C 1.65V - 2.2V 1.65V - 2.2V Commercial Industrial IS62WV1288BLL 2.5V - 3.6V 2.5V - 3.6V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions VDD Min. Max. Unit VOH Output HIGH Voltage IOH = -0.1 mA IOH = -1 mA 1.65-2.2V 2.5-3.6V 1.4 2.2 — — V V VOL Output LOW Voltage IOL = 0.1 mA IOL = 2.1 mA 1.65-2.2V 2.5-3.6V — — 0.2 0.4 V V VIH(2) Input HIGH Voltage 1.65-2.2V 2.5-3.6V 1.4 2.2 VDD + 0.2 VDD + 0.3 V V VIL(1) Input LOW Voltage 1.65-2.2V 2.5-3.6V –0.2 –0.2 0.4 0.6 V V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Notes: 1. Undershoot: –1.0V for pulse width less than 10 ns. Not 100% tested. 2. Overshoot: VDD + 1.0V for pulse width less than 10 ns. Not 100% tested. TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE CS1 CS2 OE X X H H L H X L L L X L H H H X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 VDD Current ISB1, ISB2 ISB1, ISB2 ICC ICC ICC 3 IS62WV1288ALL, ISSI IS62WV1288BLL ® CAPACITANCE(1) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 8 pF VOUT = 0V 10 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 62WV1288ALL 62WV1288BLL (Unit) 0.4V to VDD-0.2V 5 ns VREF (Unit) 0.4V to VDD-0.3V 5ns VREF See Figures 1 and 2 See Figures 1 and 2 1.65V - 2.2V 2.5V - 3.6V R1(Ω) 3070 3070 R2(Ω) 3150 3150 VREF 0.9V 1.5V VTM 1.8V 2.8V AC TEST LOADS R1 R1 VTM VTM OUTPUT OUTPUT 30 pF Including jig and scope Figure 1 4 5 pF Including jig and scope R2 R2 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 IS62WV1288ALL, ISSI IS62WV1288BLL ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) 62WV1288ALL (1.65V - 2.2V) Symbol Parameter Test Conditions ICC VDD Dynamic Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX ICC1 Operating Supply Current TTL Standby Current (TTL Inputs) VDD = Max., IOUT = 0 mA, f = 0 VDD = Max., VIN = VIH or VIL CS1 = VIH , CS2 = VIL, f = 1 MHZ CMOS Standby Current (CMOS Inputs) VDD = Max., CS1 ≥ VDD – 0.2V, CS2 ≤ 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 ISB1 ISB2 Unit Com. Ind. typ.(2) Com. Ind. Com. Ind. Max. 70 ns 8 8 5 5 5 0.8 0.8 Com. Ind. typ.(2) 10 10 5 µA mA mA mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=1.8V, TA=25oC. Not 100% tested. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) 62WV1288BLL (2.5V - 3.6V) Symbol Parameter Test Conditions ICC VDD Dynamic Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX ICC1 Operating Supply Current TTL Standby Current (TTL Inputs) VDD = Max., IOUT = 0 mA, f = 0 VDD = Max., VIN = VIH or VIL CS1 = VIH , CS2 = VIL, f = 1 MHZ CMOS Standby Current (CMOS Inputs) VDD = Max., CS1 ≥ VDD – 0.2V, CS2 ≤ 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 ISB1 ISB2 Max. 55 ns 15 15 10 5 5 0.8 0.8 Unit Com. Ind. typ.(2) Com. Ind. Com. Ind. Max. 45ns 17 17 12 5 5 0.8 0.8 Com. Ind. typ.(2) 10 10 5 10 10 5 µA mA mA mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=3.0V, TA=25oC. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 5 IS62WV1288ALL, ISSI IS62WV1288BLL ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter 45 ns Min. Max. 55 ns Min. Max. 70 ns Min. Max. Unit tRC Read Cycle Time 45 — 55 — 70 — ns tAA Address Access Time — 45 — 55 — 70 ns tOHA Output Hold Time 10 — 10 — 10 — ns tACS1/tACS2 CS1/CS2 Access Time — 45 — 55 — 70 ns tDOE OE Access Time — 20 — 25 — 35 ns tHZOE(2) OE to High-Z Output 0 15 0 20 0 25 ns OE to Low-Z Output 5 — 5 — 5 — ns (2) tHZCS1/tHZCS2 CS1/CS2 to High-Z Output 0 15 0 20 0 25 ns (2) tLZCS1/tLZCS2 CS1/CS2 to Low-Z Output 5 — 10 — 10 — ns tLZOE(2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to VDD-0.2V/VDD-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH) tRC ADDRESS tAA tOHA DOUT 6 PREVIOUS DATA VALID tOHA DATA VALID Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 IS62WV1288ALL, ISSI IS62WV1288BLL ® AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled) tRC ADDRESS tAA tOHA OE tDOE CS1 tHZOE tLZOE tACS1/tACS2 CS2 DOUT tLZCS1/ tLZCS2 HIGH-Z tHZCS DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1= VIL. CS2=WE=VIH. 3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 7 IS62WV1288ALL, ISSI IS62WV1288BLL ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol 45 ns Min. Max. Parameter 55 ns Min. Max. 70 ns Min. Max. Unit tWC Write Cycle Time 45 — 55 — 70 — ns tSCS1/tSCS2 tAW CS1/CS2 to Write End 35 — 45 — 60 — ns Address Setup Time to Write End 35 — 45 — 60 — ns tHA tSA Address Hold from Write End 0 — 0 — 0 — ns Address Setup Time 0 — 0 — 0 — ns tPWE tSD WE Pulse Width 35 — 40 — 50 — ns Data Setup to Write End 20 — 25 — 30 — ns tHD tHZWE(3) Data Hold from Write End 0 — 0 — 0 — ns WE LOW to High-Z Output — 20 — 20 — 20 ns tLZWE(3) WE HIGH to Low-Z Output 5 — 5 — 5 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to VDD-0.2V/VDD-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN 8 tHD DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 IS62WV1288ALL, ISSI IS62WV1288BLL ® AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 tHD DATA-IN VALID 9 IS62WV1288ALL, ISSI IS62WV1288BLL ® DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR VDD for Data Retention See Data Retention Waveform 1.2 3.6 V IDR Data Retention Current VDD = 1.2V, CS1 ≥ VDD – 0.2V — 5 µA tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns tRDR Recovery Time See Data Retention Waveform tRC — ns DATA RETENTION WAVEFORM (CS1 CS1 Controlled) Data Retention Mode tSDR tRDR VDD VDR CS1 ≥ VDD - 0.2V CS1 GND DATA RETENTION WAVEFORM (CS2 Controlled) Data Retention Mode VDD CS2 tSDR tRDR VDR CS2 ≤ 0.2V GND 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 IS62WV1288ALL, ISSI IS62WV1288BLL ® ORDERING INFORMATION IS62WV1288ALL (1.65V - 2.2V) Industrial Range: -40°C to +85°C Speed (ns) 70 Order Part No. Package IS62WV1288ALL-70BI mini BGA (6mm x 8mm) IS62WV1288ALL-70HI sTSOP, TYPE I IS62WV1288BLL (2.5V-3.6V) Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Package 45 IS62WV1288BLL-45TI IS62WV1288BLL-45BI IS62WV1288BLL-45HI IS62WV1288BLL-45QI TSOP, TYPE I mini BGA (6mm x 8mm) sTSOP, TYPE I SOP 55 IS62WV1288BLL-55TI IS62WV1288BLL-55TLI IS62WV1288BLL-55BI IS62WV1288BLL-55HI IS62WV1288BLL-55HLI IS62WV1288BLL-55QI IS62WV1288BLL-55QLI TSOP, TYPE I TSOP, TYPE I, Lead-free mini BGA (6mm x 8mm) sTSOP, TYPE I sTSOP, TYPE I, Lead-free SOP SOP, Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 11 ISSI ® PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (36-pin) Top View Bottom View φ b (36x) 1 2 3 4 5 6 6 A 4 3 2 1 A e B B C C D D D 5 D1 E E F F G G H H e E E1 Notes: 1. Controlling dimensions are in millimeters. A2 A A1 SEATING PLANE mBGA - 6mm x 8mm mBGA - 8mm x 10mm MILLIMETERS INCHES MILLIMETER INCHES Sym. Min. Typ. Max. Min. Typ. Max. Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 36 36 N0. Leads 36 36 A — — 1.20 — — 0.047 A — — 1.20 — — 0.047 A1 0.24 — 0.30 0.009 — 0.012 A1 0.24 — 0.30 0.009 — 0.012 A2 0.60 — — 0.024 — — A2 0.60 — — 0.024 — — D 7.90 8.00 D 9.90 10.00 10.10 D1 E 8.10 5.25BSC 5.90 6.00 0.311 0.315 0.319 0.207BSC 6.10 D1 0.232 0.236 0.240 E 5.25BSC 7.90 0.390 0.394 0.398 .207BSC 8.00 8.10 0.311 0.315 0.319 E1 3.75BSC 0.148BSC E1 3.75BSC 0.148BSC e 0.75BSC 0.030BSC e 0.75BSC 0.030BSC 0.012 0.014 0.016 b b 0.30 0.35 0.40 0.30 0.35 0.40 0.012 0.014 0.016 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 01/15/03 ISSI ® PACKAGING INFORMATION 450-mil Plastic SOP Package Code: Q (32-pin) N E1 E 1 D SEATING PLANE A S MILLIMETERS Symbol No. Leads A A1 B C D E E1 e L α S Min. L B e A1 INCHES Max. Min. Max. 32 — 3.00 0.10 — 0.36 0.51 0.15 0.30 20.14 20.75 13.87 14.38 11.18 11.43 1.27 BSC 0.58 0.99 0° 10° — 0.86 — 0.118 0.004 — 0.014 0.020 0.006 0.012 0.793 0.817 0.546 0.566 0.440 0.450 0.050 BSC 0.023 0.039 0° 10° — 0.034 α C Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/13/03 ISSI PACKAGING INFORMATION Plastic STSOP - 32 pins Package Code: H (Type I) A2 A A1 1 N E b e D1 S SEATING PLANE D L Plastic STSOP (H - Type I) Millimeters Inches Symbol Min Max Min Max Ref. Std. N 32 A — 1.25 — 0.049 A1 0.05 — 0.002 — A2 0.95 1.05 0.037 0.041 b 0.17 0.23 0.007 0.009 C 0.14 0.16 0.0055 0.0063 D 13.20 13.60 0.520 0.535 D1 11.70 11.90 0.461 0.469 E 7.90 8.10 0.311 0.319 e 0.50 BSC 0.020 BSC L 0.30 0.70 0.012 0.028 S 0.28 Typ. 0.011 Typ. α 0° 5° 0° 5° Integrated Silicon Solution, Inc. PK13197H32 Rev. B 04/21/03 α C Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. ® ISSI PACKAGING INFORMATION ® Plastic TSOP-Type I Package Code: T (32-pin) 1 E H N D SEATING PLANE A S MILLIMETERS Symbol No. Leads A A1 B C D E H e L α S Min. L B e A1 INCHES Max. Min. Max. 32 — 1.20 0.05 0.25 0.17 0.23 0.12 0.17 7.90 8.10 18.30 18.50 19.80 20.20 0.50 BSC 0.40 0.60 0° 8° 0.25 REF — 0.047 0.002 0.010 0.007 0.009 0.005 0.007 0.311 0.319 0.720 0.728 0.780 0.795 0.020 BSC 0.016 0.024 0° 8° 0.010 REF α C Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/13/03