KB HE83R125

King Billion Electronics Co., Ltd
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HE83R125
HE80000 Series
- Table of Contents 1.
General Description ___________________________________________________________________1
2.
Features _____________________________________________________________________________2
3.
Pin Description _______________________________________________________________________3
4.
Pad Location _________________________________________________________________________5
5.
LCD Power Supply ____________________________________________________________________6
6.
LCDC Control register_________________________________________________________________7
7.
LCD RAM map_______________________________________________________________________8
8.
Oscillators ___________________________________________________________________________8
9.
General Purpose I/O___________________________________________________________________9
10.
Timer1 ___________________________________________________________________________11
11.
Timer2 ___________________________________________________________________________12
12.
Watch Dog Timer __________________________________________________________________14
13.
Pulse-Width Modulation ____________________________________________________________14
14.
Summary of Registers and Mask Options ______________________________________________15
15.
Absolute Maximum Rating __________________________________________________________16
16.
Recommended Operating Conditions _________________________________________________17
17.
AC/DC Characteristics _____________________________________________________________17
18.
Application Circuit_________________________________________________________________18
1. General Description
HE83R125 is a member of 8-bit MCU series developed by King Billion. 32 LCD segment driver pins are
multiplexed with I/O pins to provide flexibility of wide variety of combinations to suit the needs of
applications Users can choose any one of combinations from 320 dots LCD Driver with 8 Bit I/O Port to
64 dots LCD Driver with 40-bit I/O Port, etc. by mask option. The built-in LCD power regulator can
provide stable LCD display effect over wide range of battery voltage. The Pulse Width Modulation with
complementary outputs provides the complete speech output mechanism. The 128K ROM can store
around 40 second of speech. This chip is applicable to the small/medium systems such as LCD Games,
Perpetual Calendar etc. The instruction set or HE80000 easy to learn and use. Most of instructions take
March 13, 2003
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V1.0E
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HE83R125
HE80000 Series
only 3 oscillator clocks. This chip is suitable for the applications that require higher performance.
2. Features
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Operation Voltage:
System Clock:
2.4V ~ 5.5V
DC ~ 8MHz @ 5.0V
DC ~ 4MHz @ 2.4V
Internal ROM:
128 KB (64K Program ROM+ 64K Data ROM)
Internal RAM:
256 Bytes
Dual Clock System:
Fast clock:
32768 ~ 8M Hz
Slow clock: 32768 Hz
4 Operation Modes:
Fast, Slow, Idle, Sleep modes.
Watch Dog Timer to prevent deadlock condition.
40-bit Bi-directional I/O port with push-pull or Open-Drain output type selectable for each I/O
pin by mask option. 32 of them are multiplexed with LCD segment pins.
64 (8 COM x 8 SEG) ~ 320 (8 COM x 40 SEG) dot LCD driver.
Built-in LCD power regulator to provide stable working voltage (~3Volt)
‹ When VDD≧2.4Volt, LV4 output voltage around 3volts.
‹ When VDD＜2.4Volt；LV4, 3, 2, 1 output voltage will going down with VDD
Complementary Pulse-Width Modulation outputs.
Two external interrupts and two internal timer interrupts.
Two 16-bit timers.
Instruction set: 32 instructions with 4 addressing modes.
Application field: LCD Games, Perpetual Calendar, etc.
March 13, 2003
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HE83R125
HE80000 Series
PRTD0
PRTD1
PRTD2
PRTD3
PRTD4
PRTD5
PRTD6
PRTD7
VDD
SXI
SXO
TSTP
FXI
FXO
RSTP
GND
LV4
LV3
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
3. Pin Description
1
2
3
4
PWMP
PWMN
GND
PRT177
PRT176
PRT175
PRT174
PRT173
PRT172
PRT171
PRT170
PRT157
PRT156
PRT155
PRT154
PRT153
HE83R125
LV2
LV1
LVF
LC2
LC1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PRT152
PRT151
PRT150
PRT147
PRT146
PRT145
PRT144
PRT143
PRT142
PRT141
PRT140
PRT117
PRT116
PRT115
PRT114
PRT113
PRT112
PRT111
PRT110
5
6
7
8
9
10
11
12
13
14
15
16
17
VDD
Pin Name
VDD
PWMP
PWMN
GND
Pin #
1
2
3
4
PRT17[7..0] 5 ~ 12
PRT15[7..0] 13 ~ 20
PRT14[7..0] 21 ~ 28
March 13, 2003
I/O
P
O
O
P
Description
Dedicated Power for Pulse Width Modulation output.
Pulse Width Modulation output.
Complementary output to PWMP.
Dedicated Power for Pulse Width Modulation output.
8-bit bi-directional I/O port 17 is shared with LCD segment pads SEG[39..32].
The function of the pad can be selected individually by mask options
MO_LIO17[7..0]. (‘1’ for LCD and ‘0’ for I/O).
B/
The output type of I/O pad can also be selected by mask option MO_17PP[7..0]
O
(1 for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using
the I/O as input, “1” must be outputted before reading.
8-bit bi-directional I/O port 15 is shared with LCD segment pads SEG[31..24].
The function of the pad can be selected individually by mask options
MO_LIO15[7..0]. (‘1’ for LCD and ‘0’ for I/O).
B/
The output type of I/O pad can also be selected by mask option MO_15PP[7..0]
O
(1 for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using
the I/O as input, “1” must be outputted before reading.
8-bit bi-directional I/O port 14 is shared with LCD segment pads SEG[23..16].
The function of the pad can be selected individually by mask options
MO_LIO14[7..0]. (‘1’ for LCD and ‘0’ for I/O).
B/
The output type of I/O pad can also be selected by mask option MO_14PP[7..0]
O
(1 for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using
the I/O as input, “1” must be outputted before reading.
3
V1.0E
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Pin Name
Pin #
PRT11[7..0] 29 ~ 36
SEG[7..0]
COM[7..0]
LC1
LC2
I/O
B/
O
37 ~ 44
45 ~ 52
53
54
55
O
O
B
B
LV1
LV2
LV3
LV4
GND
56
57
58
59
60
B
B
B
B
P
RSTP_N
61
I
FXO,
FXI
62, 63
TSTP_P
64
SXO,
SXI
65, 66
O,
I
VDD
67
P
LVF
PRTD[7..0] 68 ~ 75
March 13, 2003
I
O,
B
I
B
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HE83R125
HE80000 Series
Description
8-bit bi-directional I/O port 11 is shared with LCD segment pads SEG[15..8]. The
function of the pad can be selected individually by mask options
MO_LIO11[7..0]. (‘1’ for LCD and ‘0’ for I/O).
The output type of I/O pad can also be selected by mask option MO_11PP[7..0]
(1 for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using
the I/O as input, “1” must be outputted before reading.
LCD SEGMENT SEG[7..0] outputs.
LCD COMMON Driver pads.
Charge Pump Capacitor Pin
Charge Pump Capacitor Pin
Regulator Feedback input. The regulator output voltage can be adjusted by
the resistor between LV1 and LVF pads
LCD Charge Pump Voltage V1
LCD Charge Pump Voltage V2
LCD Charge Pump Voltage V3
LCD Charge Pump Voltage V4
Power ground Input.
System Reset input pin. Level trigger, active low on this pin will put the chip in
reset state.
External fast clock pin. Two types of oscillator can be selected by MO_FXTAL
(‘0’ for RC type and ‘1’ for crystal type). For RC type oscillator, one resistor need
to be connected between FXI and GND. For crystal oscillator, one crystal need to
be placed between FXI and FXO. Please refer to application for details.
Test input pin. Please bond this pad and reserve a test point on PCB for
debugging. But for improving ESD, please connect this point with zero Ohm
resistor to GND.
External slow clock pins. Slow clock is clock source for LCD display, TIMER1,
Time-Base and other internal blocks. Both crystal and RC oscillator are provided.
The slow clock type can be selected by mask option MO_SXTAL. Choose ‘0’ for
RC type and ‘1’ for crystal oscillator.
Positive power Input. 0.1 µF decoupling capacitors should be placed as close to
IC VDD and GND pads as possible for best decoupling effect.
8-bit bi-directional general purpose I/O port D. The output type of I/O pad can
also be selected by mask option MO_DPP[7..0] (‘1’ for push-pull and ‘0’ for
open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using
the I/O as input, ‘1’ must be outputted before reading the pin.
PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be used as external
interrupt sources.
4
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HE83R125
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HE80000 Series
4. Pad Location
P
R
T
D
[0]
P
R
T
D
[1]
P
R
T
D
[2]
P
R
T
D
[3]
P
R
T
D
[4]
P
R
T
D
[5]
P
R
T
D
[6]
P
R
T
D
[7]
V
D
D
S
X
I
S
X
O
T
S
T
P
|
P
F
X
T
F
X
O
R
S
T
P
|
N
G
N
D
L
V
4
L
V
3
LV2
VDD
LV1
LVF
PWMP
LC2
PWMN
LC1
COM[0]
GND
COM[1]
COM[2]
PRT17[7]
COM[3]
PRT17[6]
COM[4]
PRT17[5]
Product name
COM[5]
PRT17[4]
COM[6]
PRT17[3]
Die Size: 2350 µm * 3090 µm。
Substrate connect with GND。
PRT17[2]
PRT17[1]
COM[7]
SEG[0]
SEG[1]
PRT17[0]
SEG[2]
PRT15[7]
SEG[3]
PRT15[6]
SEG[4]
PRT15[5]
SEG[5]
PRT15[4]
SEG[6]
PRT15[3]
SEG[7]
P
R
T
15
[2]
March 13, 2003
P
R
T
15
[1]
P
R
T
15
[0]
P
R
T
14
[7]
P
R
T
14
[6]
P
R
T
14
[5]
P
R
T
14
[4]
P
R
T
14
[3]
P
R
T
14
[2]
P
R
T
14
[1]
5
P
R
T
14
[0]
P
R
T
11
[7]
P
R
T
11
[6]
P
R
T
11
[5]
P
R
T
11
[4]
P
R
T
11
[3]
P
R
T
11
[2]
P
R
T
11
[1]
P
R
T
11
[0]
V1.0E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
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PIN
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
PIN
Name
VDD
PWMP
PWMN
GND
PRT17[7]
PRT17[6]
PRT17[5]
PRT17[4]
PRT17[3]
PRT17[2]
PRT17[1]
PRT17[0]
PRT15[7]
PRT15[6]
PRT15[5]
PRT15[4]
PRT15[3]
PRT15[2]
PRT15[1]
PRT15[0]
PRT14[7]
PRT14[6]
PRT14[5]
PRT14[4]
PRT14[3]
PRT14[2]
PRT14[1]
PRT14[0]
PRT11[7]
PRT11[6]
PRT11[5]
PRT11[4]
PRT11[3]
PRT11[2]
PRT11[1]
PRT11[0]
SEG[7]
SEG[6]
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X
Y
PIN
PIN
Coordinate Coordinate Number Name
-1110.00
1173.40
39
SEG[5]
-1110.00
974.10
40
SEG[4]
-1110.00
699.30
41
SEG[3]
-1110.00
500.10
42
SEG[2]
-1110.00
263.10
43
SEG[1]
-1110.00
147.70
44
SEG[0]
-1110.00
32.30
45
COM[7]
-1110.00
-83.10
46
COM[6]
-1110.00
-198.50
47
COM[5]
-1110.00
-313.90
48
COM[4]
-1110.00
-429.30
49
COM[3]
-1110.00
-544.70
50
COM[2]
-1110.00
-660.10
51
COM[1]
-1110.00
-775.50
52
COM[0]
-1110.00
-890.90
53
LC1
-1110.00
-1006.30
54
LC2
-1110.00
-1121.70
55
LVF
-1076.35
-1480.00
56
LV1
-960.95
-1480.00
57
LV2
-807.55
-1480.00
58
LV3
-692.15
-1480.00
59
LV4
-576.75
-1480.00
60
GND
-461.35
-1480.00
61
RSTP_N
-345.95
-1480.00
62
FXO
-230.55
-1480.00
63
FXI
-115.15
-1480.00
64
TSTP_P
0.25
-1480.00
65
SXO
115.65
-1480.00
66
SXI
231.05
-1480.00
67
VDD
346.45
-1480.00
68
PRTD[7]
461.85
-1480.00
69
PRTD[6]
577.25
-1480.00
70
PRTD[5]
692.65
-1480.00
71
PRTD[4]
808.05
-1480.00
72
PRTD[3]
923.45
-1480.00
73
PRTD[2]
1076.85
-1480.00
74
PRTD[1]
1110.00
-1121.70
75
PRTD[0]
1110.00
-1006.30
公
司
HE83R125
HE80000 Series
X
Y
Coordinate Coordinate
1110.00
-890.90
1110.00
-775.50
1110.00
-660.10
1110.00
-544.70
1110.00
-429.30
1110.00
-313.90
1110.00
-198.50
1110.00
-83.10
1110.00
32.30
1110.00
147.70
1110.00
263.10
1110.00
378.50
1110.00
493.90
1110.00
609.30
1110.00
724.70
1110.00
840.10
1110.00
955.50
1110.00
1070.90
1110.00
1186.30
1018.00
1480.00
902.60
1480.00
787.20
1480.00
671.80
1480.00
556.40
1480.00
441.00
1480.00
325.60
1480.00
166.20
1480.00
5.05
1480.00
-110.35
1480.00
-288.90
1480.00
-404.30
1480.00
-519.70
1480.00
-635.10
1480.00
-750.50
1480.00
-865.90
1480.00
-981.30
1480.00
-1096.70
1480.00
5. LCD Power Supply
The LCD power supply is equipped with input power regulator, voltage charge pumt, and bias voltage
generating resistor network. The input power of MCU is regulated and multiplied by 4 times to generate
LCD bias for LCD driver. The regulator output voltage can be adjusted by the resistor between LV1 and
March 13, 2003
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HE83R125
HE80000 Series
LVF pads.
LV4
LV3
LV2
LV1
LVF
0.1uF
0.1uF
0.1uF
R
104
LC2
LC1
0.1uF
With the regulated LCD power, the LCD display can give steady visual effect over a wide range of
operating voltage. The built-in regulator must be enabled by mask option MO_ LVRG to function.
MO_LVRG Function
0
Disable LCD regulator
1
Enable LCD regulator
Please note that to emulate the visual effect of 1/4 bias on the ICE 3.X version the LR2 and LR3 on the
top board need be shorted.
6. LCDC Control register
LCD Control Register LCDC controls the functions of LCD driver; such as contrast level, LCD
waveform type, On/Off, Blank, etc.
LCDC
bit 7
Field
TYPE
Value
0
1
BLANK
0
1
LCDE
0
1
bit 6
-
bit 5
-
bit 4
-
bit 3
-
bit 2
TYPE
bit 1
bit 0
BLANK LCDE
Function
Select Type A LCD waveform
Select Type B LCD waveform
Normal display
LCD display blanked. LCD driver changes only COM output signal, SEG
signal remains unchanged.
LCD driver disabled, LCD driver has no output signal.
LCD driver Enabled
Please note that LCD driver must be turned off before the entering sleep mode. That means user must
clear the bit 0 of LCDC to turn off LCD driving circuit before setting bit 6 of OP1 to enter sleep mode.
Large current might happen if the procedure is not followed.
Please also note that LCD driver uses slow clock as clock source. The LCD display will not display
normally if it works in Fast clock only mode because the LCD refresh action is too fast.
March 13, 2003
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HE83R125
HE80000 Series
7. LCD RAM map
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
SEG[39..32] SEG[31..24] SEG[23..16] SEG[15..8]
F8H
F0H
E8H
E0H
F9H
F1H
E9H
E1H
FAH
F2H
EAH
E2H
FBH
F3H
EBH
E3H
FCH
F4H
ECH
E4H
FDH
F5H
EDH
E5H
FEH
F6H
EEH
E6H
FFH
F7H
EFH
E7H
SEG[7..0]
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
8. Oscillators
The MCU is equipped with two clock sources with a variety of selections on the types of oscillators to
choose from. So that system designer can select oscillator types based on the cost target, timing accuracy
requirements etc. With two clock sources available, the system can switch among operation modes of
normal, slow, idle, and sleep modes by the setting of OP1 and OP2 registers as shown in tables below to
suit the needs of application such as power saving, etc.
OP1
Field
Mode
Reset
Bit 7
1
R
1
Bit 6
STOP
R/W
0
Bit 5
SLOW
R/W
0
Bit 4
INTE
R/W
0
Bit 3
T2E
R/W
0
Bit 2
T1E
R/W
0
Bit 1
Z
R/W
-
Bit 0
C
R/W
-
OP2
Field
Mode
Reset
Bit 7
IDLE
R/W
0
Bit 6
PNWK
R/W
-
Bit 5
TCWK
R/W
-
Bit 4
0
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Crystal, Resonator or the RC oscillator or internal RC can be used as fast clock source. If the internal RC
oscillator is used, then no external component is necessary. Please note that oscillation frequency of
internal RC oscillator may vary with parameters of IC fabrication process. Therefore if timing accuracy is
essential in targeted applications, then internal RC is not recommended.
Name
MO_FOSCE
Value
0
1
MO_FRCI_S[2:0] 000
001
010
011
100
March 13, 2003
Function
Internal fast OSC
External fast OSC
RFRC_I ~= 500k
RFRC_I ~= 1M
RFRC_I ~= 1.5M
RFRC_I ~= 2M
RFRC_I ~= 2.5M
8
V1.0E
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HE83R125
HE80000 Series
101 RFRC_I ~= 3M
110 RFRC_I ~= 3.5M
111 RFRC_I ~= 4M
When Crystal oscillator or external RC are used, components should be placed as close to the pins as
possible. The type of oscillator used is selected by mask option MO_FXTAL.
MO_FXTAL Fast clock type
0
RC Oscillator.
1
Crystal Oscillator.
VDD
FXI
R
FXI
C
FXO
Two types of oscillator, crystal and RC, can be used as slow clock by mask option MO_SXTAL. If used
in for time keeping function or other applications that required the accurate timing, crystal oscillator is
recommended. If the timing accuracy is not important, then RC type oscillator can be used to reduce cost.
MO_SXTAL
0
1
Slow clock type
RC oscillator
Crystal oscillator
SXI
SXI
SXO
SXO
Crystal Osc.
RC Osc.
If the dual clock mode is used, the LCD display, Timer1 and Timer Base will derive its clock source from
slow clock while the other blocks will operate with the fast clock.
9. General Purpose I/O
There is one dedicated general purpose I/O port PRTD. All the I/O Ports are bi-directional and of
non-tri-state output structure. The output has weak sourcing (50 µA) and stronger sinking (1 mA)
capability and each can be configured as push-pull or open-drain output structure individually by mask
March 13, 2003
9
V1.0E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
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公
HE83R125
司
HE80000 Series
option. The input port has built-in Schmidt trigger to prevent it from chattering. The hysteresis level of
Schmidt trigger is 1/3 VDD.
MO_DPP[7..0] Output Structure
0
Open-drain output
1
Push-pull output
When the I/O port is used as input, the weakly high sourcing PMOS can be used as pull-up. Open drain
can be used if the pull-up is not required and let the external driver to drive the pin. Please note that a
floating pad could cause more power consumption since the noise could interfere with the circuit and
cause the input to toggle. A ‘1’ needs to be written to port first before reading the input data from the I/O
pin, otherwise, the pin will always be stuck at ‘0’. If the PMOS is used as pull-up, care should be taken to
avoid the constant power drain by DC path between pull-up and external circuit.
VDD
DOUT
VDD
Q
LATCH
Q'
MO_?PP
PAD
DIN
SCHMIDT Trigger input
PRT11[7..0], PRT14[7..0], PRT15[7..0] and PRT17[7..0] share pads with SEG[8..39]. The function of the
pins is selected by mask option MO_LIO11, MO_LIO14, MO_LIO15, MO_LIO17 respectively as shown
in the following figure.
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PRT110
PRT111
PRT112
PRT113
PRT114
PRT115
PRT116
PRT117
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
PRT150
PRT151
PRT152
PRT153
PRT154
PRT155
PRT156
PRT157
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
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有
MO_LIO11=0
MO_LIO11=1
PRT110
PRT111
PRT112
PRT113
PRT114
PRT115
PRT116
PRT117
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
MO_LIO14=0
MO_LIO14=1
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
MO_LIO15=0
MO_LIO15=1
PRT150
PRT151
PRT152
PRT153
PRT154
PRT155
PRT156
PRT157
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
MO_LIO17=0
MO_LIO17=1
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
限
公
司
HE83R125
HE80000 Series
10. Timer1
The Timer1 consists of two 8-bit write-only preload registers T1H and T1L and 16-bit down counter. If
Timer1 is enabled, the counter will decrement by one with each incoming clock pulse. Timer1 interrupt
will be generated when the counter underflows - counts down to FFFFH. And the counter will be
automatically reloaded with the value of T1H and T1L.
The clock source of Timer1 is derived from slow clock “SCK” at dual clock or slow clock only mode.
And it comes from the fast clock “FCK” at fast clock only mode.
Please note that the interrupt is generated when counter counts from 0000H to FFFFH. If the value of
T1H and T1L is N, and count down to FFFFH, the total count is N+1. The content of counter is zero
when system resets. Once it is enabled to count at this moment, interrupt will be generated immediately
and value of T1H and T1L will be loaded since it counts to FFFFH. So the T1H and T1L value should be
set before enabling Timer1.
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The contents of T1H and
T1L almost loaded into
Timer1 immediately
when Timer1 is turned on
after reset.
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T1H
有
T1L
限
公
司
HE83R125
HE80000 Series
Auto reload when
Timer1 underflow
"Timer1 Counter"
decreases 1
No
Count TO
0xFFFFh
Start Timer1
Interrupt Request.
Yes
T1_INT
The Timer1 related control registers are list as below:
Register Address
Field
Bit position Mode
Description
0x02
TC1_IER
2
R/W 0: TC1 interrupt is disabled. (default)
IER
1: TC1 interrupt is enabled.
0x03
T1L[7:0]
7~0
W Low byte of TC1 pre-load value
T1L
0x04
T1H[7:0]
7~0
W High byte of TC1 pre-load value
T1H
0x09
TC1E
2
R/W
0: TC1 is disabled. (default)
OP1
1: TC1 is enabled.
11. Timer2
Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock
“FSYS”/1.5. The system clock “FSYS” varies depending on the operation modes of the MCU.
The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If
Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will
March 13, 2003
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HE80000 Series
be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded
with the value of T2H and T2L.
Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value
of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when
system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and
value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value
should be set before enabling Timer2.
The contents of T2H and
T2L almost loaded into
Timer2 immediately
when Timer2 is turned on
after reset.
T2H
T2L
Auto reload when
Timer2 underflow
"Timer2 Counter"
decreases 1
No
Count TO
0xFFFFh
Yes
Start Timer2
Interrupt Request.
T2_INT
The Timer2 related control registers are list as below:
Register Address
Field
Bit position Mode
Description
0x02
TC2_IER
1
R/W 0: TC2 interrupt is disabled. (default)
IER
1: TC2 interrupt is enabled.
0x05
T2L[7:0]
7~0
W Low byte of TC2 pre-load value
T2L
0x06
T2H[7:0]
7~0
W High byte of TC2 pre-load value
T2H
0x09
TC2E
3
R/W 0: TC2 is disabled. (default)
OP1
1: TC2 is enabled.
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HE80000 Series
12. Watch Dog Timer
Watch Dog Timer (WDT) is designed to reset system automatically prevent system dead lock caused by
abnormal hardware activities or program execution.
WDT needs to be enabled in Mask Option.
MO_WDTE Function
0
WDT disable
1
WDT enable
To use WDT function, “CLRWDT” instruction needs to be executed in every possible program path
when the program runs normally in order to clears the WDT counter before it overflows, so that the
program can operate normally. When abnormal conditions happen to cause the MCU to divert from
normal path, the WDT counter will not be cleared and reset signal will be generated.
WDT is the enabling signal generated by calculating 32768-clock overflow. Reset Register content is
same as TC1 (Timer1 clock), which uses the same clock count source. WDT function can be generated in
Normal, Slow and Idle Mode.
However, WDT will not function during Sleep Mode (as the TC1 clock
has stopped.)
13. Pulse-Width Modulation
The pulse-width modulator (PWM) converts 7-bit unsigned speech data written to PWMC data register to
proportional duty cycle of PWM output. PWM module shares the PWMC data register with
Digit-to-Analog Converter. So PWM and DA output can exist at the same time. When PWM circuit is
enabled, it generates signal with duty ratio in proportion to the DA value.
DA = 0x20
DA = 0x80
DA = 0xE0
1 subframe
The PWM bit of VOC register controls register to enable the circuit and output driver. When PWM bit of
VOC is ‘0’, PWME bit and output drivers settings are both cleared. To use PWM for voice output, PWM
bit has to be set to ‘1’ first, then set PWME bit and enable output driver by setting the driver number. If
PWM bit is disabled and enabled again, the setting for driver and PWME bit will be clear.
March 13, 2003
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V1.0E
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HE83R125
HE80000 Series
The Fast Clock is gated through PWME bit of PWMC command register to provide the clock source of
PWM circuit when it is enabled. As PWM needs higher frequency to operate, it cannot generate correct
PWM signal in Slow clock only mode.
When the program enters into Sleep mode or Idle mode, it will automatically turn off all voice outputs by
clearing VOC[2..1] to ”00”. To activate voice output again when returning to Normal Mode, the VOC
register needs to be set again.
The PWM output volume can be adjusted by command register PWMC[6..4]. The bit 6 and 5 control 2
time driver, while bit 4 controls 1 time driver, thus it has 5 levels of driver output. By turning on/off the
internal drivers, the sound level of PWM output can be turned up and down. Please note that this
adjustment apply only to PWM, but not DA output.
PWM output driver selection
PWMC[6..4] Number of Driver
000
off
001
1
010
2
011
3
100
2
101
3
110
4
111
5
14. Summary of Registers and Mask Options
All the registers and mask options used in this chip are listed in the following tables.
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0ah
0bh
0dh
oeh
oeh
0fh
11h
13h
14h
15h
16h
17h
NAME
TPL
TPH
IER
T1L
T1H
T2L
T2H
SP
DP
OP9
OPA
PP
PRTD
PWMC
PWMC
LCDC
PRT11
VOC
PRT14
PRT15
TPP
PRT17
March 13, 2003
Field
table pointer high byte
table pointer low byte
INT1
T1
T2
Timer 1 low byte
Timer 1 high byte
Timer 2 low byte
Timer 2 high byte
stack pointer
data RAM pointer
DRDY
STOP
SLOW
INTE
T2E
T1E
Z
IDLE
PNWK TCWK
RAM page pointer
I/O port D
1
PWM O/P driver
0
7-bit DA and PWM output data
TYPE BLANK
I/O port 11
PWM
DAC
I/O port 14
I/O port 15
ROM table page pointer
I/O port 17
15
Mode
W
W
INT2
R/W
W
W
W
W
R/W
R/W
C
R/W
R/W
R/W
R/W
PWME
W
W
LCDE
W
R/W
OP
W
R/W
R/W
W
R/W
RESET
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
1111 1111
xxxx xxxx
1000 00xx
0xx- ---0000 0000
1111 1111
x000 xxxx
xxxx xxxx
xx1x xx10
1111 1111
---- -000
0000 0011
0000 0011
0000 0000
1111 1111
V1.0E
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HE83R125
HE80000 Series
Mask Options:
NAME
MO_PORE
MO_FOSCE
MO_FXTAL
MO_FRCI_S[2:0]
MO_SXTAL
MO_FCK/SCKN
MO_WDTE
MO_CPP[7:0]
MO_DPP[7:0]
MO_11PP[7:0]
MO_14PP[1:0]
MO_15PP[1:0]
MO_17PP[7:0]
MO_LIO11[1:0]
MO_LIO14[7:0]
MO_LIO15[1:0]
MO_LIO17[7:0]
MO_LVRG
VALUE
0
1
0
1
0
1
000
001
010
011
100
101
110
111
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
NOTE
power-on reset disable
power-on reset enable
internal fast OSC
external fast OSC, use it now
R/C oscillator For fast clock
Crystal oscillator For fast clock
RFRC_I ~= 500k
RFRC_I ~= 1M
RFRC_I ~= 1.5M
RFRC_I ~= 2M
RFRC_I ~= 2.5M
RFRC_I ~= 3M
RFRC_I ~= 3.5M
RFRC_I ~= 4M
R/C oscillator For 32k clock
Crystal oscillator For 32k clock
slow clock only
illegal
dual clock
fast clock only
WDT disable
WDT enable
open-drain output
push-pull output
open-drain output
push-pull output
open-drain output
push-pull output
open-drain output
push-pull output
open-drain output
push-pull output
open-drain output
push-pull output
IO pin
LCD pin
IO pin
LCD pin
IO pin
LCD pin
IO pin
LCD pin
LCD regulator disable
LCD regulator enable
15. Absolute Maximum Rating
Item
Supply Voltage
Input Voltage
March 13, 2003
Sym.
Rating
Condition
VDD
-0.5V ~ 8V
VIN -0.5V ~ VDD +0.5V
16
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Output Voltage
Operating Temperature
Storage Temperature
子
VO
TOP
TST
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有
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公
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HE83R125
HE80000 Series
-0.5V ~ VDD +0.5V
0°C ~ 70°C
-50°C ~ 100°C
16. Recommended Operating Conditions
Item
Supply Voltage
Input Voltage
Operating Frequency
Operating Temperature
Storage Temperature
Sym.
Rating
VDD
2.4V ~ 5.5V
VIH 0.9 VDD ~ VDD
VIL 0.0V ~ 0.1 VDD
FMAX
8MHz
4MHz
0
TOP
0 C ~ 700C
TST -500C ~ 1000C
Condition
VDD =5.0V
VDD =2.4V
17. AC/DC Characteristics
Test Condition: Temp. = 25℃, VDD = 3V±10%, GND=0V
PARAMETER
Symbol MIN TYP MAX UNIT
Normal mode current
Slow mode current
Idle mode current
Additional current if LCD
ON
Sleep mode current
Input high voltage
Input Low Voltage
IFAST
ISLOW
IIDLE
Input Hysteresis Width
VHYS
Output source current
Output sink current
Input Low Current
Input Low Current
IOH
IOL1
IIL2
IIL1
PWM Output Current
IPWM
0.75
10
6
12
ILCD
ISLEEP
VIH
VIL
mA
µA
µA
µA
1
µA
VDD Input pins
VDD Input pins
I/O, RSTP_N, Threshold=2/3VDD(input
from low to high)
VDD
Threshold=1/3VDD(input from high to
low)
µA Output drive high*1, VOH =2.0V
mA Output drive low, VOL= 0.4V
µA I/O, VIL= GND, pull high Internally
µA RSTP_N, VIL= GND, pull high Internally
mA PWM *2 With 32Ω Loading
mA With 64Ω Loading
mA With 100Ω Loading
0.8
0.2
1/3
50
1.0
10
6
4
CONDITION
1
20
10
20
100
20
14
8
5
2M ext. R/C
32768 Hz, LCD Disabled
32768 Hz, LCD Disabled
LCD Enabled, regulator on
Note:
1.
Source current spec. applies to Push-Pull I/O port only
2.
This spec. is based on one driver only. There are totally five drivers, so user must multiply the number of driver actually
used to get the total amount of current. ( IPWM x N; N=0,1,2,3,4,5)
March 13, 2003
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HE83R125
HE80000 Series
18. Application Circuit
VDD
VDD
1
33p
33p
0
32768Hz
+
22p
Y6
22p
R
4MHz
VDD
47uF
0.47uF
2
3.0V
Y2
PRTD0
PRTD1
PRTD2
PRTD3
PRTD4
PRTD5
PRTD6
PRTD7
VDD
SXI
SXO
TSTP
FXI
FXO
RSTP
GND
LV4
LV3
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
LV3
LV4
RESET
FXO
FXI
SXO
SXI
PRTD7
PRTD6
PRTD5
PRTD4
PRTD3
PRTD2
PRTD1
PRTD0
0.1uF
VDD
1
PWMP
2
PWMN
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
LV2
LV1
LVF
LC2
LC1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
PWMP
PWMN
GND
PRT177
PRT176
PRT175
PRT174
PRT173
PRT172
PRT171
PRT170
PRT157
PRT156
PRT155
PRT154
PRT153
HE83R125
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
0.1uF
0.1uF
0.1uF
104
R
0.1uF
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PRT152
PRT151
PRT150
PRT147
PRT146
PRT145
PRT144
PRT143
PRT142
PRT141
PRT140
PRT117
PRT116
PRT115
PRT114
PRT113
PRT112
PRT111
PRT110
PRT177
PRT176
PRT175
PRT174
PRT173
PRT172
PRT171
PRT170
PRT157
PRT156
PRT155
PRT154
PRT153
VDD
LV4
LV3
LV2
LV1
LVF
LC2
LC1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
PRT110
PRT111
PRT112
PRT113
PRT114
PRT115
PRT116
PRT117
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
PRT150
PRT151
PRT152
March 13, 2003
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