ETC HE84770(S)

King Billion Electronics Co., Ltd
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HE84770
HE80000 SERIES
- Table of Contents 1.
General Description ___________________________________________________________________2
2.
Features _____________________________________________________________________________2
3.
Functional Block Diagram ______________________________________________________________3
4.
Pin Description _______________________________________________________________________3
5.
LCD RAM Map ______________________________________________________________________5
6.
LCD Power Supply ____________________________________________________________________8
6.1.
LCDC Control register _____________________________________________________________10
7.
Oscillators __________________________________________________________________________10
8.
General Purpose I/O__________________________________________________________________12
9.
Key Scan Circuit _____________________________________________________________________13
10.
Timer1 ___________________________________________________________________________15
11.
Timer2 ___________________________________________________________________________16
12.
Time Base Interrupt________________________________________________________________18
13.
Watch Dog Timer __________________________________________________________________18
14.
Digital-to-Analog Converter _________________________________________________________19
15.
Pulse-Width Modulation ____________________________________________________________20
16.
Absolute Maximum Rating __________________________________________________________21
17.
Recommended Operating Conditions _________________________________________________21
18.
AC/DC Characteristics _____________________________________________________________21
19.
Application Circuit_________________________________________________________________23
20.
Important Note ____________________________________________________________________24
21.
Updated Record ___________________________________________________________________25
August 25, 2003
Page 1 of 26
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King Billion Electronics Co., Ltd
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HE84770
HE80000 SERIES
1. General Description
HE84770 is a member of 8-bit Micro-controller series developed by King Billion Electronics. Four LCD
driver configurations, 32 COM x 128 SEG, 48 COM x 112 SEG, 64 COM x 96 SEG or 80 COM x 80
SEG are available by mask option. 24 LCD segment driver pins are multiplexed with I/O pins to provide
flexibility of wide variety of combinations to suit the needs of applications. The built-in LCD power
supply is equipped with voltage charge-pump circuit to generate the high voltage required by the high
duty LCD driver, bias voltage generating circuit and input voltage regulator circuit to supply stable LCD
display effect over the wide battery life. The built-in OP comparator can be used with (light, voice,
temperature, humility) sensor and used as battery low detection. 7-bit current-type D/A converter and
PWM device provide the complete speech output mechanism. The 2 MB ROM can be used in the storage
of speech, graphic, text, etc. It is ideal for applications such as Translator, Data Bank, Educational Toy,
Digital Voice Recording System, etc.
The instruction set of HE80000 series is easy to learn and simple to use. Only 32 instructions with four
addressing modes are provided. Most of instructions take only 3 oscillator clocks to execute. The
processing power is enough to most of battery operation system.
2. Features
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Operation Voltage:
System Clock:
2.4V ~ 3.6V
DC ~ 8MHz @ 3.6V
DC ~ 4MHz @ 2.4V
Internal ROM:
2 MB (256 KB Program ROM + 1792 KB Data ROM)
Internal RAM:
16 KB
Dual Clock System: Fast clock:
32768 ~ 8M Hz (No Internal Clock)
Slow clock: 32768 Hz
Operation Mode:
Fast, Slow, Idle and Sleep modes.
24 ~ 48 bit bi-directional general purpose I/O port with push-pull or Open-Drain output type
selectable for each I/O pin by mask option. 24 of them are multiplexed with LCD segment
pins.
Built-in 4x20 hardware keyboard scan circuit (multiplexed with LCD SEG pin) helps to
reduce the pin counts as well as the firmware effort.
Voltage Detector with two detecting thresholds.
Four LCD configurations: 32 COM x 128 SEG, 48 COM x 112 SEG, 64 COM x 96 SEG or
80 COM x 80 SEG. All of LCD configurations are B TYPE.
Built-in LCD power supply with input voltage regulator, x3, x4, x5 voltage multiplier and
bias voltage generating circuit.
One 7-bit current-type DAC output.
Single-ended Pulse Width Modulation circuit for alternative voice output.
Built-in OP comparator.
Two 16-bit timers and one Time-Base timer.
Watch Dog Timer to prevent deadlock condition.
Two external interrupts and three internal timer interrupts.
Instruction set: 32 instructions with 4 addressing modes.
August 25, 2003
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HE84770
HE80000 SERIES
3. Functional Block Diagram
SEG
COM
LCD
Driver
LCD Power
Supply
8 Bit CPU
2 MB ROM
Fast Clock
OSC.
Slow Clock
OSC
FXI, FXO
SXI, SXO
16 KB RAM
PRTC, PRTD, PRT10,
PRT17
SGKY[43..24]
I/O Port
Key Scan
TC1
TC2
PWM
PWM
DAC
VO, DAO
TBI
WDT
OP Amp
OPO,OPIN, OPIP
SEG48
SEG47
SEG46
SEG45
SEG44
SGKY 43
SGKY 42
SGKY 41
SGKY 40
SGKY 39
SGKY 38
SGKY 37
SGKY 36
SGKY 35
SGKY 34
SGKY 33
SGKY 32
SGKY 31
SGKY 30
SGKY 29
SGKY 28
SGKY 27
SGKY 26
SGKY 25
SGKY 24
PRT147
PRT146
PRT145
PRT144
HE84770
VDD_RAM
PRTC0
PRTC1
PRTC2
PRTC3
PRTC4
PRTC5
PRTC6
PRTC7
PWM
GND_PWM
PRTD0
PRTD1
PRTD2
PRTD3
PRTD4
PRTD5
PRTD6
PRTD7
PRT100
PRT101
PRT102
PRT103
PRT104
PRT105
PRT106
PRT107
VDD
SXI
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
PRT143
PRT142
PRT141
PRT140
PRT157
PRT156
PRT155
PRT154
PRT153
PRT152
PRT151
PRT150
PRT177
PRT176
PRT175
PRT174
PRT173
PRT172
PRT171
PRT170
COM31
COM30
COM29
COM28
COM27
COM26
COM25
C0M24
C0M23
C0M22
C0M21
C0M20
C0M19
C0M18
C0M17
C0M16
C0M15
C0M14
C0M13
C0M12
C0M11
C0M10
C0M9
C0M8
C0M7
C0M6
C0M5
C0M4
C0M3
COM2
COM1
COM0
LVL1
LVL2
LVL3
LVL4
LVL5
LGS2
LVP
LCAP4A
LCAP2B
LCAP2A
LCAP1A
LCAP1B
LCAP3A
LVREG
LGS1
LVAG
GND
VO
DAO
OPIN
OPIP
OPO
RSTP_N
FXO
FXI
TSTP_P
SXO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
CMSG79
CMSG78
CMSG77
CMSG76
CMSG75
CMSG74
CMSG73
CMSG72
CMSG71
CMSG70
CMSG69
CMSG68
CMSG67
CMSG66
CMSG65
CMSG64
CMSG63
CMSG62
CMSG61
CMSG60
CMSG59
CMSG58
CMSG57
CMSG56
CMSG55
CMSG54
CMSG53
CMSG52
CMSG51
CMSG50
CMSG49
CMSG48
CMSG47
CMSG46
CMSG45
CMSG44
CMSG43
CMSG42
CMSG41
CMSG40
CMSG39
CMSG38
CMSG37
CMSG36
CMSG35
CMSG34
CMSG33
CMSG32
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
4. Pin Description
Pin Name
Pin # I/O
Description
186~216
SEG[79..44]
O LCD segment SEG[79..44] driver outputs.
,1~5
LCD segments share pads with key scan out SCNO[19..0]. The key scan function of
SGKY[43..24] 6 ~ 25 O these pins can be disabled by mask option clearing MO_LCDKEY to ‘0’, then
SGKY[43..24] function as LCD segment driver only. Setting MO_LCDKEY to ‘1’
August 25, 2003
Page 3 of 26
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Pin Name
Pin # I/O
PRT14[7..0]/
SEG[23:16]
26 ~ 33
B/
O
PRT15[7..0]/
SEG[15:8]
34 ~ 41
B/
O
PRT17[7..0]/
SEG[7:0]
42 ~ 49
B/
O
COM[31..0]
LVL1
LVL2
LVL3
LVL4
LVL5
LGS2
LVP
LCAP4A
LCAP2B
LCAP2A
LCAP1A
LCAP1B
LCAP3A
50 ~ 81
82
83
84
85
86
87
88
89
90
91
92
93
94
O
P
P
P
P
P
I
P
O
O
O
O
O
O
LVREG
95
O
LGS1
LVAG
GND
96
97
98
I
O
P
VO
99
O
DAO
100
O
OPIN
101
I
OPIP
OPO
102
103
I
O
RSTP_N
104
I
FXO,
105, 106 O,
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HE84770
HE80000 SERIES
Description
will turn on the key scan function.
8-bit bi-directional I/O port 14 is shared with LCD segment pads SEG[23..16]. The
function of the pad can be selected individually by mask options MO_LIO14[7..0].
(‘1’ for LCD and ‘0’ for I/O).
The output type of I/O pad can also be selected by mask option MO_14PP[7..0] (1 for
push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, “1” must be outputted before reading.
8-bit bi-directional I/O port 15 is shared with LCD segment pads SEG[15..8]. The
function of the pad can be selected individually by mask options MO_LIO15[7..0].
(‘1’ for LCD and ‘0’ for I/O).
The output type of I/O pad can also be selected by mask option MO_15PP[7..0] (1 for
push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, “1” must be outputted before reading.
8-bit bi-directional I/O port 17 is shared with LCD segment pads SEG[7..0]. The
function of the pad can be selected individually by mask options MO_LIO17[7..0].
(‘1’ for LCD and ‘0’ for I/O).
The output type of I/O pad can also be selected by mask option MO_17PP[7..0] (1 for
push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, “1” must be outputted before reading.
LCD COMMON Driver pads.
LCD Bias Voltage 1.
LCD Bias Voltage 2
LCD Bias Voltage 3
LCD Bias Voltage 4
LCD Bias Voltage 5.
LCD Drive Voltage Setting
Charge Pump Output..
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns
pumped to LVP. Adjust resistor between LGS1 and LVREG to set LVREG voltage.
Regulator Voltage Setting
Reference Voltage Output. Fixed 0.9 Volt DC reference voltage
Power ground Input.
DAC Voice Output. Set the bit 1 and clear the bit 0 of VOC (DA = ‘1’ and OP = ‘0’)
register to turn on DAC with VO output.
Alternate output of DAC. Set both bit 1 and bit 0 of VOC register (DA = ‘1’ and OP =
‘1’) to turn on DAC with DAO output as well as OP comparator.
Inverting input of OP Amp. Set the bit 0 of VOC register (OP = ‘1’) to turn on OP
comparator.
Non-inverting input of OP Amp.
Output of OP Amp.
System Reset input pin. Level trigger, active low on this pin will put the chip in reset
state.
External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (‘0’
Page 4 of 26
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HE84770
HE80000 SERIES
Pin Name
FXI
Pin # I/O
Description
B for RC type and ‘1’ for crystal type). For RC type oscillator, one resistor need to be
connected between FXI and GND. For crystal oscillator, one crystal need to be placed
between FXI and FXO. Please refer to application circuit for details.
Test input pin. Please bond this pad and reserve a test point on PCB for debugging.
TSTP_P
107
I
But for improving ESD, please connect this point with zero Ohm resistor to GND.
External slow clock pins. Slow clock is clock source for LCD display, TIMER1,
O, Time-Base and other internal blocks. Both crystal and RC oscillator are provided. The
SXO,
108, 109
I slow clock type can be selected by mask option MO_SXTAL. Choose ‘0’ for RC type
SXI
and ‘1’ for crystal oscillator.
Positive power Input. 0.1 µF decoupling capacitors should be placed as close to IC
VDD
110
P
VDD and GND pads as possible for best decoupling effect.
8-bit bi-directional I/O port 10. The output type of I/O pad can be selected by mask
option MO_10PP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
111 ~
B
PRT10[7..0]
118
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
pad as input pad, “1” must be outputted before reading.
8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by
mask option MO_DPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
119 ~
B
PRTD[7..0]
126
as input, ‘1’ must be outputted before reading the pin.
PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt
sources.
GND_PWM 127
O Dedicated Ground for PWM output.
The PWM output can drive speaker or buzzer directly. Set the bit2 of VOC register as
PWM
128
O
one to turn on PWM. Using VDD & PWM to drive output device.
8-bit bi-directional I/O port C. PRTC[7:4] is shared with Key Scan Dedicated Input
SCNI[3:0]. The Key Scan function can be disabled by clearing MO_LCDKEY mask
option to ‘0’.
129 ~
PRTC[7..0]
B The output type of I/O pad can also be selected by mask option MO_CPP[7..0] (‘1’
136
for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, ‘1’ must be outputted before reading the pin.
VDD_RAM 137
P Dedicated power input for RAM
COM[32..79] pads are shared with SEG[127..80] outputs. The functions of the pads to
138 ~
CMSG[32..79]
O be COM drivers or SEG drivers can be selected by mask option MO_COM[0]. Please
185
refer to LCD driver configuration for details.
I: Input, O: Output, B: Bidirectional, P: Power.
5. LCD RAM Map
There are 4 LCD configurations as determined by mask option MO_COM[1..0]. The functions of
CMSG[79..32] are different in each configuration as listed in the following table.
MO_COM[1..0] Configuration CMSG[79..64] CMSG[63..48] CMSG[47..32]
00
32 x 128 SEG[80..95] SEG[96..111] SEG[112..127]
01
48 x 112 SEG[80..95] SEG[96..111] COM[47..32]
10
64 x 96
SEG[80..95] COM[63..48] COM[47..32]
11
80 x 80
COM[79..64] COM[63..48] COM[47..32]
August 25, 2003
Page 5 of 26
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COMXSEG
CMSG32
CMSG33
CMSG34
CMSG35
CMSG36
CMSG37
CMSG38
CMSG39
CMSG40
CMSG41
CMSG42
CMSG43
CMSG44
CMSG45
CMSG46
CMSG47
CMSG48
CMSG49
CMSG50
CMSG51
CMSG52
CMSG53
CMSG54
CMSG55
CMSG56
CMSG57
CMSG58
CMSG59
CMSG60
CMSG61
CMSG62
CMSG63
CMSG64
CMSG65
CMSG66
CMSG67
CMSG68
CMSG69
CMSG70
CMSG71
CMSG72
CMSG73
CMSG74
CMSG75
CMSG76
CMSG77
CMSG78
CMSG79
電
子
32X128
SEG127
SEG126
SEG125
SEG124
SEG123
SEG122
SEG121
SEG120
SEG119
SEG118
SEG117
SEG116
SEG115
SEG114
SEG113
SEG112
SEG111
SEG110
SEG109
SEG108
SEG107
SEG106
SEG105
SEG104
SEG103
SEG102
SEG101
SEG100
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
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48X112
64X96
80X80
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
SEG111
SEG110
SEG109
SEG108
SEG107
SEG106
SEG105
SEG104
SEG103
SEG102
SEG101
SEG100
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
HE84770
HE80000 SERIES
The RAM Maps of all four different LCD configurations are as the following:
32 COM:
Page
7
COM0
COM1
:
COM15
COM16
:
COM30
COM31
Page
6
COM0
COM1
:
COM15
COM16
SEG
[7:0]
7E0H
7E1H
:
7EFH
7F0H
:
7FEH
7FFH
SEG
[71:64]
6E0H
6E1H
:
6EFH
6F0H
August 25, 2003
SEG
[15:8]
7C0H
7C1H
:
7CFH
7D0H
:
7DEH
7DFH
SEG
[79:72]
6C0H
6C1H
:
6CFH
6D0H
SEG
[23:16]
7A0H
7A1H
:
7AFH
7B0H
:
7BEH
7BFH
SEG
[87:80]
6A0H
6A1H
:
6AFH
6B0H
SEG
[31:24]
780H
781H
:
78FH
790H
:
79EH
79FH
SEG
[95:88]
680H
681H
:
68FH
690H
Page 6 of 26
SEG
SEG
SEG
SEG
[39:32]
[47:40]
[55:48]
[63:56]
760H
740H
720H
700H
761H
741H
721H
701H
:
:
:
:
76FH
74FH
72FH
70FH
770H
750H
730H
710H
:
:
:
:
77EH
75EH
73EH
71EH
77FH
75FH
73FH
71FH
SEG
SEG
SEG
SEG
[103:96] [111:104] [119:112] [127:120]
660H
640H
620H
600H
661H
641H
621H
601H
:
:
:
:
66FH
64FH
62FH
60FH
670H
650H
630H
610H
V2.6E
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:
COM30
COM31
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HE84770
HE80000 SERIES
48 COM：
Page 7,6
COM0
COM1
:
COM15
COM16
:
COM31
COM32
:
COM46
COM47
SEG[7:0]
7C0H
7C1H
:
7CFH
7D0H
:
7DFH
7E0H
:
7EEH
7EFH
SEG[15:8] SEG[23:16] SEG[31:24] SEG[39:32] SEG[47:40] SEG[55:48]
780H
740H
700H
6C0H
680H
640H
781H
741H
701H
6C1H
681H
641h
:
:
:
:
:
:
78FH
74FH
70FH
6CFH
68FH
64FH
790H
750H
710H
6D0H
690H
650H
:
:
:
:
:
:
79FH
75FH
71FH
6DFH
69FH
65FH
7A0H
760H
720H
6E0H
6A0H
660H
:
:
:
:
:
:
7AEH
76EH
72EH
6EEH
6AEH
66EH
7AFH
76FH
72FH
6EFH
6AFH
66FH
Page
6, 5, 4
COM0
COM1
:
COM15
COM16
:
COM31
COM32
:
COM46
COM47
SEG
[63:56]
600H
601H
:
60FH
610H
:
61FH
620H
:
62EH
62FH
August 25, 2003
SEG[7:0]
7C0H
7C1H
:
7CFH
7D0H
:
7DFH
7E0H
:
7EFH
7F0H
:
7FEH
7FFH
SEG
[79:72]
580H
581H
:
58FH
590H
:
59FH
5A0H
:
5AEH
5AFH
SEG[15:8]
780H
781H
:
78FH
790H
:
79FH
7A0H
:
7AFH
7B0H
:
7BEH
7BFH
:
67EH
67FH
公
:
6DEH
6DFH
64 COM：
Page 7,6
COM0
COM1
:
COM15
COM16
:
COM31
COM32
:
COM47
COM48
:
COM62
COM63
:
69EH
69FH
有
:
6FEH
6FFH
SEG
[71:64]
5C0H
5C1H
:
5CFH
5D0H
:
5DFH
5E0H
:
5EEH
5EFH
:
6BEH
6BFH
份
SEG
[87:80]
540H
541h
:
54FH
550H
:
55FH
560H
:
56EH
56FH
SEG[23:16]
740H
741H
:
74FH
750H
:
75FH
760H
:
76FH
770H
:
77EH
77FH
Page 7 of 26
:
65EH
65FH
SEG
[95:88]
500H
501H
:
50FH
510H
:
51FH
520H
:
52EH
52FH
SEG[31:24]
700H
701H
:
70FH
710H
:
71FH
720H
:
72FH
730H
:
73EH
73FH
:
63EH
63FH
SEG
[103:96]
4C0H
4C1H
:
4CFH
4D0H
:
4DFH
4E0H
:
4EEH
4EFH
SEG[39:32]
6C0H
6C1H
:
6CFH
6D0H
:
6DFH
6E0H
:
6EFH
6F0H
:
6FEH
6FFH
:
61EH
61FH
SEG
[111:104]
480H
481H
:
48FH
490H
:
49FH
4A0H
:
4AEH
4AFH
SEG[47:40]
680H
681H
:
68FH
690H
:
69FH
6A0H
:
6AFH
6B0H
:
6BEH
6BFH
V2.6E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
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Page 6, 5
COM0
COM1
:
COM15
COM16
:
COM31
COM32
:
COM47
COM48
:
COM62
COM63
SEG[55:48]
640H
641H
:
64FH
650H
:
65FH
660H
:
66FH
670H
:
67EH
67FH
80 COM：
Page
SEG
7:3
[7:0]
COM0 780H
COM1 781H
:
:
COM15 78FH
COM16 790H
:
:
COM31 79FH
COM32 7A0H
:
:
COM47 7AFH
COM48 7B0H
:
:
COM62 7BFH
COM63 7C0H
:
:
COM78 7CEH
COM79 7CFH
SEG
[15:8]
700H
701H
:
70FH
710H
:
71FH
720H
:
72FH
730H
:
73FH
740H
:
74EH
74FH
億
電
子
SEG[63:56]
600H
601H
:
60FH
610H
:
61FH
620H
:
62FH
630H
:
63EH
63FH
股
份
SEG[71:64]
5C0H
5C1H
:
5CFH
5D0H
:
5DFH
5E0H
:
5EFH
5F0H
:
5FEH
5FFH
有
限
公
SEG[79:72]
580H
581H
:
58FH
590H
:
59FH
5A0H
:
5AFH
5B0H
:
5BEH
5BFH
司
HE84770
HE80000 SERIES
SEG[87:80]
540H
541H
:
54FH
550H
:
55FH
560H
:
56FH
570H
:
57EH
57FH
SEG[95:88]
500H
501H
:
50FH
510H
:
51FH
520H
:
52FH
530H
:
53EH
53FH
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
[23:16] [31:24] [39:32] [47:40] [55:48] [63:56] [71:64] [79:72]
680H
600H
580H
500H
480H
400H
380H
300H
681H
601H
581H
501H
481H
401H
381H
301H
:
:
:
:
:
:
:
:
68FH
60FH
58FH
50FH
48FH
40FH
38FH
30FH
690H
610H
590H
510H
490H
410H
390H
310H
:
:
:
:
:
:
:
:
69FH
61FH
59FH
51FH
49FH
41FH
39FH
31FH
6A0H
620H
5A0H
520H
4A0H
420H
3A0H
320H
:
:
:
:
:
:
:
:
6AFH
62FH
5AFH
52FH
4AFH
42FH
3AFH 32FH
6B0H
630H
5B0H
530H
4B0H
430H
3B0H
330H
:
:
:
:
:
:
:
:
6BFH
63FH
5BFH
53FH
4BFH
43FH
3BFH
33FH
6C0H
640H
5C0H
540H
4C0H
440H
3C0H
340H
:
:
:
:
:
:
:
:
6CEH 64EH 5CEH 54EH 4CEH 44EH 3CEH 34EH
6CFH
64FH
5CFH
54FH
4CFH
44FH
3CFH
34FH
6. LCD Power Supply
The built-in LCD power supply is equipped with input voltage regulator, voltage multiplier and bias
voltage generating circuit with active buffer instead of passive resistor voltage dividing network. The
input voltage is regulated to LVREG using the internally generated LVAG as reference voltage. LVREG
can be adjusted by resistor between LGS1 and LVREG.
LVREG adjustment guideline: First, the level of VDD must be 0.3 volt higher than LVREG even at the
end of battery life for the regulator to function properly. For example, if the VDD is expected to drop to
2.2 volts when battery is low, then the level of LVREG can only be set at 1.9 volts max. Secondly, the
higher the level of LVREG, the less multiples it requires to pump LVP to same level. For example, to
August 25, 2003
Page 8 of 26
V2.6E
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pump the 2.25 volts to 9 volts requires 4 times multiplier; to pump the 3 volts to 9 volts requires only 3
time multiplier which consumes less power. So it is advisable not to adjust the LVREG to an unnecessary
low level.
Voltage multiplication: The LVREG is then multiplied by 3, 4, or 5 times, depending on external
capacitors configurations as shown below, to generate LVP. Please note that LVP must be lower than 9
volts to prevent chip from breaking down.
x3 multiplier
x4 multiplier
x5 multiplier
4.7uF
LVL1
4.7uF
LVL1
4.7uF
LVL1
0.1uF
LVL2
0.1uF
LVL2
0.1uF
LVL2
0.1uF
LVL3
0.1uF
LVL3
0.1uF
LVL3
4.7uF
LVL4
4.7uF
LVL4
4.7uF
LVL4
10uF
LVL5
10uF
LVL5
10uF
LVL5
LGS2
4.7uF
R
LGS2
4.7uF
R
LGS2
LVP
4.7uF
LCAP4A
LCAP4A
0.1uF
LCAP2B
LCAP2B
LVP
R
LVP
LCAP4A
LCAP2B
0.1uF
LCAP2A
0.1uF
LCAP2A
0.1uF
LCAP2A
0.1uF
LCAP1A
0.1uF
LCAP1A
0.1uF
LCAP1A
LCAP1B
0.1uF
LCAP1B
0.1uF
LCAP3A
0.1uF
LCAP3A
LVREG
0.1uF
LVREG
0.1uF
LVREG
LGS1
0.1uF
R
LCAP1B
LCAP3A
LGS1
0.1uF
LVAG
R
LVAG
LGS1
0.1uF
R
LVAG
The LVP is then regulated to generated LVL1 ~ LVL5. LVL5 can be adjusted by the resistor between
LGS2 and LV5. Be sure to leave at least 0.3 volt between LVP and LV5 for the regulator circuit to
function properly. The formula is:
LVL5 = (1 + R2/80K) x 0.9V
Different duties require different bias settings. There is some theoretical correspondence between the
Duty and Bias Setting. However, it is better to use it as starting point and adjust it with real LCD panel
connected to it to determine the final setting. The theoretic relationship between the duty and bias setting
as following:
Duty Cycle Normal Bias Alternative Bias
32 duty
1/7
1/7.5
48 duty
1/8
1/7.5, 1/8.5
64 duty
1/9
1/8.5, 1/9.5
80 duty
1/10
1/9.5, 1/10.5
The bias setting is made by mask option MO_LBSR[2..0].
MO_LBSR[2..0] Bias Setting
August 25, 2003
Page 9 of 26
V2.6E
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000
001
010
011
100
101
110
111
有
限
公
司
HE84770
HE80000 SERIES
1/7
1/7.5
1/8
1/8.5
1/9
1/9.5
1/10
1/10.5
6.1. LCDC Control register
The gray scale of the LCD driver can be adjusted by GRAY field of LCD. The LCD panel can be blanked
by setting the BLANK field of LCDC register. LCD driver can be totally turned off by clearing LCDE bit
of LCDC.
LCDC
Field
Reset
bit 7
-
Field
GRAY
Value
000
111
BLANK
0
1
LCDE
0
1
bit 6
-
bit 5
-
bit 4
-
bit 3
GRAY
-
bit 2
-
bit 1
BLANK
1
bit 0
LCDE
0
Function
LCD is darkest.
LCD is lightest.
normal display
LCD display blanked. The COM signals of LCD driver output inactive levels
(LVL4 and LVL1) while SEG signals output normal display patterns.
LCD driver disabled, LCD driver has no output signal.
LCD driver Enabled
Please note that LCD driver must be turned off before the MCU goes into sleep mode. In other words,
user must clear the bit 0 (LCDE bit) of LCDC to turn off LCD driving circuit before setting bit6 of OP1
to enter sleep mode. Large current might happen if the procedure is not followed.
Please note that LCD driver uses slow clock as clock source. The LCD display would not display
normally if it worked in Fast clock only mode as the LCD refresh action would be too fast.
7. Oscillators
The MCU is equipped with two clock sources with a variety of selections on the types of oscillators to
choose from. So that system designer can select oscillator types based on the cost target, timing accuracy
requirements etc. Crystal, Resonator or the RC oscillator can be used as fast clock source, components
should be placed as close to the pins as possible. The type of oscillator used is selected by mask option
MO_FXTAL.
August 25, 2003
Page 10 of 26
V2.6E
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VDD
FXI
FXI
FXO
Crystal Osc.
RC Osc.
MO_FXTAL Fast clock type
0
RC Oscillator.
1
Crystal Oscillator.
Slow clock is clock source for LCD display, Timer1, and Timer Base, etc. Two types of oscillator, crystal
and RC, can be used as slow clock by mask option MO_SXTAL. If used for time keeping function or
other applications that required the accurate timing, crystal oscillator is recommended. If the timing
accuracy is not important, then RC type oscillator can be used to reduce cost.
MO_SXTAL Slow clock type
0
R/C oscillator
1
Crystal oscillator
SXI
SXI
SXO
SXO
Crystal Osc.
RC Osc.
With two clock sources available, the system can switch among operation modes of Fast, Slow, Idle, and
Sleep modes by the setting of OP1 and OP2 registers as shown in tables below to suit the needs of
application such as power saving, etc.
OP1
Field
Mode
Reset
Bit 7
DRDY
R/W
1
Bit 6
STOP
R/W
0
Bit 5
SLOW
R/W
0
Bit 4
INTE
R/W
0
Bit 3
T2E
R/W
0
Bit 2
T1E
R/W
0
Bit 1
Z
R/W
-
Bit 0
C
R/W
-
OP2
Field
Mode
Reset
Bit 7
IDLE
R/W
0
Bit 6
PNWK
R
-
Bit 5
TCWK
R
-
Bit 4
TBE
R/W
0
Bit 3
Bit 2
Bit 1
TBS[3..0]
W
W
-
Bit 0
August 25, 2003
Page 11 of 26
W
-
W
-
V2.6E
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If the dual clock mode is used, the LCD display, Timer1 and Timer Base will derive its clock source from
slow clock while the other blocks will operate with the fast clock.
8. General Purpose I/O
There are three dedicated general purpose I/O port, PRTC, PRTD and PRT10, while PRT14, PRT15 and
PRT17 are multiplexed with LCD segment driver pins. All the I/O Ports are bi-directional and of nontri-state output structure. The output has weak sourcing (50 µA) and stronger sinking (1 mA) capability
and each can be configured as push-pull or open-drain output structure individually by mask option.
When the I/O port is used as input, the weakly high sourcing can be used as weakly pull-up. Open drain
can be used if the pull-up is not required and let the external driver to drive the pin. Please note that a
floating pad could cause more power consumption since the noise could interfere with the circuit and
cause the input to toggle. A ‘1’ needs to be written to port first before reading the input data from the I/O
pin. If the PMOS is used as pull-up, care should be taken to avoid the constant power drain by DC path
between pull-up and external circuit.
The input port has built-in Schmidt trigger to prevent it from chattering. Hysteresis level of Schmidt
trigger is 1/3*VDD.
VDD
DOUT
VDD
Q
LATCH
Q'
MO_?PP
PAD
DIN
SCHMIDT Trigger input
As pads of PRT14, PRT15 and PRT17 are shared with LCD segment driver, the function of the pads is
determined by mask options.
August 25, 2003
Page 12 of 26
V2.6E
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LIO17=0
LIO17=1
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
LIO15=0
LIO15=1
PRT150
PRT151
PRT152
PRT153
PRT154
PRT155
PRT156
PRT157
PRT150
PRT151
PRT152
PRT153
PRT154
PRT155
PRT156
PRT157
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
LIO14=0
LIO14=1
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
公
司
HE84770
HE80000 SERIES
Following table is the setting for MO_LIO?[...] and MO_?PP[...] and others related to LCD display
setting and pin assignment features.
MO_LIO?[…] MO_?PP[...]
I/O Port
LCD Pin
0
0
Open-drain output
-0
1
Push-pull output
-1
0
-xx
1
1
-LCD Display
--: Function not available.
xx: Displayable, but may have abnormal leakage current, do not use.
9. Key Scan Circuit
The built-in 4x20 hardware keyboard scan circuit helps to reduce the pin counts where application
requires large key matrix and high LCD pixel count as well as the firmware effort. As key-scan pins are
shared with LCD segment and PRTC4 ~ PRTC7 pins, it is advisable to put resistors between segment pins
and key matrix to avoid shorting the segment pins when two or more keys in the same row are pressed
simultaneously. Two key can be detected simultaneously and the first detected key code is stored in
KEY0 register and the second in KEY1 register respectively. The key code for each key location is listed
in the following table.
Key Loc
SCNO0
SCNO1
SCNO2
SCNO3
SCNO4
August 25, 2003
SCNI0
0x80
0x81
0x82
0x83
0x84
SCNI1
0xA0
0xA1
0xA2
0xA3
0xA4
SCNI2
0xC0
0xC1
0xC2
0xC3
0xC4
Page 13 of 26
SCNI3
0xE0
0xE1
0xE2
0xE3
0xE4
V2.6E
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SCNO5
SCNO6
SCNO7
SCNO8
SCNO9
SCNO10
SCNO11
SCNO12
SCNO13
SCNO14
SCNO15
SCNO16
SCNO17
SCNO18
SCNO19
子
股
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
份
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
有
限
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
0xD2
0xD3
公
司
HE84770
HE80000 SERIES
0xE5
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
0xEF
0xF0
0xF1
0xF2
0xF3
KEY0
0x22
BIT7
R
BIT6
BIT5
Row Index
BIT4
BIT3
BIT2
BIT1
Column Index
BIT0
KEY1
0x23
BIT7
R
BIT6
BIT5
Row Index
BIT4
BIT3
BIT2
BIT1
Column Index
BIT0
The bit 7 of KEY0 and KEY1 is repeat indicator when the same key is scanned for the second time, the R
bit will be cleared to indicate the key is not released yet.
The key-scan function can be turned on/off by mask option MO_LCDKEY.
MO_LCDKEY
0
1
SGKY[43..24] Function
as SEG only
as SEG as well as KEY_SCAN
The pulse width of key-scan signal can be selected by mask options MO_SNCK[1..0].
MO_SNCK[1..0]
00
01
10
11
Key Scan Pulse Width
0.5 sck
1 sck
1.5 sck
2 sck
The strength of key-scan signal can also be selected by mask options MO_SNCK[1..0].
MO_SCDRV[1..0]
00
01
10
11
August 25, 2003
Key Scan Signal Strength
weakest
strongest
Page 14 of 26
V2.6E
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SCNO0
SCNO1
SCNO2
SCNO3
SCNO17
SCNO18
SCNO19
SGKY 24
SGKY 25
SGKY 26
SGKY 27
:
SGKY 41
SGKY 42
SGKY 43
SCNI0
PRTC4
SCNI1
PRTC5
SCNI2
PRTC6
SCNI3
PRTC7
億
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有
47K
47K
47K
47K
限
公
47K
司
HE84770
HE80000 SERIES
47K
47K
....
10. Timer1
The Timer1 consists of two 8-bit write-only preload registers T1H and T1L and 16-bit down counter. If
Timer1 is enabled, the counter will decrement by one with each incoming clock pulse. Timer1 interrupt
will be generated when the counter underflows - counts down to FFFFH. And the counter will be
automatically reloaded with the value of T1H and T1L.
The clock source of Timer1 is derived from slow clock “SCK” at dual clock or slow clock only mode.
And it comes from the fast clock “FCK” at fast clock only mode.
Please note that the interrupt is generated when counter counts from 0000H to FFFFH. If the value of
T1H and T1L is N, and count down to FFFFH, the total count is N+1. The content of counter is zero
when system resets. Once it is enabled to count at this moment, interrupt will be generated immediately
and value of T1H and T1L will be loaded since it counts to FFFFH. So the T1H and T1L value should be
set before enabling Timer1.
August 25, 2003
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V2.6E
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The contents of T1H and
T1L almost loaded into
Timer1 immediately
when Timer1 is turned on
after reset.
子
股
T1H
份
有
限
T1L
公
司
HE84770
HE80000 SERIES
Auto reload when
Timer1 underflow
"Timer1 Counter"
decreases 1
No
Count TO
0xFFFFh
Start Timer1
Interrupt Request.
Yes
T1_INT
The Timer1 related control registers are list as below:
Register Address
Field
Bit position Mode
Description
0x02
TC1_IER
2
R/W 0: TC1 interrupt is disabled. (default)
IER
1: TC1 interrupt is enabled.
0x03
T1L[7:0]
7~0
W Low byte of TC1 pre-load value
T1L
0x04
T1H[7:0]
7~0
W High byte of TC1 pre-load value
T1H
0x09
TC1E
2
R/W 0: TC1 is disabled. (default)
OP1
1: TC1 is enabled.
11. Timer2
Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock
“Fsys”/1.5. The system clock “Fsys” varies depending on the operation modes of the MCU.
The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If
Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will
be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded
August 25, 2003
Page 16 of 26
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with the value of T2H and T2L.
Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value
of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when
system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and
value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value
should be set before enabling Timer2.
The contents of T2H and
T2L almost loaded into
Timer2 immediately
when Timer2 is turned on
after reset.
T2H
T2L
Auto reload when
Timer2 underflow
"Timer2 Counter"
decreases 1
No
Count TO
0xFFFFh
Yes
Start Timer2
Interrupt Request.
T2_INT
The Timer2 related control registers are list as below:
Register Address
Field
Bit position Mode
Description
0x02
TC2_IER
1
R/W 0: TC2 interrupt is disabled. (default)
IER
1: TC2 interrupt is enabled.
0x05
T2L[7:0]
7~0
W
Low byte of TC2 pre-load value
T2L
0x06
T2H[7:0]
7~0
W High byte of TC2 pre-load value
T2H
0x09
TC2E
3
R/W 0: TC2 is disabled. (default)
OP1
1: TC2 is enabled.
August 25, 2003
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V2.6E
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12. Time Base Interrupt
The TB timer is used to generate time-out interrupt at fixed period. The time-out frequency of TB is
determined by dividing slow clock with a factor selected in OP2[3:0]. TBE (Time Base Enable) bit
controls enable or disable of the circuit.
OP2
Field
Mode
Reset
Bit 7
IDLE
R/W
0
Bit 6
PNWK
R
-
Bit 5
TCWK
R
-
Bit 4
TBE
R/W
0
Bit 3
W
-
Bit 2
Bit 1
TBS[3..0]
W
W
-
Bit 0
W
-
TBE Function
0
Disable Time Base
1
Enable Time Base
For example, if the slow clock is 32768 Hz, then the interrupt frequency is as shown in following table.
TBS[3..0] Interrupt Frequency
0000
16.384 KHz
0001
8.192 KHz
0010
4.096 KHz
0011
2.048 KHz
0100
1.024 KHz
0101
512 Hz
0110
256 Hz
0111
128 Hz
1000
64 Hz
1001
32 Hz
1010
16 Hz
1011
8 Hz
1100
4 Hz
1101
2 Hz
1110
1 Hz
1111
0.5 Hz
13. Watch Dog Timer
Watch Dog Timer (WDT) is designed to reset system automatically prevent system dead lock caused by
abnormal hardware activities or program execution.
WDT needs to be enabled in Mask Option.
MO_WDTE Function
0
WDT disable
1
WDT enable
To use WDT function, “CLRWDT” instruction needs to be executed in every possible program path
when the program runs normally in order to clears the WDT counter before it overflows, so that the
August 25, 2003
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program can operate normally. When abnormal conditions happen to cause the MCU to divert from
normal path, the WDT counter will not be cleared and reset signal will be generated.
WDT is the enabling signal generated by calculating 32768-clock overflow.
same as TC1 (Timer1 clock), which uses the same clock count source.
Reset Register content is
WDT function can be generated
in Normal, Slow and Idle Mode. However, WDT will not function during Sleep Mode (as the TC1
clock has stopped.)
14. Digital-to-Analog Converter
The Digital-to-Analog converter (DAC) converts the 7-bit unsigned speech data written to PWMC to
proportional current output.
PWMC register
DA & PWM Data
Control
Bit 7
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
DA and PWM output value
PWM O/P driver
-
Bit 1
Bit 0
-
PWME
There are two output paths for the DAC. Either VO or DAO can be selected as output port of DAC by
VOC register when it is enabled. The VO output is primarily intended for speech generation, although it
is not necessary so, while the DAO output path can be used in conjunction with built-in OP comparator to
function as an Analog-to-Digital Converter as required in applications such as speech recording, speech
recognition or sensor interfaces.
OPO
OP
+
-
PWMC[DATA]
DAC
OPIP
OPIN
1
DAO
0
VO
R
VOC[DAC]
VOC[OP]
The DAC is enabled by DAC bit of VOC register. Please note that the DAC bit of VOC register will be
automatically cleared when the system enter Idle or Sleep mode. So it needs to be set again when
returning to Normal mode.
VOC register
Field
Reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit Name Value
1
1
DAC
0
August 25, 2003
Bit 4
-
Bit 3
-
Bit 2
PWM
0
Bit 1
DAC
0
Bit 0
OP
0
Function description
DA Enable
DA Disable
Page 19 of 26
V2.6E
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15. Pulse-Width Modulation
The pulse-width modulator (PWM) converts 7-bit unsigned speech data written to PWMC data register to
proportional duty cycle of PWM output. PWM module shares the PWMC data register with
Digit-to-Analog Converter. So PWM and DA output can exist at the same time. When PWM circuit is
enabled, it generates signal with duty ratio in proportion to the DA value.
DA = 0x20
DA = 0x80
DA = 0xE0
1 subframe
The PWM bit of VOC register controls register to enable the circuit and output driver. When PWM bit of
VOC is ‘0’, PWME bit and output drivers settings are both cleared. To use PWM for voice output, PWM
bit has to be set to ‘1’ first, then set PWME bit and enable output driver by setting the driver number. If
PWM bit is disabled and enabled again, the setting for driver and PWME bit will be clear.
The Fast Clock is gated through PWME bit of PWMC command register to provide the clock source of
PWM circuit when it is enabled. As PWM needs higher frequency to operate, it cannot generate correct
PWM signal in Slow clock only mode.
When the program enters into Sleep mode or Idle mode, it will automatically turn off all voice outputs by
clearing VOC[2..1] to ”00”. To activate voice output again when returning to Normal Mode, the VOC
register needs to be set again.
The PWM output volume can be adjusted by command register PWMC[6..4]. The bit 6 and 5 control 2
time driver, while bit 4 controls 1 time driver, thus it has 5 levels of driver output. By turning on/off the
internal drivers, the sound level of PWM output can be turned up and down. Please note that this
adjustment apply only to PWM, but not DA output.
PWM output driver selection
PWMC[6..4] Number of Driver
000
off
001
1
010
2
011
3
100
2
101
3
110
4
111
5
August 25, 2003
Page 20 of 26
V2.6E
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16. Absolute Maximum Rating
Item
Supply Voltage
LCD operating Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
Sym.
Rating
Condition
VDD
-0.5V ~ 4.0V
VLVP
< 8.5 Volts
VIN -0.5V ~ VDD +0.5V
VO -0.5V ~ VDD +0.5V
TOP
0°C ~ 70°C
TST
-50°C ~ 100°C
17. Recommended Operating Conditions
Item
Supply Voltage
Input Voltage
Operating Frequency
Operating Temperature
Storage Temperature
18.
Sym.
Rating
VDD
2.4V ~ 3.6V
VIH 0.9 VDD ~ VDD
VIL 0.0V ~ 0.1 VDD
8MHz
FMAX
6MHz
°
TOP
0 C ~ 70°C
TST -50°C ~ 100°C
Condition
VDD =3.0V
VDD =2.4V
AC/DC Characteristics
Testing Condition : TEMP=25℃, VDD=3V±10%
Parameters
Symbol
Power consumption
Normal mode current
Min.
Typ.
Max.
Unit
Condition
IFAST
1
1.5
mA
Slow mode Current
ISLOW
15
25
µA
Idle mode Current
IIDLE
10
20
µA
2M external R/C fast clock
32768 Hz slow clock with LCD
disabled
32768 Hz slow clock with LCD
disabled
Sleep mode Current
ISLEEP
µA
Additional Current if LCD
ON
ILCD
200
250
300
1
220
275
330
µA
I/O specification
Input High Voltage
Input Low Voltage
VIH
VIL
Input Hysteresis Width
VHYS
Output Source Current
Output Sink Current
IOH
IOL1
Input Low Current
IIL1
20
µA
Input Low Current
IIL2
100
µA
PWM and DAC
PWM Output Current
IPWM
14
mA
August 25, 2003
0.8
0.2
1/3
VDD
VDD
VDD
50
1.0
10
µA
mA
Page 21 of 26
LVP=3*LVREG
LVP=4*LVREG
LVP=5*LVREG
Input Pins
Input Pins
I/O, RSTP_N Threshold = 2/3xVDD
(Input from low to high), Threshold =
1/3xVDD (Input from high to low)
Output drive high*1, VOL=2.0V
Output drive low, VOL=0.4V
RSTP_N, VIL = GND, Pull high
Internally
I/O, VIL=GND, if pull high Internally by
user
PWM *2 With 32Ω Loading
V2.6E
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4
8
5
mA
mA
2.5
3
mA
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HE84770
HE80000 SERIES
With 64Ω Loading
With 100Ω Loading
VO, DAO@ VDD=3V,VO=0~2V, Data
= 7F
Notes:
1.
The “Output Source Current” specification is applicable only to the Push-Pull I/O type.
2.
This specification indicates only one PWM driving capability, and there are totally five built-in drivers, user
can multiply the actual number of driver to get the actual current. (IPWM x N; where N = 0, 1, 2, 3, 4, 5)
August 25, 2003
Page 22 of 26
V2.6E
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19. Application Circuit
VDD
HE84770
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PRTC0
PRTC1
PRTC2
PRTC3
PRTC4
PRTC5
PRTC6
PRTC7
PWM
0.1uF
BUZZER
PRTD0
PRTD1
PRTD2
PRTD3
PRTD4
PRTD5
PRTD6
PRTD7
PRT100
PRT101
PRT102
PRT103
PRT104
PRT105
PRT106
PRT107
VDD
0.1uF
SXI
1
VDD_RAM
PRTC0
PRTC1
PRTC2
PRTC3
PRTC4
PRTC5
PRTC6
PRTC7
PWM
GND_PWM
PRTD0
PRTD1
PRTD2
PRTD3
PRTD4
PRTD5
PRTD6
PRTD7
PRT100
PRT101
PRT102
PRT103
PRT104
PRT105
PRT106
PRT107
VDD
SXI
+
SXI
3.0V
47uF
2
SEG48
SEG47
SEG46
SEG45
SEG44
SGKY43
SGKY42
SGKY41
SGKY40
SGKY39
SGKY38
SGKY37
SGKY36
SGKY35
SGKY34
SGKY33
SGKY32
SGKY31
SGKY30
SGKY29
SGKY28
SGKY27
SGKY26
SGKY25
SGKY24
PRT147
PRT146
PRT145
PRT144
PRT143
PRT142
PRT141
PRT140
PRT157
PRT156
PRT155
PRT154
PRT153
PRT152
PRT151
PRT150
PRT177
PRT176
PRT175
PRT174
PRT173
PRT172
PRT171
PRT170
COM31
COM30
COM29
COM28
COM27
COM26
COM25
C0M24
C0M23
C0M22
C0M21
C0M20
C0M19
C0M18
C0M17
C0M16
C0M15
C0M14
C0M13
C0M12
C0M11
C0M10
C0M9
C0M8
C0M7
C0M6
C0M5
C0M4
C0M3
COM2
COM1
COM0
LVL1
LVL2
LVL3
LVL4
LVL5
LGS2
LVP
LCAP4A
LCAP2B
LCAP2A
LCAP1A
LCAP1B
LCAP3A
LVREG
LGS1
LVAG
GND
VO
DAO
OPIN
OPIP
OPO
RSTP_N
FXO
FXI
TSTP_P
SXO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
CMSG79
CMSG78
CMSG77
CMSG76
CMSG75
CMSG74
CMSG73
CMSG72
CMSG71
CMSG70
CMSG69
CMSG68
CMSG67
CMSG66
CMSG65
CMSG64
CMSG63
CMSG62
CMSG61
CMSG60
CMSG59
CMSG58
CMSG57
CMSG56
CMSG55
CMSG54
CMSG53
CMSG52
CMSG51
CMSG50
CMSG49
CMSG48
CMSG47
CMSG46
CMSG45
CMSG44
CMSG43
CMSG42
CMSG41
CMSG40
CMSG39
CMSG38
CMSG37
CMSG36
CMSG35
CMSG34
CMSG33
CMSG32
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
CMSG32
CMSG33
CMSG34
CMSG35
CMSG36
CMSG37
CMSG38
CMSG39
CMSG40
CMSG41
CMSG42
CMSG43
CMSG44
CMSG45
CMSG46
CMSG47
CMSG48
CMSG49
CMSG50
CMSG51
CMSG52
CMSG53
CMSG54
CMSG55
CMSG56
CMSG57
CMSG58
CMSG59
CMSG60
CMSG61
CMSG62
CMSG63
CMSG64
CMSG65
CMSG66
CMSG67
CMSG68
CMSG69
CMSG70
CMSG71
CMSG72
CMSG73
CMSG74
CMSG75
CMSG76
CMSG77
CMSG78
CMSG79
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
PRT147
PRT146
PRT145
PRT144
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
20P
VDD
Y1
SXO
FXI
FXO
RST
OPO
OPIP
OPIN
DAO
VO
LVAG
LGS1
LVREG
LCAP3A
LCAP1B
LCAP1A
LCAP2A
LCAP2B
LCAP4A
LVP
LGS2
LVL5
LVL4
LVL3
LVL2
LVL1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
PRT150
PRT151
PRT152
PRT153
PRT154
PRT155
PRT156
PRT157
PRT140
PRT141
PRT142
PRT143
32768Hz
20P
R
SXO
FXI
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
PRT150
PRT151
PRT152
PRT153
PRT154
PRT155
PRT156
PRT157
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
LIO17=0
LIO17=1
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
LIO15=0
LIO15=1
PRT150
PRT151
PRT152
PRT153
PRT154
PRT155
PRT156
PRT157
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
LIO14=0
LIO14=1
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
VDD
SXI
SXO
FXI
RC Osc.
CMSG32
CMSG33
CMSG34
CMSG35
CMSG36
CMSG37
CMSG38
CMSG39
CMSG40
CMSG41
CMSG42
CMSG43
CMSG44
CMSG45
CMSG46
CMSG47
CMSG48
CMSG49
CMSG50
CMSG51
CMSG52
CMSG53
CMSG54
CMSG55
CMSG56
CMSG57
CMSG58
CMSG59
CMSG60
CMSG61
CMSG62
CMSG63
CMSG64
CMSG65
CMSG66
CMSG67
CMSG68
CMSG69
CMSG70
CMSG71
CMSG72
CMSG73
CMSG74
CMSG75
CMSG76
CMSG77
CMSG78
CMSG79
32X128
SEG127
SEG126
SEG125
SEG124
SEG123
SEG122
SEG121
SEG120
SEG119
SEG118
SEG117
SEG116
SEG115
SEG114
SEG113
SEG112
SEG111
SEG110
SEG109
SEG108
SEG107
SEG106
SEG105
SEG104
SEG103
SEG102
SEG101
SEG100
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
48X112
64X96
80X80
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
SEG111
SEG110
SEG109
SEG108
SEG107
SEG106
SEG105
SEG104
SEG103
SEG102
SEG101
SEG100
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
Y2
4MHz
0.1uF
560K
4.7uF
0.1uF
0.1uF
1uF
0.1uF
10uF
0.1uF
4.7uF
0.1uF
4.7uF
SCNO0
SCNO1
SCNO2
SCNO3
SCNO17
SCNO18
SCNO19
FXO
SGKY24
SGKY25
SGKY26
SGKY27
:
SGKY41
SGKY42
SGKY43
47K
SCNI0
PRTC4
SCNI1
PRTC5
SCNI2
PRTC6
SCNI3
PRTC7
0.1uF
15P
47K
47K
47K
....
47K
47K
x3 multiplier
47K
x4 multiplier
x5 multiplier
4.7uF
LVL1
4.7uF
LVL1
4.7uF
LVL1
0.1uF
LVL2
0.1uF
LVL2
0.1uF
LVL2
0.1uF
LVL3
0.1uF
LVL3
0.1uF
LVL3
4.7uF
LVL4
4.7uF
LVL4
4.7uF
LVL4
10uF
LVL5
10uF
LVL5
10uF
LGS2
R
LVP
4.7uF
RC Osc.
LGS2
R
LVL5
LGS2
R
LVP
4.7uF
LVP
LCAP4A
LCAP4A
0.1uF
LCAP4A
LCAP2B
LCAP2B
4.7uF
LCAP2B
0.1uF
LCAP2A
0.1uF
LCAP2A
0.1uF
LCAP2A
0.1uF
LCAP1A
0.1uF
LCAP1A
0.1uF
LCAP1A
LCAP1B
0.1uF
LCAP1B
0.1uF
Page 23 of 26
R
LCAP1B
LCAP3A
0.1uF
LCAP3A
0.1uF
LVREG
0.1uF
LVREG
0.1uF
LGS1
August 25, 2003
15P
0
260K
COMXSEG
LVAG
LCAP3A
LVREG
LGS1
0.1uF
R
LVAG
LGS1
0.1uF
R
LVAG
V2.6E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
HE84770
HE80000 SERIES
20. Important Note
1. The LCD refresh cycles are:
32 COM : Refresh Cycle=~170Hz
48 COM : Refresh Cycle=~110Hz.
2. To access any data ROM (DROM) of which address is larger than 64KB, users must update TPP first,
TPH 2nd and TPL lastly. Only follow this order, the pre-charge circuit of DROM will work correctly.
Since the Data ROM is a low speed ROM. 5us waiting time is necessary before LDV instruction is
executed to access the DROM. Note this 5us delay can’t be emulated in the developing tools (ICE and
KBIDS) and the 5us delay should be added by firmware.
3. LCD driving circuit must be turn off before IC enters into sleep mode.
4. Please bonds the TSTP_P, RSTP_N and PRTD[7:0] with test point on PCB (can be soldered and
probed) as you can. If necessary, some IC testing can be done on the PCB. The following figure is an
example (Testing point with through hole).
5. LVP must small than 8.5 Volt. Otherwise IC may breakdown.
6. The LCD voltage adjustment mechanism shall be reserved for LV5 voltage fine-tunes; since it’s possible
there is some variation in LV5 voltage due to IC manufacture process variation. User can use
variable-resistor to adjust the LV5 voltage or use some tools to detect the LV5 and then select a proper
resistor. Please refer to application note AN025 for the detailed description.
7. Users must call the library “swap_page” in the file swappage.asm of AN029. The real IC register is different
from ICE4.x or ICE5.x. This subroutine makes sure that users can run on both real IC and ICE for page
swapping.
.area
swapping_variable(data)
_mapreg1::
.ds
1 ;store page register(R1Bh)
_mapreg2::
.ds
1 ;store page register(R1Ch)
August 25, 2003
Page 24 of 26
V2.6E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
HE84770
司
HE80000 SERIES
.area
swapping_page(code,pag0)
;======================================================
;swap page function
;======================================================
swap_page::
lda #10h
sta _mapreg1
lda #00h
; P1E_O[2] <--0
to enable Port R1Fh
sta r_iceco
; R_ICECO is write only
lda _mapreg2
sta r_iced
lda _mapreg2
anda #0fh
ora #20h
;Mapping _mapreg2 low nibble to Logical segment2
;
sta r1Ch
sta r_ps1
lda _mapreg2
rorc
rorc
rorc
rorc
anda #0fh
;Mapping _mapreg2 high nibble to Logical segment3
;
ora #30h
sta r_ps1
sta r1Ch
ret
21. Updated Record
Version
V2.2
Nov 27,2001
Date
V2.3
Dec 13, 2001
V2.4
Dec 14, 2001
V2.41
Dec 19, 2001
2.4V
32 COM : ~64Hz -> ~170Hz
B
LCD Refresh Rate
48 COM : ~64Hz -> ~110Hz
VDD_RAM
D,F,G, I
No VDD_RAM, replaced by VDD
MO_LCDKEY=1: LCD SGKY[43:24] MO_LCDKEY=0: LCD SGKY[43:24]
D
V2.42
May 29, 2003
J
August 25, 2003
Section
Original Content
B, H
2.2V (VDD operation voltage)
New Content
as SEG pin only
as SEG pin only
TSTP_P pin Floating
TSTP_P pin connect with zero Ohm
Page 25 of 26
V2.6E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
B
V2.5
Feb. 13, 2003
V2.6
Sep. 25, 2003
August 25, 2003
限
公
司
HE84770
HE80000 SERIES
LCDC control register bit definition
Added function block descriptions
Remove the low voltage function,
this function is not implemented.
Page 26 of 26
V2.6E
This specification is subject to change without notice. Please contact sales person for the latest version before use.