TECHNICAL DATA KK74HC574A Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS N SUFFIX PLASTIC DIP The KK74HC574A is identical in pinout to the LS/ALS574. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The OE input does not affect the states of the flip-flops, but when OE is high, all device outputs are forced to the high-impedance state; thus, data may be stored even when the outputs are not enabled. • • • • 20 1 DW SUFFIX SOIC 20 1 ORDERING INFORMATION Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices KK74HC574AN Plastic DIP KK74HC574ADW SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM DATA INPUTS D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 D4 6 15 Q3 Q4 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 D5 CLOCK NONINVERTING OUTPUTS OE 1 20 V CC D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 10 11 CLOCK GND FUNCTION TABLE 11 Inputs OE 1 OE PIN 20=VCC PIN 10 = GND D Q L H H L L L X no change X Z L H Clock Output L,H, X H= high level L = low level X = don’t care Z = high impedance 1 KK74HC574A MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN Tstg TL Storage Temperature Lead Temperature, 1.5 mm from Case for 4 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74HC574A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VC Guaranteed Limit C Symbol Parameter Test Conditions V 25 °C to -55°C ≤85 °C ≤125 °C Unit VIH Minimum High-Level Input Voltage VOUT ≥ VCC-0.1 V ⎢IOUT⎢≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT⎢ ≤ 0.1 V ⎢IOUT⎢ ≤ 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V VOH Minimum High-Level Output Voltage VIN=VIH ⎢IOUT⎢ ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN= VIL ⎢IOUT⎢ ≤ 6.0 mA ⎢IOUT⎢ ≤7.8 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 VIN=VIH ⎢IOUT⎢ ≤ 6.0 mA ⎢IOUT⎢ ≤ 7.8 mA VOL Maximum Low-Level Output Voltage VIN= VIL ⎢IOUT⎢ ≤ 20 µA V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA IOZ Maximum Three State Leakage Current Output in High-Impedance State VIN =VIH VOUT= VCC or GND 6.0 ±0.5 ±5.0 ±10 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 4.0 40 160 µA 3 KK74HC574A AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125° C Unit Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 4.5 6.0 6.0 30 35 4.8 24 28 4.0 20 24 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures 1 and 4) 2.0 4.5 6.0 160 32 27 200 40 34 240 48 41 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tPZH, tPZL Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5) 2.0 4.5 6.0 140 28 24 175 35 30 210 42 36 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns Maximum Input Capacitance - 10 10 10 pF Maximum Three-State Output Capacitance (Output in High-Impedance State) - 15 15 15 pF Symbol fmax CIN COUT CPD Parameter Power Dissipation Capacitance (Per Enabled Output) Typical @25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 24 pF TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns) VCC Symbol Parameter Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit tSU Minimum Setup Time, Data to Clock (Figure 3) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns th Minimum Hold Time, Clock to Data (Figure 3) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns 4 KK74HC574A tr VCC tf VCC 90% 50% 10% CLOCK 50% OE GND GND t PZL t PLZ tw 1/fmax Q t PHL tPLH Q 50% 10% 50% 10% t PHZ tPZH 90% Q tTLH HIGH IMPEDANCE VOL VOH 90% 50% HIGH IMPEDANCE t THL Figure 1. Switching Waveforms Figure 2. Switching Waveforms VALID VCC D 50% GND t su th VCC CLOCK 50% GND Figure 3. Switching Waveforms TEST POINT DEVICE UNDER TEST TEST POINT OUTPUT DEVICE UNDER TEST * CL OUTPUT Connect to V CC when testing tPLZ and tPZL Connect to GND when testing tPHZ and tPZH 1k * CL * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 4. Test Circuit Figure 5. Test Circuit EXPANDED LOGIC DIAGRAM D0 D1 D D2 D C Q D3 D C Q D4 D C Q D5 D C Q D6 D C Q D7 D C Q D C Q C Q CLOCK OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 5 KK74HC574A N SUFFIX PLASTIC DIP (MS - 001AD) A Dimension, mm 11 20 B 1 10 Symbol MIN MAX A 24.89 26.92 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 N G K M J H D 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 013AC) A 20 11 H Dimension, mm B 1 P 10 G R x 45 C -TK D SEATING PLANE J 0.25 (0.010) M T C M NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. F M Symbol MIN MAX A 12.6 13 B 7.4 7.6 C 2.35 2.65 D 0.33 0.51 F 0.4 1.27 G 1.27 H 9.53 J 0° 8° K 0.1 0.3 M 0.23 0.32 P 10 10.65 R 0.25 0.75 6