TECHNICAL DATA KK74LV164 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER The KK74LV164 is a low-voltage Si-gate CMOS device and is pin and function compatible with the KK74HC/HCT164. The KK74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is the logical AND of the two data inputs (DSA, DSB ) that existed one set-up time prior to the rising clock edge. A LOW on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 1.2 to 5.5 V • Low Input Current: 1.0 µA, 0.1 µА at Т = 25 °С • Output Current: 6 mA at VCC = 3.0 V; 12 mA at VCC = 4.5 V • High Noise Immunity Characteristic of CMOS Devices N SUFFIX PLASTIC DIP 14 1 D SUFFIX SO 14 1 ORDERING INFORMATION Plastic SOIC KK74LV164N KK74LV164D TA = -40° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM 1 SERIAL DSA DATA 2 INPUTS DSB DATA DSA 1 14 VCC DSB 2 13 Q7 Q0 3 12 Q6 Q1 4 11 Q5 Q2 5 10 Q4 2 Q0 Q3 6 9 MR 4 Q1 GND 7 8 CP 5 Q2 6 Q3 10 Q4 PARALLEL DATA OUTPUTS 11 Q5 12 Q6 CP 8 FUNCTION TABLE 13 Q7 Inputs MR 9 PIN 14=VCC PIN 7 = GND Outputs MR CP DSA DSB Q0 Q1 ... Q7 L X X X L L … L H L L L Q0 ... Q6 H L H L Q0 ... Q6 H H L L Q0 ... Q6 H H H H Q0 ... Q6 H = high voltage level L = low voltage level X = don’t care 1 KK74LV164 MAXIMUM RATINGS* Symbol VCC Parameter DC supply voltage Value Unit -0.5 to + 7.0 V 1 DC Input diode current ±20 mA 2 DC Output diode current ±50 mA DC Output source or sink current ±25 mA ICC VCC current ±50 mA IGND GND current ±50 mA IIK * IOK * IO * 3 PD Tstg TL Power dissipation per package: * Plastic DIP SO 4 mW 750 500 Storage Temperature -65 to +150 °C 260 °C Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. *1 VI < -0.5 V or VI > VCC + 0.5 V. *2 VO < -0.5 V or VO > VCC + 0.5 V. *3 -0.5 V < VO < VCC + 0.5 V. *4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SO Package: : - 8 mW/°C from 70° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter DC Supply Voltage Min Max Unit 1.2 5.5 V VI Input Voltage 0 VCC V VO Output Voltage 0 VCC V TA Operating Temperature, All Package Types -40 +125 °C tr, tf Input Rise and Fall Time (Figure 1) 0 0 0 0 500 200 100 50 ns 1.0 V ≤ VCC < 2.0 V 2.0 V ≤ VCC < 2.7 V 2.7 V ≤ VCC < 3.6 V 3.6 V ≤ VCC ≤ 5.5 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74LV164 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test VCC conditions V Guaranteed Limit 25°C to -40°C 85°C Unit 125°C min max min max min max VIH HIGH level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - V VIL LOW level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 V VOH HIGH level output voltage VI = VIH or VIL IO = -100 µА 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.05 1.85 2.55 2.85 3.45 4.35 5.35 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - V VI = VIH or VIL IO = -6.0 mА 3.0 2.48 - 2.40 - 2.20 - V VI = VIH or VIL IO = -12.0 mА 4.5 3.70 - 3.60 - 3.50 - V VI = VIH or VIL IO = 100 µА 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.15 0.15 0.15 0.15 0.15 0.15 0.15 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 V VI = VIH or VIL IO = 6.0 mА 3.0 - 0.33 - 0.4 - 0.5 V VI = VIH or VIL IO = 12.0 mА 4.5 - 0.40 - 0.55 - 0.65 V Input current VI = VCC or 0 V 5.5 - ±0.1 - ±1.0 - ±1.0 µА ICC Supply current VI =VCC or 0 V IO = 0 µА 5.5 - 8.0 - 80 - 160 µА ICC1 Supply current VI =VCC – 0.6 V 2.7 3.6 - 0.2 - 0.5 - 0.85 mА VOL II LOW level output voltage 3 KK74LV164 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf= 2.5 ns, RL = 1 kΩ) Symbol Parameter tPHL, tPLH Propagation delay , CP to Qn Test VCC conditions V Guaranteed Limit 25°C to -40°C 85°C 125°C min max min max min max Unit VI = 0 V or V1 Figure 1 and 4 1.2 2.0 2.7 3.0 4.5 - 150 30 23 18 15 - 180 39 29 23 19 - 210 49 36 29 24 ns Propagation delay , MR to VI = 0 V or V1 Qn Figure 1 and 4 1.2 2.0 2.7 3.0 4.5 - 150 30 23 18 15 - 180 39 29 23 19 - 210 49 36 29 24 ns tw Pulse Width, CP or MR VI = 0 V or V1 Figure 1 1.2 2.0 2.7 3.0 4.5 100 28 21 17 14 - 130 34 25 20 17 - 160 41 30 24 20 - ns tsu Setup Time, DSA or DSB VI = 0 V or V1 to CP Figure 3 1.2 2.0 2.7 3.0 4.5 60 19 13 11 9 - 80 22 16 13 11 - 100 26 19 15 13 - ns th Hold Time, DSA or DSB to CP VI = 0 V or V1 Figure 3 1.2 2.0 2.7 3.0 4.5 50 5 5 5 5 - 50 5 5 5 5 - 50 5 5 5 5 - ns trec Recovery Time, MR to CP VI = 0 V or V1 Figure 2 1.2 2.0 2.7 3.0 4.5 70 15 11 9 8 - 100 19 14 11 10 - 130 24 18 14 12 - ns fmax Clock Frequency 1.2 2.0 2.7 3.0 4.5 - 2 16 22 27 32 - 1 14 19 24 27 - 1 12 16 20 24 MHz CI Input capacitance 5.0 - 7.0 - - - - pF CPD Power dissipation capacitance 5.5 - 80 - - - - pF tPHL VI = 0 V or V1 Figure 1 and 4 VI = 0 V or VCC 4 KK74LV164 tw tr CP VM 10% tf V1 90% (1) (2) MR GND (2) V1 (1) VM GND t PHL tw 1/fmax Q tPLH Q VM VM VOH (1) VOL t PHL VOH (1) t rec VOL Figure 1. Switching Waveforms (2) V1 (1) CP VM GND Figure 2. Switching Waveforms TEST POINT VALID DSA or DSB VM (2) V1 (1) DEVICE UNDER TEST GND t su CP th VM (2) V1 (1) OUTPUT RL * CL GND * Includes all probe and jig capacitance Figure 3. Switching Waveforms Figure 4. Test Circuit Note: (1) VM = 1.5 V at VCC = 2.7 V VM = 0.5 ⋅VCC at VCC =1.2 V, 2.0 V, 3.0 V, 4.5 V (2) V1 = VCC at VCC =1.2 V, 2.0 V, 2.7 V, 4.5 V V1 = 2.7 V at VCC = 3.0 V TIMING DIAGRAM CP DSA DSB MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 5 KK74LV164 N SUFFIX PLASTIC DIP (MS - 001AA) A Dimension, mm 8 14 B 7 1 Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE N G M K J H D 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 012AB) Dimension, mm A 14 8 H B 1 G P 7 R x 45 C -TK D SEATING PLANE M Symbol MIN MAX A 8.55 8.75 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 G 1.27 H 5.27 J 0° 8° K 0.1 0.25 1. Dimensions A and B do not include mold flash or protrusion. M 0.19 0.25 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. P 5.8 6.2 R 0.25 0.5 J 0.25 (0.010) M T C M NOTES: F 6