DA9276.003 13 July, 2006 MAS9276 IC for 10.00 – 30.00 MHz VCTCXO Very High Control Voltage Sensitivity True Sinewave Output Electrically Trimmable Very Low Phase Noise Low Power Low Cost • • • • • • DESCRIPTION To build a VCTCXO only a crystal is required in addition to MAS9276. The compensation method is fully analog, working continuously without generating any steps or other interference. MAS9276 is integrated circuit well suited to build VCTCXO for mobile communications. Temperature calibration is achieved at three calibration temperatures only. The trimming is done through a serial bus and the calibration information is stored in an internal PROM. This means that no rework for trimming is needed. FEATURES • • • • • APPLICATIONS Very small size Minimal current consumption Wide operating temperature range Phase noise <-120 dBc/Hz at 100 Hz offset Programmable Vc sensitivity • • VCTCXO for mobile phones VCTCXO for other telecommunications systems BLOCK DIAGRAM DA CLK PV CUB 4 INF 4 SENS 4 LIN 8 MAS9276 f(T) TE1 Σ f(T) T Vref TMux TE2 VC CDAC1 8 VDD OUT VSS X2 X1 1 (8) DA9276.003 13 July, 2006 PIN DESCRIPTION Pin Description Symbol x-coordinate y-coordinate Power Supply Voltage Programming Input Serial Bus Clock Input VDD PV CLK 166 420 979 1430 1435 1441 Serial Bus Data Input Temperature Output Test Multiplexer Output Voltage Control Input Crystal Oscillator Output Crystal/Varactor Oscillator Input Power Supply Ground Buffer Output DA TE1 TE2 VC X1 X2 VSS OUT 1234 1488 1742 185 439 1357 1790 2046 1441 1441 1441 153 149 149 166 153 Note: Because the substrate of the die is internally connected to GND, the die has to be connected to GND or left floating. Please make sure that GND is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Pad coordinates are measured from the left bottom corner of the chip to the center of the pads. The coordinates may vary depending on sawing width and location, however, distances between pads are accurate. ABSOLUTE MAXIMUM RATINGS (test conditions) Parameter Symbol Min Max Unit Supply Voltage Input Voltage Power Dissipation Storage Temperature VDD - VSS VIN PMAX TST -0.3 VSS -0.3 6.0 VDD + 0.3 20 150 V V mW o C -55 Note 1) Note 1: Not valid for programming pin PV RECOMMENDED OPERATION CONDITIONS Parameter Symbol Supply Voltage Supply Current Operating Temperature Storage Temperature VDD ICC TC TS Crystal Pulling Sensitivity Crystal Load Capacitance S CL Conditions Min Typ Max Unit 2.7 2.8 5.5 1.8 +85 +40 V mA o C o C Vdd = 2.8 Volt Relative humidity = 15%…70% -30 -5 30 10 ppm/pF pF 2 (8) Note DA9276.003 13 July, 2006 ELECTRICAL CHARACTERISTICS Parameter Symbol Min Typ Max Unit 10.00 30.00 MHz 0 Vdd Frequency Range fo Voltage Control Range VC Frequency vs. Supply Voltage dfo ±0.2 ppm 1) Frequency vs. Load Change dfo ±0.2 ppm 2) 3) Voltage Control Sensitivity (VCR = 0) VCSENS 11 25 ppm/V Voltage Control Sensitivity (VCR = 1) VCSENS 5 11 ppm/V Output Voltage (10kΩ // 10 pF) Vout Compensation Range ± 2.5 ppm TC 1.0 -30 Vpp 85 o C o C Compensation Range ± 2.0 ppm TC -25 75 Compensation Range Linear Part a1 -0.7 0.0 Compensation Inflection Point INF 25 31 Compensation Range Cubic Part a3 Compensation CDAC1 (8 Bit) C10 C10 + 18 TSTART 2 ppm/K o C ppm2/K3 95 CX1 Start up Time Note pF 4) ms Note 1: VDD within +/- 5% Note 2: R = 10 kohm +/- 10%, C = 10 pF +/- 10% Note 3: default Note 4: typ C10 = 13 pF IC OUTLINES VDD PV CLK DA TE1 TE2 1584 µm MAS9276 VC X1 X2 VSS OUT Die map reference 2204 µm Note 1: MAS9276 pads are round with 80 µm diameter at opening. Note 2: Pins CLK and DA can either be connected to VSS or left floating, pin PV can either be connected to VDD or left floating and pin TE1 must be left floating in VCTCXO module end-user application. Note 3: Die map reference is the actual left bottom corner of the sawn chip. 3 (8) DA9276.003 13 July, 2006 SAMPLES IN SB20 DIL PACKAGE 1 20OUT 2 19 3 18GND TE2 4 DA 6 MAS9276 YYWW XXXXX.X TE1 5 17 CLK 7 16X2 Top marking: YYWW = Year, Week XXXXX.X = Lot number 15 14X1 PV 8 13 VDD 9 12VC 10 11 DEVICE OUTLINE CONFIGURATION MSOP10 OUT DA VSS CLK X2 PV VDD 9276 AX YWW TE2 Top View X1 VC A = product version X = voltage version Y = year WW= week 4 (8) DA9276.003 13 July, 2006 PACKAGE (MSOP-10) OUTLINE e S See Detail A c B c1 b1 (b) E1 E1 B Section B - B E E 5-15 Degrees L1 Detail A A2A F AA A1 Land Pattern Recommendation Gauge Plane 0 - 8 Degrees L2 D Seating Plane N L G Symbol Min Nom Max Unit A A1 A2 b b1 c c1 D E E1 e F G L (Terminal length for soldering) L1 L2 M N S -0.00 0.75 0.15 0.15 0.08 0.08 --0.85 ---- 1.10 0.15 0.95 0.30 0.25 0.23 0.18 mm mm mm mm mm mm mm mm mm mm mm mm mm mm 0.40 3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 4.8 0.50 0.60 0.80 0.95 REF 0.25 BSC 0.41 1.02 0.50 mm mm mm Mm Dimensions do not include mold or interlead flash, protrusions or gate burrs. Reference Standard : JEDEC MO-187 BA. 5 (8) M DA9276.003 13 July, 2006 SOLDERING INFORMATION Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile According to RSH test IEC 68-2-58/20 2*220°C 240°C 2 Thermal profile parameters stated in JESD22-A113 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 µm, material Sn 85% Pb 15% Seating Plane Co-planarity Lead Finish EMBOSSED TAPE SPECIFICATIONS P1 T DO PO P2 E W F BO A AO KO D1 Section A-A User Direction of Feed Pin 1 Designator Dimension Min/Max Unit Ao Bo Do D1 E F Ko Po P1 P2 T W 5.00 ±0.10 3.20 ±0.10 1.50 +0.1/-0.0 1.50 min 1.75 5.50 ±0.05 1.45 ±0.10 4.0 8.0 ±0.10 2.0 ±0.05 0.3 ±0.05 12.00 +0.30/-0.10 mm mm mm mm mm mm mm mm mm mm mm mm 6 (8) DA9276.003 13 July, 2006 REEL SPECIFICATIONS W2 A D C Tape Slot for Tape Start N B W1 5000 Components on Each Reel Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative Carrier Tape Cover Tape End Start Trailer Dimension A B C D N W 1 (measured at hub) W 2 (measured at hub) Trailer Leader Weight Leader Components Min 1.5 12.80 20.2 50 12.4 Max Unit 330 mm mm mm mm mm mm mm mm mm 13.50 14.4 18.4 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape 1500 g 7 (8) DA9276.003 13 July, 2006 ORDERING INFORMATION Product Code Product Package Size MAS9276A1TG00 MAS9276A1SM06 IC FOR VCTCXO IC FOR VCTCXO EWS Tested wafers 215 µm MSOP-10/Top Marking A1 Die Size 2.204 x 1.584 mm Tape & Reel, 5.000 pcs/reel Contact Micro Analog Systems Oy for other wafer thickness options. LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 8 (8)