INDEX MX26C1000A 1M-BIT [128K x 8] CMOS MULTIPLE-TIME-PROGRAMMABLE-EPROM FEATURES • • • • • • • 128K x 8 organization +5V operating power supply +12.75V program/erase voltage Electric erase instead of UV light erase Fast access time: 70/90/100/120/150 ns Totally static operation Completely TTL compatible • • • • Operating current: 30mA Standby current: 100uA 100 minimum erase/program cycles Package type: - 32 pin PDIP - 32 pin SOP GY O L - 32 pin PLCC NO - 32 pin TSOP(I) ECH DT E ENT T A P GENERAL DESCRIPTION single pulse. The MX26C1000A supports an intelligent quick pulse programming algorithm which can result in a programming time of less than 30 seconds. PIN CONFIGURATIONS BLOCK DIAGRAM A7 1 32 CE 30 29 A13 A8 A9 MX26C1000A 9 25 OE A1 A10 A0 A0~A16 ADDRESS INPUTS A11 A2 CE 21 20 Q5 Q4 17 Q7 VCC GND . . . . . . . . Y-DECODER X-DECODER . . . . . . . . Y-SELECT 1M BIT CELL MAXTRIX VPP PIN DESCRIPTION TSOP A3 A2 A1 A0 Q0 Q1 Q2 GND Q3 Q4 Q5 Q6 Q7 CE A10 OE Q0~Q7 Q6 13 14 Q3 Q0 OUTPUT BUFFERS A14 A5 A4 CONTROL LOGIC OE A6 A3 This MTP EPROMTM is packaged in industry standard 32 pin dual-in-line packages, 32 pinPLCC packages or 32 pin TSOP packages and 32 pin SOP packages. NC VCC A16 A15 4 VPP 5 GND VCC PGM NC A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3 A12 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Q2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Q1 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND PLCC MX26C1000A PDIP/SOP PGM The MX26C1000A is a 12.75V/5V, 1M-bit MTP EPROMTM (Multiple Time Programmable Read Only Memory). It is organized as 128K words by 8 bits per word, operates from a + 5 volt supply, has a static standby mode, and features fast address location programming. It is designed to be reprogrammed and erased by an EPROM programmer or on-board. All programming/erasing signals are TTL levels, requiring a 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P/N: PM0454 MX261000A Patent#: US#5,526,307 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A4 A5 A6 A7 A12 A15 A16 VPP VCC PGM NC A14 A13 A8 A9 A11 1 SYMBOL PIN NAME A0~A16 Address Input Q0~Q7 Data Input/Output CE Chip Enable Input OE Output Enable Input VPP Program Supply Voltage NC No Internal Connection VCC Power Supply Pin (+5V) GND Ground Pin REV.1.5, FEB 10, 1998 INDEX MX26C1000A FUNCTIONAL DESCRIPTION ERASE MODE When the MX26C1000A is delivered, or it is erased, the chip has all 1000K bits in the "ONE", or HIGH state. "ZEROs" are loaded into the MX26C1000 through the procedure of programming. The MX26C1000A is erased by an EPROM programmer or in-system. The device is set up in erase mode when the A9 = VPP = 12.75V are applied, with VCC = 5V and PGM = VIL.(Algorithm shown in Figure 3). Erase time is around 1sec. If the erase is not verified, an additional erase processes will be repeated for a maximum of 200 times. PROGRAMMING MODE PROGRAMMING ALGORITHM The MX26C1000A is programmed by an EPROM programmer or on-board. The device is set up in the programming mode when the programming voltage VPP = 12.75V is applied, with VCC = 5 V and PGM = VIH (Algorithm shown in Figure 1). Programming is achieved by applying a single TTL low level 25us pulse to the PGM input after addresses and data lines are stable. If the data is not verified, additional pulses are applied for a maximum of 20 pulses. After the data is verified, one 25us pulse is applied to overprogram the byte so that program margin is assured. This process is repeated while sequencing through each address of the device. When programming is completed, the data at all the address is verified at VCC = VPP = 5V ± 10%. PROGRAM INHIBIT MODE Programming of multiple MX26C1000s in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX26C1000 may be common. A TTL low-level program pulse applied to an MX26C1000A CE input with VPP = 12.75 ± 0.25 V and PGM LOW will program that MX26C1000A. A high-level CE input inhibits the other MX26C1000A from being programmed. PROGRAM VERIFY MODE Verification should be performed on the programmed bits to determine that they were correctly programmed. Verification should be performed with OE and CE, at VIL, PGM at VIH, and VPP at its programming voltage. The VCC supply of the MXIC On-Board Programming Algorithm is designed to be 5V ± 10% particularly to faciliate the programming operation under the on-board application environment. But it can also be implemented in an industrial-standard EPROM programmer. ERASE VERIFY MODE Verification should be performed on the erased chip to determine that the whole chip(all bits) was correctly erased. Verification should be performed with OE and CE at VIL, PGM at VIH, and VCC = 5V, VPP = 12.5V COMPATIBILITY WITH MX27C1000 FAST PROGRAMMING ALGORITHM Besides the On-Board Programming Algorithm, the Fast Programming Algorithm of MX27C1000 also applies to MX26C1000A. MXIC Fast Algorithm is the conventional EPROM programming algorithm and is available in industrial-standard EPROM programmers. A user of industrial-standard EPROM programmer can choose either of the algorithms base on his preference. AUTO IDENTIFY MODE The auto identify mode allows the reading out of a binary code from an MTP that will identify its manufacturer and device type. This mode is intended for use by the programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the MX26C1000A. The device is set up in the fast programming mode when the programming voltage VPP = 12.75V is applted, with VCC = 6.25V and PGM = VIL(or OE = VIH)(Algorithm is shown in Figure 2). The programming is achieved by applying a single TTL low level 25~100us pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = VPP = 5V ± 10%. P/N: PM0454 Patent#: US#5,526,307 To activate this mode, the programming equipment must force 12.75V on address line A9 of the device. Two 2 REV.1.5, FEB 10, 1998 INDEX MX26C1000A This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode. Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX26C1000A, these two identifier bytes are given in the Mode Select Table. All identifiers for the manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. SYSTEM CONSIDERATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 uF bulk electrolytic capacitor should be used between VCC and GND for each of the eight devices. The location of the capacitor should be close to where the power supply is connected to the array. READ MODE The MX26C1000A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC - tOE. STANDBY MODE The MX26C1000A has a CMOS standby mode which reduces the maximum VCC current to 100 uA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The MX26C1000A also has a TTL-standby mode which reduces the maximum VCC current to 1.5 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. TWO-LINE OUTPUT CONTROL FUNCTION To accommodate multiple memory connections, a twoline control function is provided to allow for: 1. Low memory power dissipation, 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. P/N: PM0454 Patent#: US#5,526,307 3 REV.1.5, FEB 10, 1998 INDEX MX26C1000A MODE SELECT TABLE PINS MODE CE OE PGM A0 A9 VPP OUTPUTS Read VIL VIL X X X VCC DOUT Output Disable VIL VIH X X X VCC High Z Standby (TTL) VIH X X X X VCC High Z Standby (CMOS) VCC X X X X VCC High Z Program VIL VIH VIL X X VPP DIN Program Verify VIL VIL VIH X X VPP DOUT Erase VIL VIH VIL X VPP VPP HIGH Z Erase Verify VIL VIL VIH X X VPP DOUT Program Inhibit VIH X X X X VPP High Z Manufacturer Code VIL VIL X VIL VH VCC C2H Device Code(26C1000) VIL VIL X VIH VH VCC D2H NOTES: 1. VH = 12.0 V ± 0.5 V 2. X = Either VIH or VIL(For auto select) 3. A1 - A8 = A10 - A16 = VIL(For auto select) 4. See DC Programming Characteristics for VPP voltage during programming. FIGURE 1. PROGRAMMING FLOW CHART START ADDRESS = FIRST LOCATION VCC = 5V VPP = 12.75V X=0 PROGRAM ONE 25us PULSE INCREMENT X INTERACTIVE SECTION YES X = 20 ? NO FAIL VERIFY BYTE ? PROGRAM ONE 25us PULSE PASS NO LAST ADDRESS INCREMENT ADDRESS FAIL PROGRAM ONE 25us PULSE YES VCC = VPP = 5V VERIFY SECTION VERIFY ALL BYTES ? FAIL DEVICE FAILED PASS DEVICE PASSED P/N: PM0454 Patent#: US#5,526,307 4 REV.1.5, FEB 10, 1998 INDEX MX26C1000A FIGURE 2. COMPATIBILITY WITH MX27C1000 FAST PROGRAMMING FLOW CHART START ADDRESS = FIRST LOCATION VCC = 6.25V VPP = 12.75V X=0 PROGRAM ONE 25~100us PULSE INCREMENT X INTERACTIVE SECTION YES X = 25? NO FAIL VERIFY BYTE ? PASS NO LAST ADDRESS INCREMENT ADDRESS FAIL YES VCC = VPP = 5.25V VERIFY SECTION VERIFY ALL BYTES ? FAIL DEVICE FAILED PASS DEVICE PASSED P/N: PM0454 Patent#: US#5,526,307 5 REV.1.5, FEB 10, 1998 INDEX MX26C1000A FIGURE 3. ERASING MODE FLOW CHART START X=0 PROGRAM ALL "0" A9 = 12.75V VCC = 5V VPP = 12.75V CHIP ERASE (0.5s) A9 = VIL or VIH VCC = 5V VPP = 12.75V All Bits Verify NO FAIL ERASE VERIFY ? INCREMENT X X = 200 ? YES PASS CHIP ERASE (0.5s) DEVICE FAILED DEVICE PASSED P/N: PM0454 Patent#: US#5,526,307 6 REV.1.5, FEB 10, 1998 INDEX MX26C1000A SWITCHING TEST CIRCUITS 1.8K ohm DEVICE UNDER +5V TEST CL 6.2K ohm DIODES = IN3064 OR EQUIVALENT CL = 100 pF including jig capacitance(30pF for 70 ns parts) SWITCHING TEST WAVEFORMS 3.0V TEST POINTS 1.5V 1.5V 0V OUTPUT INPUT AC TESTING: (1) Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 10ns. (2) For MX26C1000A P/N: PM0454 Patent#: US#5,526,307 7 REV.1.5, FEB 10, 1998 INDEX MX26C1000A ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature 0oC to 70oC Storage Temperature -65oC to 125oC Applied Input Voltage -0.5V to 7.0V Applied Output Voltage -0.5V to VCC + 0.5V VCC to Ground Potential -0.5V to 7.0V A9 & Vpp -0.5V to 13.5V NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change. DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± 10% SYMBOL PARAMETER MIN. VOH Output High Voltage 2.4 VOL Output Low Voltage VIH Input High Voltage VIL MAX. UNIT CONDITIONS V IOH = -0.4mA 0.4 V IOL = 2.1mA 2.0 VCC + 0.5 V Input Low Voltage -0.3 0.8 V ILI Input Leakage Current -10 10 uA VIN = 0 to 5.5V ILO Output Leakage Current -10 10 uA VOUT = 0 to 5.5V ICC3 VCC Power-Down Current 100 uA CE = VCC ± 0.3V ICC2 VCC Standby Current 1.5 mA CE = VIH ICC1 VCC Active Current 30 mA CE = VIL, f=5MHz, Iout = 0mA IPP VPP Supply Current Read 100 uA CE = OE = VIL, VPP = 5.5V CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only) SYMBOL PARAMETER TYP. MAX. UNIT CONDITIONS CIN Input Capacitance 8 8 pF VIN = 0V COUT Output Capacitance 8 12 pF VOUT = 0V CVPP VPP Capacitance 18 25 pF VPP = 0V P/N: PM0454 Patent#: US#5,526,307 8 REV.1.5, FEB 10, 1998 INDEX MX26C1000A AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V± 10% 26C1000A 26C1000A -70 -90 SYMBOL PARAMETER MIN. tACC Address to Output Delay 70 tCE Chip Enable to Output Delay 70 tOE tDF Output Enable to Output Delay OE High to Output Float, tOH or CE High to Output Float Output Hold from Address, CE or OE which ever occurred firs 0 MAX. MIN. 35 20 MAX. 0 0 UNIT CONDITIONS 90 ns CE = OE = VIL 90 ns OE = VIL 40 25 ns ns CE = VIL 0 ns 26C1000A 26C1000A 26C1000A -10 -12 -15 SYMBOL PARAMETER MIN. tACC Address to Output Delay 100 tCE Chip Enable to Output Delay 100 tOE tDF Output Enable to Output Delay OE High to Output Float, tOH or CE High to Output Float Output Hold from Address, 0 CE or OE which ever occurred first 0 MAX. 45 30 MIN. 0 MAX. MIN. MAX. UNIT CONDITIONS 120 150 ns CE = OE = VIL 120 150 ns OE = VIL 65 50 ns ns CE = VIL 50 35 0 0 0 ns DC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5°C SYMBOL PARAMETER MIN. VOH Output High Voltage 2.4 VOL Output Low Voltage VIH Input High Voltage VIL MAX. UNIT CONDITIONS V IOH = -0.40mA 0.4 V IOL = 2.1mA 2.0 VCC + 0.5 V Input Low Voltage -0.3 0.8 V ILI Input Leakage Current -10 10 uA VH A9 Auto Select Voltage 11.5 12.5 V ICC3 VCC Supply Current (Program/Erase & Verify) 50 mA IPP2 VPP Supply Current(Program)/Erase 50 mA VIN = 0 to 5.5V CE = PGM = VIL, OE = VIH VCC2 Programming & Erase Supply Voltage 4.5 6.5 V VPP2 Programming & Erase Voltage 12.5 13.0 V IPP A9 A9 Auto Select Current /Erase 1 mA CE = PGM = VIL, OE = VIH P/N: PM0454 Patent#: US#5,526,307 9 REV.1.5, FEB 10, 1998 INDEX MX26C1000A AC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5oC SYMBOL PARAMETER MIN. MAX. tAS Address Setup Time 2.0 us tOES OE Setup Time 2.0 us tDS Data Setup Time 2.0 us tAH Address Hold Time 0 us tDH Data Hold Time 2.0 us tDFP CE to Output Float Delay 0 tVPS VPP Setup Time 2.0 tPW Program Pulse Width 20 tVCS VCC Setup Time 2.0 tDV Data Valid from CE tCES CE Setup Time tOE Data valid from OE tER Erase Recovery Time 0.5 s tPR Program Recovery Time 2 us tEW Erase Pulse Width 0.5 s tEV Erase Verify Time 200 ns tPV Program Verify Time 200 ns tA9S A9 Setup Time 2.0 us tPVS Program Verify Setup 2 us tEVS Erase Verify Setup 0.5 s 130 UNIT CONDITIONS ns us 105 us us 250 2.0 ns us 150 ns WAVEFORMS READ CYCLE ADDRESS INPUTS DATA ADDRESS tACC CE tCE OE tDF DATA OUT VALID DATA tOE P/N: PM0454 Patent#: US#5,526,307 tOH 10 REV.1.5, FEB 10, 1998 INDEX MX26C1000A PROGRAMMING WAVEFORMS PROGRAM ADDRESS INPUTS PROGRAM VERIFY VIH VALID ADDRESS VIL tAS DATA OUT DATA OUT VALID DATA IN STABLE tDH tDS VPP VPP VCC tVPS VCC+1 VCC VCC tVCS tPVS tPV VIH CE VIL tCES VIH PGM VIL tPR tPW VIH OE VIL ERASE WAVEFORMS Erase VPP ADDRESS INPUTS Erase Verify A9 VIH Others Not Care VIL DATA OUT OUT VPP VPP tVPS VCC tEVS VIH OE VIL tEV VIH CE VIL PGM VIH VIL P/N: PM0454 tER tCES Patent#: US#5,526,307 tEW 11 REV.1.5, FEB 10, 1998 INDEX MX26C1000A ORDERING INFORMATION PLASTIC PACKAGE PART NO. OPERATING CURRENT MAX.(mA) STANDBY CURRENT MAX.(uA) PACKAGE MX26C1000APC-70 70 30 100 32 Pin DIP MX26C1000AMC-70 70 30 100 32 Pin SOP MX26C1000AQC-70 70 30 100 32 Pin PLCC MX26C1000ATC-70 70 30 100 32 Pin TSOP MX26C1000APC-90 90 30 100 32 Pin DIP MX26C1000AMC-90 90 30 100 32 Pin SOP MX26C1000AQC-90 90 30 100 32 Pin PLCC MX26C1000ATC-90 90 30 100 32 Pin TSOP MX26C1000APC-10 100 30 100 32 Pin DIP MX26C1000AMC-10 100 30 100 32 Pin SOP MX26C1000AQC-10 100 30 100 32 Pin PLCC MX26C1000ATC-10 100 30 100 32 Pin TSOP MX26C1000APC-12 120 30 100 32 Pin DIP MX26C1000AMC-12 120 30 100 32 Pin SOP MX26C1000AQC-12 120 30 100 32 Pin PLCC MX26C1000ATC-12 120 30 100 32 Pin TSOP MX26C1000APC-15 150 30 100 32 Pin DIP MX26C1000AMC-15 150 30 100 32 Pin SOP MX26C1000AQC-15 150 30 100 32 Pin PLCC MX26C1000ATC-15 150 30 100 32 Pin TSOP P/N: PM0454 ACCESS TIME(ns) Patent#: US#5,526,307 12 REV.1.5, FEB 10, 1998 INDEX MX26C1000A PACKAGE INFORMATION 32-PIN PLASTIC DIP(600 mil) ITEM MILLIMETERS INCHES A 42.13 max. 1.660 max. B 1.90 [REF] .075 [REF] C 2.54 [TP] .100 [TP] D .46 [Typ.] .018 [Typ.] E 38.07 1.500 F 1.27 [Typ.] .050 [Typ.] G 3.30 ± .25 .130 ± .010 H .51 [REF] .020 [REF] I 3.94 ± .25 .155 ± .010 J 5.33 max. .210 max. K 15.22 ± .25 .600 ± .010 L 13.97 ± .25 .550 ± .010 M .25 [Typ.] .010 [Typ.] NOTE: 32 17 1 16 A K L F D Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition. C I J H G 0~15¡ M B E 32-PIN PLASTIC LEADED CHIP CARRIER (PLCC) A ITEM MILLIMETERS INCHES A 12.44 ± .13 .490 ± .005 B 11.50 ± .13 .453 ± .005 C 14.04 ± .13 .553 ± .005 D 14.98 ± .13 .590 ± .005 E 1.93 .076 F 3.30 ± .25 .130 ± .010 G 2.03 ± .13 .080 ± .005 H .51 ± .13 .020 ± .005 I 1.27 [Typ.] .050 [Typ.] J .71[REF] .028[REF] K L .46 [REF] 10.40/12.94 (W) (L) .018 [REF] .410/.510 (W) (L) M .89 R .035 R N .25 (TYP.) .010 (TYP.) NOTE: B 1 4 32 30 5 29 9 25 13 C D 21 14 20 17 E F G Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition. N H M I J K L P/N: PM0454 Patent#: US#5,526,307 13 REV.1.5, FEB 10, 1998 INDEX MX26C1000A PACKAGE INFORMATION 32-PIN PLASTIC TSOP ITEM MILLIMETERS A 20.0 ± .20 INCHES .078 ± .006 B 18.40 ± .10 .724 ± .004 C 8.20 max. .323 max. D 0.15 [Typ.] .006 [Typ.] E .80 [Typ.] .031 [Typ.] F .20 ± .10 .008 ± .004 G .30 ± .10 .012 ± .004 H .50 [Typ.] .020 [Typ.] I .45 max. .018 max. J 0 ~ .20 0 ~ .008 K 1.00 ± .10 .039 ± .004 L 1.27 max. .050 max. M .50 .020 N 19.00 .748 O 0~5 .500 NOTE: A B C O N M K L D E F H G I J Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at a maximum material condition. 32-PIN PLASTIC SOP (450 mil) ITEM MILLIMETERS INCHES A 20.95 max. .825 max. B 1.00 [REF] .039 [REF] C 1.27 [TP] .050 [TP] D .40 [Typ.] .016 [Typ.] E .05 min. .002 min. F 3.05 max. .120 max. G 2.69 ± .13 .106 ± .005 H 14.12 ± .25 .556 ± .010 I 11.30 ± .13 .445 ± .005 J 1.42 .056 K .20 [Typ.] .008 [Typ.] L .79 .031 NOTE: P/N: PM0454 Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition. Patent#: US#5,526,307 32 17 1 16 H A I G J F K E D C 14 B L REV.1.5, FEB 10, 1998 INDEX MX26C1000A Revision History Revision # 1.1 1.2 ` 1.3 1.4 1.5 Description Eraseing mode flow chart: Chip erase(5s)---> (1s). Programming waveforms: CE changed. MTP ROM----> MTP EPROM Chip erase(1s)---->0.5s. X = 60?--->200? Switching Test Waveforms revise. tEW Erase Pulse Width 1 sec---> 0.5sec Programming/erase waveforms modifiction. VPP: from 12.0~13V to 12.5~13V. Erase Verify Time: 60---->200. Change Part Name: 26C1000 ---> 26C1000A Change tPW:Min. 95us --> Min. 20us Programming flow chart revised. Date 4/10/1997 5/30/1997 7/25/1997 11/05/1997 2/10/1998 Mode Select Table, Erase Mode A9=VH-->A9=VPP. Erase flow chart revised. P/N: PM0454 Patent#: US#5,526,307 15 REV.1.5, FEB 10, 1998 INDEX MX26C1000A MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-8888 FAX:+886-3-578-8887 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-747-2309 FAX:+65-748-4090 TAIPEI OFFICE: TEL:+886-3-509-3300 FAX:+886-3-509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 16