MDTIC MDT10C5A2Q

MDT10C65
1. General Description
3. Applications
This ROM-Based 8-bit micro-controller
uses a fully static CMOS technology
process to achieve higher speed and
smaller size with the low power
consumption and high noise immunity. On
chip memory includes 4K words of ROM,
and 192 bytes of static RAM.
The application areas of this MDT10C65
range from appliance motor control and high
speed automotive to low power remote
transmitters/receivers
and
tele-communications processors, such as
Remote controller, small instruments, toy,
automobile and keyboard … etc.
2. Features
4. Pin Diagram
u
u
u
u
u
u
u
u
u
u
u
u
u
RISC CPU
Fully static design
37 single word instructions
4K x 14 program memory.
192 bytes RAM for data
35 bi-directional I/O
Eight level hardware stacks
Watchdog timer with on-chip RC
oscillator.
Interrupt capability
Timer0 : 8-bit timer with 8-bit
prescaler
Timer1 : 8-bit timer with 8-bit compare
register. This timer can be used as
carrier generator.
Sleep mode for power saving.
PB and PD with port change wake-up
interrupt.
PA6
/RES
PA0
PA1
PA2
PA3
PA4/T0CLK
PA5
PE0
PE1
PE2
VDD
VSS
OSC1
OSC2
PC0/T1OSCO
PC1/T1OSCI
PC2
PC3
PD0
PD1
This specification are subject to be changed without notice. Any latest information
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P. 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
2004/7
PA7
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0/IRQ
VDD
VSS
PD7
PD6
PD5
PD4
PC7
PC6
PC5
PC4
PD3
PD2
Ver. 1.1
MDT10C65
MDT10C65A1Q
MDT10C5A2Q
This specification are subject to be changed without notice. Any latest information
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P. 2
2004/12
Ver. 1.1
MDT10C65
5. Pin function description
Pin name Type Buffer type
OSC1
OSC2
/RES
I
O
I
ST
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
TTL
TTL
TTL
PB0/IQR
PB1
PB2
PB3
PB4
PB5
PB6
PB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0-PD7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
PE0
PE1
PE2
Vdd
I/O
I/O
I/O
ST
ST
ST
Vss
Description
Oscillator input
Oscillator out
Reset input with 130K ohm pull-up
Bi-directional I/O port A. Port A can be software
programmed for internal 45K ohm pull-up on all pins
except PA5. The pull-up resistance on PA5 is 100K ohm.
Can be clock input to Timer0.
Bi-directional I/O port B. Port B can be software
programmed for internal 25K ohm pull-up on all pins.
PB0-PB7 can generate interrupt on pin state change.
Can be the external interrupt pin.
Bi-directional I/O port C. Port C can be software
programmed for internal 100K pull-up on all pins.
Can be Timer1 oscillator output or Timer1 clock input.
Can be Timer1 oscillator input.
Bi-directional port. All pins can generate interrupt on pin
state change. Port D can be software programmed for
internal 100K pull-up on all pins.
Bi-directional port E. Port E can be software programmed
for internal 100K pull-up on all pins.
Power input
Ground pin
This specification are subject to be changed without notice. Any latest information
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P. 3
2004/12
Ver. 1.1
MDT10C65
6. Memory Mapping
6.2Register file map :
6.1Program memory :
0000h
0001h
0002h
0003h
0004h
Reset Vector
Peripheral interrupt
Vector
0005h
Program memory
(Page 0)
07FFh
0800h
Program memory
(Page 1)
0FFFh
BANK 0
IAR
RTCC
PCL
STATUS
MSR
PORT A
PORT B
PORT C
PORT D
PORT E
PCH
INTS
PIFB1
PIFB2
TMR1L
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
T1STA
11h
12h
13h
14h
15h
CCP1L
16h
17h CCP1CTL
18h
BANK 1
IAR
TMR
PCL
STATUS
MSR
CPIO A
CPIO B
CPIO C
CPIO D
CPIO E
PCH
INTS
PIEB1
PIEB2
PSTA
PPHE
1Fh
20h
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
9Fh
A0h
General
Purpose
Register
General
Purpose
Register
7Fh
FFh
Unimplemented memory location.
This specification are subject to be changed without notice. Any latest information
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P. 4
2004/12
Ver. 1.1
MDT10C65
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
Indirect addressing register
Timer0 register
Program counter low byte
Status register
Bit 0 : Carry
1 : Digit carry
2 : Zero flag
3 : Power-down
4 : WDT time-out
5 : Register bank select (For direct addressing)
=0 Bank 0 (00h-7Fh)
=1 Bank 1 (80h-FFh)
7-6 : Always read as zero.
Memory select register
Port A data register
Port B data register
Port C data register
Port D data register
Port E data register
Bit 2-0 – Port E data register.
7-3 – Unimplemented. Always set as 0.
Program memory segment register
Interrupt control register
Bit 0 – PB port change interrupt flag bit.
1 – PB0/IRQ external interrupt flag bit.
2 – Timer0 overflow interrupt flag bit.
3 – PB port change interrupt enable bit.
4 – PB0/IRQ external interrupt enable bit.
5 – Timer0 overflow interrupt enable bit.
6 – Peripheral interrupt enable bit.
7 – Global interrupt enable bit.
Peripheral interrupt flag register 1.
Bit 0 – Timer1 overflow interrupt flag bit
7-1 – Unimplemented. Always read as 0.
Peripheral interrupt flag register 2.
Bit 6-0 – Unimplemented. Read as zero.
7 – PD port change interrupt flag bit
Timer1 data register low byte.
Unimplemented..
This specification are subject to be changed without notice. Any latest information
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P. 5
2004/12
Ver. 1.1
MDT10C65
10
Timer1 control register
Bit 0 – Timer1 enable bit
1 – Timer1 clock source select
2 – Timer 1 external clock synchronization control bit
3 – Timer 1 oscillator enable control bit
5-4 – Timer 1 prescaler select bits
7-6 – Unimplemented. Always read as 0.
11-14 Unimplemented.
15
Timer1 compare register
16
Unimplemented.
17
Timer1 compare control register
Bit 7-1 –Unimplemented. Always set as 0.
0 – compare enable bit
18-1F Unimplemented.
20-7F General purpose register
80
Same as register 00.
81
TMR register
Bit 2-0 – Prescaler rate select bits
3 – Prescaler assign bit
4 – Timer 0 edge select bit
5 – Timer 0 clock source select bit
6 – PB0/IRQ interrupt edge select bit
7 – Port B pull-up enable bit.
82-84 Same as 02H-04H.
85
Port A data direction register.
86
Port B data direction register.
87
Port C data direction register.
88
Port D data direction register.
89
Port E data direction register.
Bit 2-0 – Port E data direction register.
7-3 – Unimplemented. Always set as 0.
8A -8B Same as 0AH-0BH.
8C
Peripheral interrupt control register 1.
Bit 0 – Timer1 overflow interrupt enable bit.
7-1 – Unimplemented. Always set these bits to 0.
8D
Peripheral interrupt control register 2
Bit 6-0 – Unimplemented.
7 – PD port change interrupt enable bit.
8E
Power control register.
This specification are subject to be changed without notice. Any latest information
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P. 6
2004/12
Ver. 1.1
MDT10C65
Bit 0 –Unimplemented. Always read as 0.
1 – Power-on reset status bit.
7-2 – Unimplemented. Always read as 0.
8F
Unimplemented.
90
PPHE register . ( “ 0 ” Enable ; “ 1 ” Disable )
Bit 0-3 – Unimplemented.
4 – PA port pull-up enable bit.
5 – PC port pull-up enable bit.
6 – PD port pull-up enable bit.
7 – PE port pull-up enable bit.
91-9F Unimplemented.
A0-FF General purpose register.
7. Timer1 CCP Mode
CCP1CTL
Enable
CCP1L
Input 1 / 2 Output
COMPARA
TOR
TMR1L
Clear TMR1L
PA7
TRISA< 7 >
PA7
Output Enable
Input
Output
Default
This specification are subject to be changed without notice. Any latest information
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P. 7
2004/12
Ver. 1.1
MDT10C65
8. Reset Condition for all Registers
Register
Power-On Reset,
Address
/MCLR or WDT Reset Wake-up from SLEEP
Power range
detector Reset
IAR
00h(80h)
0000 0000
0000 0000
uuuu uuuu
RTCC
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h(82h)
0000 0000
0000 0000
0000 0100
STATUS
03h(83h)
0001 1xxx
000# #uuu
000# #uuu
MSR
04h(84h)
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORT A
05h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORT B
06h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORT C
07h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORT D
08h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORT E
09h
---- -xxx
---- -uuu
---- -uuu
PCH
0Ah(8Ah)
---- 0000
---- 0000
---- uuuu
INTS
0Bh(8Bh)
0000 0001
0000 0001
uuuu uuuu
PIFB1
0Ch
---- ---x
---- ---u
---- ---u
PIFB2
0Dh
1--- ----
1--- ----
u--- ----
TMR1L
0Eh
xxxx xxxx
Uuuu uuuu
Uuuu uuuu
T1STA
10h
--00 0000
--00 0000
--uu uuuu
CCP1L
15h
Xxxx xxxx
uuuu uuuu
--uu uuuu
CCP1CTL
17h
---- ---0
---- ---0
---- ---u
TMR
81h
1111 1111
1111 1111
uuuu uuuu
CPIOA
85h
1111 1111
1111 1111
uuuu uuuu
CPIOB
86h
1111 1111
1111 1111
uuuu uuuu
CPIOC
87h
1111 1111
1111 1111
uuuu uuuu
CPIOD
88h
1111 1111
1111 1111
uuuu uuuu
CPIOE
89h
---- -111
---- -111
---- -uuu
PIEB1
8Ch
---- ---0
---- ---0
---- ---u
PIEB2
8Dh
0--- ----
0--- ----
u--- ----
PSTA
8Eh
---- --#-
---- --u-
---- --u-
PPHE
90h
1111 ----
1111 ----
uuuu ----
Note : u = unchanged,
x = unknown,
- = unimplemented, read as “0”
This specification are subject to be changed without notice. Any latest information
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P. 8
2004/12
Ver. 1.1
MDT10C65
# = value depends on the condition of the following table
Condition
Status
bit 4
Status
bit 3
PSTA
bit 1
POWR ON RESET
1
1
0
/MCLR reset (not during SLEEP)
u
u
u
/MCLR reset during SLEEP
1
0
u
WDT reset (not during SLEEP)
0
1
u
WDT reset during SLEEP
0
0
u
Interrupt Wake-up during SLEEP
1
0
u
9. Electrical Characteristics
(Operating temperature at 25℃).
Sym
Description
Condition
Vdd Operating voltage
VIL
VIH
IIL
Min
Typ
Max
Unit
2.3
5.5
V
Input Low Voltage
PA, PB, PC, PD, PE
Vdd=5V
-0.6
1.0
V
/RES
Vdd=5V
-0.6
1.0
V
PA, PB, PC, PD, PE
Vdd=5V
2.0
Vdd+0.6
V
/RES
Vdd=5V
3.0
Vdd+0.6
V
Input leakage current
Vdd=5V
+/-1
µA
Input high Voltage
VOL Output Low Voltage
PA0-PA3
Vdd=5V, IOL=15mA
2.6
V
PA4-PA7, PB, PC, PD, PE
Vdd=5V, IOL=20mA
0.5
V
Vdd=5V, IOL=5mA
0.2
V
Vdd=5V, IOH= -20mA
3.5
V
Vdd=5V, IOH= -5mA
4.5
V
PA0-PA4, PA6-PA7
Vdd=5V
45K
Ohm
PB
Vdd=5V
25K
Ohm
PA5, PC, PD, PE
Vdd=5V
100K
Ohm
VOH Output High Voltage
PA, PB, PC, PD, PE
RHi
Pull-up resistance
This specification are subject to be changed without notice. Any latest information
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P. 9
2004/12
Ver. 1.1
MDT10C65
10. Instruction Set
Instruction Code
Mnemonic
Operands
Function
Operation
Status
010000 00000000 NOP
010000 00000001 CLRWT
No operation
None
Clear Watchdog timer
0→WT
TF, PF
010000 00000010 SLEEP
Sleep mode
TF, PF
010000 00000011 TMODE
010000 00000rrr CPIO R
Load W to TMODE register
0→WT,
stop OSC
W→TMODE
Control I/O port register
W→CPIO
010001 1rrrrrrr STWR R
011000 trrrrrrr LDR R, t
Store W to register
W→R
Load register
R→t
Z
111010 iiiiiiii LDWI I
Load immediate to W
010111 trrrrrrr SWAPR R, t Swap halves register
I→W
None
[R(0~3) ↔
R(4~7)]→t
None
011001 trrrrrrr INCR R, t Increment register
011010 trrrrrrr INCRSZ R, t Increment register, skip if
zero
011011 trrrrrrr ADDWR R, t Add W and register
011100 trrrrrrr SUBWR R, t Subtract W from register
R + 1→t
Z
R + 1→t
None
W + R→t
C, HC, Z
R ﹣W→t
(R+/W+1→t)
C, HC, Z
011101 trrrrrrr DECR R, t
011110 trrrrrrr DECRSZ R,
t
010010 trrrrrrr ANDWR R, t
110100 iiiiiiii ANDWI i
Decrement register
R ﹣1→t
Z
Decrement register, skip if
zero
AND W and register
R ﹣1→t
None
R ∩ W→t
Z
AND W and immediate
i ∩ W→W
Z
R ∪ W→t
Z
i ∪ W→W
Z
R ♁ W→t
Z
010011 trrrrrrr IORWR R, t Inclu. OR W and register
110101 iiiiiiii IORWI i
Inclu. OR W and immediate
010100 trrrrrrr XORWR R, t Exclu. OR W and register
None
r
None
110110 iiiiiiii XORWI i Exclu. OR W and immediate i ♁ W→W
011111 trrrrrrr COMR R, t Complement register
/R→t
010110 trrrrrrr RRR R, t Rotate right register
R(n) →
R(n-1), C→
R(7),
R(0)→C
010101 trrrrrrr RLR R, t Rotate left register
R(n)→r(n+1),
010000 1xxxxxxx CLRW
Clear working register
This specification are subject to be changed without notice. Any latest information
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P. 10
C→R(0),
R(7)→C
0→W
2004/12
None
Z
Z
C
C
Z
Ver. 1.1
MDT10C65
Instruction Code
Mnemonic
Operands
Function
Operation
Status
010001 0rrrrrrr CLRR
R Clear register
0000bb brrrrrrr BCR
R, b Bit clear
0010bb brrrrrrr BSR R, b Bit set
0001bb brrrrrrr BTSC R, b Bit Test, skip if clear
0→R
0011bb brrrrrrr BTSS R, b Bit Test, skip if set
100nnn nnnnnnnn LCALL n Long CALL subroutine
Skip if R(b)=1 None
101nnn nnnnnnnn LJUMP
110001 iiiiiiii RTIW i
n
Long JUMP to address
Return, place immediate to
W
Add immediate to W
111000 iiiiiiii SUBWI
Subtract W from immediate
010000 00001001 RTFI
Return from interrupt
010000 00000100 RET
Return from subroutine
:
:
:
:
:
:
:
:
:
:
:
Working register
Watchdog timer
TMODE mode register
Control I/O port register
Timer overflow flag
Power loss flag
Program Counter
Oscillator
Inclusive ‘∪’
Exclusive ‘♁’
Logic AND ‘∩’
0→R(b)
None
1→R(b)
None
Skip if R(b)=0 None
110111 iiiiiiii ADDWI
Note :
W
WT
TMODE
CPIO
TF
PF
PC
OSC
Inclu.
Exclu.
AND
Z
n→PC,
PC+1→Stack
n→PC
None
Stack→PC,
i→W
PC+1→PC,
W+i→W
i-W→W
None
Stack→PC,
1→GIS
Stack→PC
None
C,HC,Z
C,HC,Z
None
None
b
t
0
1
R
C
HC
Z
/
x
i
:
:
:
:
:
:
:
:
:
:
:
Bit position
Target
Working register
General register
General register address
Carry flag
Half carry
Zero flag
Complement
Don’t care
Immediate data ( 8 bits )
n
:
Immediate address
This specification are subject to be changed without notice. Any latest information
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P. 11
2004/12
Ver. 1.1