MDT10P74 1. General Description -Port B<7:4> interrupt on change -CCP1, CCP2, SCM, USAR, USAT, PCM This EPROM-Based 8-bit micro-controller uses a fully static u CMOS technology process to achieve higher speed and -8 analog inputs multiplexed into one A/D smaller size with the low power consumption and high noise converter immunity. On chip memory includes 4K words of ROM, and -8-bit resolution u 192 bytes of static RAM. A/D converter module: TMR0 : 8-bit real time clock/counter TMR1 : 16-bit real time clock/count 2. Features TMR2 : 8-bit clock/counter(internal) u 4 types of oscillator can be selected by The followings are some of the features on the hardware programming option: and software : RC－Low cost RC oscillator u Fully CMOS static design LFXT－Low frequency crystal oscillator u 8-bit data bus XTAL－Standard crystal oscillator u On chip EPROM size : 4.0 K words HFXT－High frequency crystal oscillator u Internal RAM size : 238 bytes (192 general purpose registers, 46 special registers) u On-chip RC oscillator based Watchdog Timer(WDT) u 33 I/O pins with their own independent direction control u 37 single word instructions u 14-bit instructions u 8-level stacks u Operating voltage : 2.5 V ~ 5.5 V (PRD Disable) The application areas of this MDT10P74 range from 4.5 V ~ 5.5 V (PRD Enable) appliance motor control and high speed auto-motive to low 3. Applications u Operating frequency : DC ~ 20 MHz power remote transmitters/receivers, pointing devices, and u The most fast execution time is 200 ns under 20 telecommunications MHz in all single cycle instructions except the controller, small instruments, chargers, toy, automobile branch instruction and PC peripheral … etc. u processors, such Addressing modes include direct, indirect and relative addressing modes u Power-on Reset u Power edge-detector Reset u Power range-detector Reset u Sleep Mode for power saving u Capture, Compare, PWM module u Synchronous serial port with SCM u 12 interrupt sources: -External INT pin -TMR0 timer, TMR1 timer, TMR2 timer -A/D conversion completion This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 1 (Preliminary) 2005/6 Ver. 1.5 as Remote MDT10P74 4. Pin Assignment This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 2 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 5. Pin Function Description Pin Name I/O Function Description PA0~PA3, PA5 I/O Port A, TTL input level / Analog input channel RTCC/PA4 I/O Real Time Clock/Counter, Schmitt Trigger input levels Open drain output PB0~PB7 I/O Port B, TTL input level / PB0:External interrupt input , PB4~PB7:Interrupt on pin change PC0~PC7 I/O Port C, Schmitt Trigger input levels PD0~PD7 I/O Port D, Schmitt Trigger input levels / TTL input level PE0~PE2 I/O Port E, Schmitt Trigger input levels / TTL input level , Analog input channel /MCLR I Master Clear, Schmitt Trigger input levels OSC1/CLKIN I Oscillator Input/external clock input OSC2/CLKOUT O Oscillator Output/in RC mode， the CLKOUT pin has 1/4 frequency of CLKIN Vdd Power supply Vss Ground 6. Memory Map (A) Register Map Address Description BANK0 00 Indirect Addressing Register 01 RTCC 02 PCL 03 STATUS 04 MSR 05 Port A 06 Port B 07 Port C 08 Port D 09 Port E 0A PCHLAT This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 3 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 Address Description 0B INTS 0C PIFB1 0D PIFB2 0E TMR1L 0F TMR1H 10 T1STA 11 TMR2 12 T2STA 13 SCMBUF 14 SCMCTL 15 CCP1L 16 CCP1H 17 CCP1CTL 18 RCSC 19 TXREG 1A RCREG 1B CCP2L 1C CCP2H 1D CCP2CTL 1E ADRES 1F ADS0 20~7F General purpose register BANK1 01 TMR 05 CPIO A 06 CPIO B 07 CPIO C 08 CPIO D 09 CPIO E 0C PIEB1 0D PIEB2 0E PSTA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 4 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 Address Description 12 T2PER 14 SCMSTA 18 TXSC 19 BRREG 1F ADS1 A0~FF General purpose register (1)IAR (Indirect Address Register) ： R00 (2)RTCC (Real Time Counter/Counter Register) ： R01 (3) PC (Program Counter) ： R02,R0A Write PC --- from PCHLAT Write PC --- from PCHLAT LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK A11 A10~A8 A7~A0 Write PC --- from ALU LJUMP, LCALL --- from instruction word RTWI, RET, RTFI --- from STACK (4) STATUS (Status register) ： R03 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 /PF Power down Flag bit 4 /TF WDT Timer overflow Flag bit 5 RBS0 Register Bank Select bit ： 0 ： 00H --- 7FH(Bank0) 1 ： 80H --- FFH(Bank1) 7-6 —— General purpose bit This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 5 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 (5) MSR (Memory Bank Select Register) ： R04 Memory Bank Select Register ： 0 ： 00~7F(Bank0) 1 ： 80~FF(Bank1) b7 b6 b5 b4 b3 b2 b1 Indirect Addressing Mode (6) PORT A ： R05 PA5~PA0, I/O Register (7) PORT B ： R06 PB7~PB0, I/O Register (8) PORT C ： R07 PC7~PC0, I/O Register (9) PORT D ： R08 PD7~PD0, I/O Register (10) PORT E ： R09 PE2~PE0, I/O Register (11)PCHLAT ： R0A (12) INTS (Interrupt Status Register) ： R0B Bit Symbol Function 0 RBIF PORT B change interrupt flag. Set when PB <7：4> inputs change 1 INTF Set when INT interrupt occurs. INT interrupt flag. 2 TIF 3 RBIE Set when TMR0 overflows. 0 ： disable PB change interrupt 1 ： enable PB change interrupt 4 INTS 0 ： disable INT interrupt 1 ： enable INT interrupt This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 6 (Preliminary) 2005/6 Ver. 1.5 b0 MDT10P74 Bit Symbol 5 TIS Function 0 ： disable TMR0 interrupt 1 ： enable TMR0 interrupt 6 PEIE 0 ： disable all peripheral interrupt 1 ： enable all peripheral interrupt 7 GIS 0 ： disable global interrupt 1 ： enable global interrupt (13) PIFB1 (Peripheral Interrupt Flag Bit) ： R0C Bit Symbol 0 TMR1IF Function TMR1 interrupt flag 0 ： TMR1 did not overflow 1 ： TMR1 overflowed 1 TMR2IF TMR2 interrupt flag 0 ： No TMR2 to T2PER match occurred 1 ： TMR2 to T2PER match occurred 2 CCP1IF CCP1 interrupt flag 0 ： No TMR1 capture/compare occurred 1 ： A TMR1 capture/compare occurred 3 SCMIF SCM interrupt flag 0 ： Waiting SCM transmit/receive 1 ： The SCM transmission/reception is complete 4 TXIF USART transmit interrupt flag 0 ： The USART transmit buffer is full 1 ： The USART transmit buffer is empty 5 RCIF UASRT receive interrupt flag 0 ： The USART receive buffer is empty 1 ： The USART receive buffer is full 6 ADIF A/D interrupt flag 0 ： A/D conversion is not complete 1 ： A/D conversion completed 7 PCMIF PCM read/write interrupt flag 0 ： No read or write has occurred 1 ： A read or a write has occurred This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 7 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 (14) PIFB2 (Peripheral Interrupt Flag Bit) ： R0D Bit Symbol 0 CCP2IF Function CCP2 interrupt flag 0 ： No TMR1 capture/compare occurred 1 ： A TMR1 capture/compare occurred 7~1 -- Unimplemented (15) TMR1L ： R0E The LSB of the 16-bit TMR1 (16) TMR1H ： R0F The MSB of the 16-bit TMR1 (17) T1STA ： R10 Bit Symbol 0 TMR1ON Function 0 ： Stop TMR1 1 ： Enable TMR1 1 TMR1CLK 0 ： Internal clock (Fosc/4) 1 ： External clock from pin PC0 2 /T1SYNC TMR1CLK = 1 0 ： Synchronize external clock 1 ： Do not synchronize external clock TMR1CLK = 0 This bit is ignored 3 T1OSCEN 0 ： TMR1 Oscillator is shut off 1 ： TMR1 Oscillator is enable 5~4 T1CKPS1 1 1 = 1：8 Prescale value ~ 1 0 = 1：4 Prescale value T1CKPS0 0 1 = 1：2 Prescale value 0 0 = 1：1 Prescale value 7~6 -- Unimplemented (18) TMR2 ： R11 TMR2 register This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 8 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 (19) T2STA ： R12 Bit Symbol 1~0 T2CKPS1 0 0 = Prescaler is 1 ~ 0 1 = Prescaler is 4 T2CKPS0 1 x = Prescaler is 16 TMR2ON 0 ： TMR2 is off 2 Function 1 ： TMR2 is on 7~3 -- Unimplemented (20) SCMBUF ： R13 Serial communication port buffer (21) SCMCTL ： R14 Bit Symbol Function 3~0 SCM3 0 0 0 0 ： SCM master mode , clock = Fosc/4 ~ 0 0 0 1 ： SCM master mode , clock = Fosc/16 SCM0 0 0 1 0 ： SCM master mode , clock = Fosc/64 0 0 1 1 ： SCM master mode , clock = TMR2 output/2 0 1 0 0 ： SCM slave mode , clock = SCK pin , /SS control enable 0 1 0 1 ： SCM slave mode , clock = SCK pin , /SS control disable 4 CKS 0 ： Transmit happens on rising edge , receive on falling edge, Idle state for clock is low level. 1 ： Transmit happens on falling edge , receive on rising edge, Idle state for clock is high level 5 SCMEN 0 ： disable SCM, then PC3, PC4, PC5 is I/O port. 1 ： enable SCM 6 SCMROI 0 ： No overflow 1 ： Overflow 7 WCOL 0 ： No collision 1 ： The SCMBUF is written while it is still transmitting the previous word (22) CCP1L ： R15 Capture/Compare/PWM LSB (23) CCP1H ： R16 Capture/Compare/PWM MSB This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 9 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 (24) CCP1CTL ： R17 Bit Symbol 3~0 CCP1M3 Function 0 0 0 0 ： CCP1 off ~ 0 1 0 0 ： Capture1 mode , every falling edge CCP1M0 0 1 0 1 ： Capture1 mode , every rising edge 0 1 1 0 ： Capture1 mode , every 4th rising edge 0 1 1 1 ： Capture1 mode , every 16th rising edge 1 0 0 0 ： Compare1 mode , set output on match 1 0 0 1 ： Compare1 mode , clear output on match 1 0 1 0 ： Compare1 mode , generate software interrupt on match 1 0 1 1 ： Compare1 mode , trigger special event 1 1 x x ： PWM1 mode 5~4 7~6 PWM1LSB These bits are the two LSBs of the PWM1 duty cycle -- Unimplemented (25) RCSC ： R18 Bit Symbol Function 0 RX9DF 9th bit of received data 1 OERF 0 ： No overrun error 1 ： Overrun error 2 FERF 0 ： No framing error 1 ： Framing error 3 -- 4 CRENF Unimplemented 0 ： Disable continuous receive 1 ： Enable continuous receive 5 SRENF 0 ： Disable single receive 1 ： Enable single receive 6 RX9ENF 0 ： Select 8-bit reception 1 ： Select 9-bit reception 7 SPENF 0 ： Serial port disable 1 ： Serial port enable (26) TXREG ： R19 USART transmit register (27) RCREG ： R1A USART receive register This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 10 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 (28) CCP2L ： R1B Capture/Compare/PWM LSB (29) CCP2H ： R1C Capture/Compare/PWM MSB (30) CCP2CTL ： R1D Bit Symbol 3~0 CCP2M3 Function 0 0 0 0 ： CCP2 off ~ 0 1 0 0 ： Capture2 mode , every falling edge CCP2M0 0 1 0 1 ： Capture2 mode , every rising edge 0 1 1 0 ： Capture2 mode , every 4th rising edge 0 1 1 1 ： Capture2 mode , every 16th rising edge 1 0 0 0 ： Compare2 mode , set output on match 1 0 0 1 ： Compare2 mode , clear output on match 1 0 1 0 ： Compare2 mode , generate software interrupt on match 1 0 1 1 ： Compare2 mode , trigger special event 1 1 x x ： PWM2 mode 5~4 PWM2LSB These bits are the two LSBs of the PWM2 duty cycle 7~6 -- Unimplemented (31) ADRES ： R1E A/D result register (32) ADS0 ： R1F Bit Symbol 0 ADRUN Function 0 ： A/D converter module is shut off and consumes no operating current 1 ： A/D converter module is operating 1 -- 2 GO/DONEB Unimplemented 0：A/D conversion not in progress 1：A/D conversion in progress 5~3 CHS2~0 000 ： AIC0 001 ： AIC1 010 ： AIC2 011 ： AIC3 100 ： AIC4 101 ： AIC5 110 ： AIC6 111 ： AIC7 7~6 ASCS1-0 00 ： fosc/2 01： fosc/8 10 ： fosc/32 11 ： f RC (*Note) *Note： determined by OSC mode, HF： fosc/32 XT： fosc/8 RC： fosc/2 LF： fosc/2 (33) TMR (Time Mode Register) ： R81 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 11 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 Bit Symbol Function Prescaler Value 2~0 PS2~0 RTCC rate WDT rate 000 1 ： 2 1 ： 1 001 1 ： 4 1 ： 2 010 1 ： 8 1 ： 4 011 1 ： 16 1 ： 8 1 ： 32 1 ： 16 1 ： 64 1 ： 32 1 ： 128 1 ： 64 1 ： 256 1 ： 128 100 101 101 111 3 PSC 4 TCE 5 TCS 6 IES 7 PBPH Prescaler assignment bit ： 0 — RTCC 1 — Watchdog Timer RTCC signal edge ： 0 — Increment on low-to-high transition on RTCC pin 1 — Increment on high-to-low transition on RTCC pin RTCC signal set ： 0 — Internal instruction cycle clock 1 — Transition on RTCC pin Interrupt edge select 0 — Interrupt on falling edge on PB0 1 — Interrupt on rising edge on PB0 PORTB3~0 pull-hi 0 — PORTB3~0 pull-hi are enable 1 — PORTB3~0 pull-hi are disable (34) CPIO A (Control Port I/O Mode Register) ： R85 ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. (35) CPIO B (Control Port I/O Mode Register) ： R86 ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. (36) CPIO C (Control Port I/O Mode Register) ： R87 ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. (37) CPIO D (Control Port I/O Mode Register) ： R88 ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 12 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 (38) CPIO E (Control Port I/O Mode Register) ： R89 Bit Symbol Function 2~0 BIT 2 ~ BIT 0 Port E control port I/O mode bits 0 ： I/O pin in output mode 1 ： I/O pin in input mode 3 4 -- Unimplemented PCMMODE PCM mode select bit 0 ： General I/O mode 1 ： PCM mode 5 IBOV Input buffer overflow detect bit 0 ： No overflow occurred 1 ： Overflow 6 OBF Output buffer full status bit 0 ： The output buffer has been read 1 ： The output buffer has not been read 7 IBF Input buffer full status bit 0 ： No word has been received 1 ： A word has been received (39) PIEB1 ： R8C Bit Symbol 0 TMR1IE Function TMR1 interrupt enable bit 0 ： disable TMR1 interrupt 1 ： enable TMR1 interrupt 1 TMR2IE TMR2 interrupt enable bit 0 ： disable TMR2 interrupt 1 ： enable TMR2 interrupt 2 CCP1IE CCP1 interrupt enable bit 0 ： disable CCP1 interrupt 1 ： enable CCP1 interrupt 3 SCMIE SCM interrupt enable bit 0 ： disable SCM interrupt 1 ： enable SCM interrupt 4 TXIE USART transmit interrupt enable bit 0 ： disable the USART transmit interrupt 1 ： enable the USART transmit interrupt This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 13 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 Bit Symbol 5 RCIE Function USART receive interrupt enable bit 0 : disable the USART receive interrupt 1 : enable the USART receive interrupt 6 ADIE A/D interrupt enable bit 0 : disable A/D interrupt 1 : enable A/D interrupt 7 PCMIE PCM R/W interrupt enable bit 0 : disable the PCM interrupt 1 : enable the PCM interrupt (40) PIEB2 : R8D Bit Symbol 0 CCP2IE Function 0：disable CCP2 interrupt 1：enable CCP2 interrupt 7~1 -- Unimplemented (41) PSTA : R8E Bit 0 Symbol PRDB Function 0:Power range-detector Reset occurred 1:No Power range-detector Reset Occurred 1 PORB 0:Power on Reset occurred 1:No Power on Reset occurred (42) T2PER : R92 Timer2 period (43) SCMSTA : R94 Bit Symbol 0 BF Function 0 : Receive not complete 1 : Receive complete 7~1 -- Unimplemented (44) TXSC : R98 Bit Symbol Function 0 TX9DF 9th bit of transmit data 1 TSRCF 0 : TSR full 1 : TSR empty 2 HBRCF 0 : Low speed 1 : High speed This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 14 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 Bit Symbol 3 -- 4 UMSF Function Unimplemented 0 : USART asynchronous mode 1 : USART synchronous mode 5 TXENF 0 : Transmit disable 1 : Transmit enable 6 TX9ENF 0 : Select 8-bit reception 1 : Select 9-bit reception 7 CSSF 0 : Slave mode 1 : Master mode (45) BRREG : R99 Baud rate register (46) ADS1 ( A/D Status Register ) : R9F Bit Symbol Function 0 0 0 : PA0~3, PA5, PE0~2 = analog input, VREF = VDD 2~0 PAVM2~0 0 0 1 : PA0~2, PA5, PE0~2 = analog input, VREF = PA3 0 1 0 : PA0~3, PA5 = analog input, PE0~2 = digital I/O, VREF = VDD 0 1 1 : PA0~2, PA5 = analog input, PE0~2 = digital I/O, VREF = PA3 1 0 0 : PA0, 1, 3 = analog input, PA2, 5, PE0~2 = digital I/O, VREF = VDD 1 0 1 : PA0, 1 = analog input, PA2, 5, PE0~2 = digital I/O, VREF =PA3 1 1 x : PA0~3, 5, PE0~2 = digital I/O 7~3 -- Unimplemented (47) Configurable options for EPROM (Set by writer) : Oscillator Type RC Oscillator HFXT Oscillator XTAL Oscillator LFXT Oscillator Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 15 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 Power-range control Power-range disable Power-range enable Oscillator-start Timer control 0ms 75ms Power-edge Detect Security state PED Disable Security Disable PED Enable Security Enable (B) Program Memory Address 000-FFF Description Program memory 000 The starting address of power on, external reset or WDT time-out reset. 004 Interrupt vector 7. Reset Condition for all Registers Register Address Power-On Reset, Power range detector Reset IAR 00h N/A N/A N/A RTCC 01h xxxx xxxx uuuu uuuu uuuu uuuu 0Ah,02h 0000 0000 0000 0000 0000 0000 PC+1 STATUS 03h 0001 1xxx 000# #uuu 000# #uuu MSR 04h xxxx xxxx uuuu uuuu uuuu uuuu PORT A 05h --xx xxxx --uu uuuu --uu uuuu PORT B 06h xxxx xxxx uuuu uuuu uuuu uuuu PORT C 07h xxxx xxxx uuuu uuuu uuuu uuuu PORT D 08h xxxx xxxx uuuu uuuu uuuu uuuu PORT E 09h ---- -xxx ---- -uuu ---- -uuu PCHLAT 0Ah ---0 0000 ---0 0000 ---u uuuu PC /MCLR or WDT Reset Wake-up from SLEEP This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 16 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 Register Address Power-On Reset, Power range detector Reset /MCLR or WDT Reset Wake-up from SLEEP INTS 0Bh 0000 000x 0000 000u uuuu uuuu PIFB1 0Ch 0000 0000 0000 0000 uuuu uuuu PIFB2 0Dh ---- ---0 ---- ---0 ---- ---u TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1STA 10h --00 0000 --uu uuuu --uu uuuu TMR2 11h 0000 0000 0000 0000 uuuu uuuu T2STA 12h ---- -000 ---- -uuu ---- -uuu SCMBUF 13h xxxx xxxx uuuu uuuu uuuu uuuu SCMCTL 14h 0000 0000 0000 0000 uuuu uuuu CCP1L 15h xxxx xxxx uuuu uuuu uuuu uuuu CCP1H 16h xxxx xxxx uuuu uuuu uuuu uuuu CCP1CTL 17h --00 0000 --00 0000 --uu uuuu RCSC 18h 0000 -00x 0000 -00x uuuu -uuu TXREG 19h 0000 0000 0000 0000 uuuu uuuu RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu CCP2L 1Bh xxxx xxxx uuuu uuuu uuuu uuuu CCP2H 1Ch xxxx xxxx uuuu uuuu uuuu uuuu CCP2CTL 1Dh --00 0000 --00 0000 --uu uuuu ADRES 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADS0 1Fh 0000 00-0 0000 00-0 uuuu uu-u TMR 81h 1111 1111 1111 1111 uuuu uuuu CPIOA 85h --11 1111 --11 1111 --uu uuuu CPIOB 86h 1111 1111 1111 1111 uuuu uuuu CPIOC 87h 1111 1111 1111 1111 uuuu uuuu CPIOD 88h 1111 1111 1111 1111 uuuu uuuu CPIOE 89h 0000 -111 0000 -111 uuuu -uuu PIEB1 8Ch 0000 0000 0000 0000 uuuu uuuu PIEB2 8Dh ---- ---0 ---- ---0 ---- ---u PSTA 8Eh ---- --0u ---- --uu ---- --uu T2PER 92h 1111 1111 1111 1111 1111 1111 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 17 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 Register Address Power-On Reset, Power range detector Reset /MCLR or WDT Reset Wake-up from SLEEP SCMSTA 94h ---- ---0 ---- ---0 ---- ---u TXSC 98h 0000 -010 0000 -010 uuuu -uuu BRREG 99h 0000 0000 0000 0000 uuuu uuuu ADS1 9Fh ---- -000 ---- -000 ---- -uuu Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” #＝value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 PSTA: bit 1 PSTA: bit 0 /MCLR reset (not during SLEEP) u u u u /MCLR reset during SLEEP 1 0 u u WDT reset (not during SLEEP) 0 1 u u WDT reset during SLEEP 0 0 u u Power-on reset 1 1 0 x Power-range reset 1 1 u 0 Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” 8. Instruction Set : Instruction Code Mnemonic Operands Function Operating Status 010000 00000000 NOP No operation None 010000 00000001 CLRWT Clear Watchdog timer 0→WT TF, PF 010000 00000010 SLEEP Sleep mode 0→WT, stop OSC TF, PF 010000 00000011 TMODE Load W to TMODE register W→TMODE None 010000 00000100 RET Return from subroutine Stack→PC None 010000 00000rrr CPIO R Control I/O port register W→CPIO r None 010001 1rrrrrrr STWR R Store W to register W→R None 011000 trrrrrrr LDR R, t Load register R→t Z 111010 iiiiiiii LDWI I Load immediate to W I→W None 010111 trrrrrrr SWAPR R, t Swap halves register [R(0~3) ↔R(4~7)]→t None 011001 trrrrrrr INCR R, t Increment register R + 1→t Z 011010 trrrrrrr INCRSZ R, t Increment register, skip if zero R + 1→t None 011011 trrrrrrr ADDWR R, t Add W and register W + R→t C, HC, Z This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 18 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 Instruction Code Mnemonic Operands Function Operating Status 011100 trrrrrrr SUBWR R, t Subtract W from register R ﹣W→t or (R+/W+1 C, HC, Z →t) 011101 trrrrrrr DECR R, t Decrement register R ﹣1→t 011110 trrrrrrr DECRSZ R, t Decrement register, skip if zero R ﹣1→t 010010 trrrrrrr ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI i AND W and immediate i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI i Inclu. OR W and immediate i ∪ W→W Z 010100 trrrrrrr XORWR R, t Exclu. OR W and register R ♁ W→t Z 110110 iiiiiiii XORWI i Exclu. OR W and immediate i ♁ W→W Z 011111 trrrrrrr COMR R, t Complement register /R→t Z 010110 trrrrrrr RRR Rotate right register R(n) →R(n-1), C R, t Z None C→R(7), R(0)→C 010101 trrrrrrr RLR R, t Rotate left register R(n)→r(n+1), C C→R(0), R(7)→C 010000 1xxxxxxx CLRW Clear working register 0→W Z 010001 0rrrrrrr CLRR Clear register 0→R Z 0000bb brrrrrrr BCR R, b Bit clear 0→R(b) None 0010bb brrrrrrr BSR R, b Bit set 1→R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 100nnn nnnnnnnn LCALL n Long CALL subroutine n→PC, None R PC+1→Stack 101nnn nnnnnnnn LJUMP n Long JUMP to address n→PC 110111 iiiiiiii ADDWI i Add immediate to W W+i→W 110001 iiiiiiii RTWI Return, place immediate to W Stack→PC,i→W 111000 iiiiiiii SUBWI i Subtract W from immediate i-W→W 010000 00001001 RTFI Reture from interrupt Stack→PC,1→GIS i None C,HC,Z None C,HC,Z None Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ b t R C HC Z / x i : : 0 1 : : : : : : : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don’t care Immediate data ( 8 bits ) This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 19 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 n : Immediate address 9. Electrical Characteristics *Note: Temperature=25°C 1.Operation Current : (1) HF (C=10p) , WDT - disable, PRD – disable 4M 10M 20M Sleep 2.5V 330u 710u 1.3m <1u 3.0V 480u 910u 1.7m <1u 4.0V 720u 1.4m 2.8m <1u 5.0V 1.4m 2.6m 4.3m <1u 5.5V 1.8m 3.5m 5.7m <1u These parameters are for reference only. (2) XT (C=10p) , WDT - disable, PRD – disable 1M 4M 10M Sleep 2.5V 100u 310u 600u <1u 3.0V 220u 450u 860u <1u 4.0V 310u 660u 1.3m <1u 5.0V 560u 1.0m 1.9m <1u 5.5V 780u 1.5m 2.9m <1u These parameters are for reference only. (3) LF (C=10p) , WDT - disable, PRD - disable, 32K 455K 1M Sleep 2.5V 10u @2.7V 50u 80u <1u 3.0V 15u 60u 90u <1u 4.0V 25u 80u 150u <1u 5.0V 40u 140u 230u <1u 5.5V 80u 250u 390u <1u These parameters are for reference only. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 20 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 (4) RC, WDT - disable; PRD - disable; @Vdd = 5.0V C 3p 20p 100p 300p R Freq. Current 4.7k 8.4M 1.7m 10k 4.5M 1.1m 47k 1.1M 430u 100k 520K 330u 300k 180K 165u 470k 110K 155u 4.7k 3.2M 1.3m 10k 2.2M 640u 47k 500K 230u 100k 240K 180u 300k 81.2K 150u 470k 51.6K 145u 4.7k 1.4M 500u 10k 688K 370u 47k 152K 165u 100k 72.8K 150u 300k 24.4K 140u 470k 15.6K 138u 4.7k 592K 350u 10k 292K 190u 47k 64K 147u 100k 30.8K 141u 300k 10.4K 137u 470k 6.4K 136u These parameters are for reference only. 2. Input Voltage (Vdd = 5V) : Vil Port Min Max TTL Vss 0.8V Vss 0.6V 3.0V Vdd 3.8V Vdd Schmitt trigger Vih TTL Schmitt trigger These parameters are for reference only. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 21 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 Input Voltage (Vdd = 3V) : Port Min Max TTL Vss 0.4V Schmitt trigger Vss 0.2V TTL 2.0V Vdd Schmitt trigger 2.6V Vdd Vil Vih These parameters are for reference only. 3. Output Voltage (Vdd = 5V) : PA,PB Condition Voh 3.5V Ioh = -20mA Vol 0.9V Iol = 20mA Voh 4.2V Ioh = -5mA Vol 0.7V Iol = 5mA These parameters are for reference only. 4. Output Current (Max.) (Vdd = 5V) : I/O Port Current source current 25mA sink current 40mA These parameters are for reference only. 5. The basic WDT time-out cycle time : Time 2.5V 26 3.0V 23 4.0V 20 5.0V 18 5.5V 17 Unit = ms These parameters are for reference only. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 22 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 6. PRD : (1)PRD reset voltage : Voltage Vih 4.0±10% Vil 3.6±10% Unit = V These parameters are for reference only. (2) PRD reset current : Current 5.0V 120 4.0V 100 Unit = uA These parameters are for reference only. 7. Pull high resistor : Vdd PB3~0 Pull high 5V 3V 40 80 Unit = K Ohm These parameters are for reference only. 8. MCLR filter time : Vdd=5V time 640 Unit = ns These parameters are for reference only. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 23 (Preliminary) 2005/6 Ver. 1.5 MDT10P74 10.Block Diagram S ta ck 8 Le ve ls EP R OM 4Kx14 (MDT10P 74) R AM 192X8 P ort A P ortA P A0 ~ PA5 6 bits 12 bits 14 bits 12 bits P rogra m Counte rs Ins truction R e gis te r S pe cia l Re gis te r P ort B O S C1 D0~ D7 O S C2 MC LR Os cillator Circuit P ortB P B0 ~ PB7 8 bits Ins truction De coder Control C ircuit P ortC P o rtC P C 0~ P C 7 8 bits Da ta 8-bit P owe r on Re s e t P owe r Down R e s et Working R egis te r S ta tus Re gis te r ALU P ortD P o rtD P D0~ P D7 8 bits P owe r R a nge De te ctor A/D 8bit C ounte r / Time r0 Tim e r1 / Tim e r2 (CC P 1,CC P 2) P a ra lle l S la ve P ort / S e ria l P ort (S C M/US AR T) WDT/O S T Time r P ortE This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 24 (Preliminary) 2005/6 Ver. 1.5 Po rtE P E 0~ P E 2 3 bits