MDT10P7212 1. General Description -8 analog inputs multiplexed into one A/D converter This EPROM-Based 8-bit micro-controller uses a fully -10-bit resolution static CMOS technology process to achieve higher TMR0: 8-bit real time clock/counter speed and smaller size with the low power consumption TMR1: 16-bit real time clock/count and high noise immunity. On chip memory includes 4K TMR2: 8-bit clock/counter (internal) words of ROM, and 192 bytes of static RAM. 5 types of oscillator can be selected by programming option: 2. Features RC－Low cost RC oscillator LFXT－Low frequency crystal oscillator The followings are some of the features on the XTAL－Standard crystal oscillator hardware and software: HFXT－High frequency crystal oscillator Fully CMOS static design IRC－Internal 8MHz RC oscillator 8-bit data bus On-chip RC oscillator based Watchdog Timer On chip EPROM size: 4.0 K words (WDT) Internal RAM size: 192 bytes 18/20 I/O pins with their own independent direction 37 single word instructions control 14-bit instructions 8-level stacks 3. Applications Operating voltage: 2.5 V ~ 5.5 V (PRD Disable) 4.5 V ~ 5.5 V (PRD Enable) The application areas of this MDT10P7212 range from Operating frequency: DC ~ 20 MHz appliance motor control and high speed auto-motive to The most fast execution time is 200 ns under 20 low MHz in all single cycle instructions except the devices, and telecommunications processors, such as branch instruction Remote controller, small instruments, chargers, toy, Addressing modes include direct, indirect and automobile and PC peripheral … etc. power remote transmitters/receivers, relative addressing modes Power-on Reset Power edge-detector Reset Power range-detector Reset Sleep Mode for power saving Capture, Compare, PWM module 7 interrupt sources: -External INT pin -TMR0 timer, TMR1 timer, TMR2 timer -A/D conversion completion -Port B<7:4> interrupt on change -CCP1 A/D converter module: This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 1 2007/11 VER1.2 pointing MDT10P7212 4. Pin Assignment PE2/AIC7 1 PA0/AIC0 2 PA1/AIC1 3 PA2/AIC2 4 PA3/AIC3 5 PA5/AIC4 6 PA4/T0CKI/VPP 7 VSS 8 PB0 9 PB1 10 PB2 11 PB3 12 24 PE1/AIC6 23 22 21 20 19 18 17 16 15 14 13 PE0/AIC5 PC2/CCP1 PC1/T1OSC1 PC0/T1OSC2 PC4 PC3 VDD PB7 PB6 PB5 PB4 PE2/AIC7 1 PA0/AIC0 2 PA1/AIC1 3 PA2/AIC2 4 PA3/AIC3 5 PA5/AIC4 6 PA4/T0CKI/VPP 7 VSS 8 PB0 9 PB1 10 PB2 11 PB3 12 MDT10P7212K11 (SKINNY) MDT10P7212S11 (SOP) 24 PE1/AIC6 23 22 21 20 19 18 17 16 15 14 13 PE0/AIC5 PC2/CCP1 PC1/T1OSC1 PC0/T1OSC2 OSC1 OSC2 VDD PB7 PB6 PB5 PB4 MDT10P7212K12 (SKINNY) MDT10P7212S12 (SOP) 5. Order information Device ROM RAM I/O A/D Timer (words) (bytes) MDT10P7212K11 4K 192 MDT10P7212S11 4K MDT10P7212K12 MDT10P7212S12 CCP INRC Package (10 bits) (8/16) 22 8-channel 2/1 1 Yes SKINNY 192 22 8-channel 2/1 1 Yes SOP 4K 192 20 8-channel 2/1 1 No SKINNY 4K 192 20 8-channel 2/1 1 No SOP (8Mhz) 6. Pin Function Description Pin Name I/O PA0~PA3, PA5 I/O Function Description Port A, TTL input level Analog input channel PA4/T0CKI/VPP I/O Real Time Clock/Counter, Schmitt Trigger input levels Open drain output, Vpp input when programming PB0~PB7 I/O Port B, TTL input level/PB0: External interrupt input, PB4~PB7: Interrupt on pin change PC0~PC2 I/O Port C, Schmitt Trigger input levels OSC1/PC4 I, I/O Oscillator Input/external clock input PC4 in IRC mode This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 2 2007/11 VER1.2 MDT10P7212 Pin Name I/O Function Description OSC2/PC3 O, I/O Oscillator Output/in RC mode, the CLKOUT pin has 1/4 frequency of CLKIN PC3 in IRC mode PE0~PE2 I/O Port E, Schmitt Trigger input levels Analog input channel VDD Power supply VSS Ground 7. Memory Map (A) Register Map Address Description BANK0 00 Indirect Addressing Register 01 RTCC 02 PCL 03 STATUS 04 MSR 05 Port A 06 Port B 07 Port C 09 Port E 0A PCHLAT 0B INTS 0C PIFB1 0E TMR1L 0F TMR1H 10 T1STA 11 TMR2 12 T2STA 15 CCP1L 16 CCP1H This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 3 2007/11 VER1.2 MDT10P7212 Address Description 17 CCP1CTL 1E ADRESH, The ADRESH register is not a writable register. 1F ADS0 20~7F General purpose register BANK1 01 TMR 05 CPIO A 06 CPIO B 07 CPIO C 09 CPIO E 0C PIEB1 0D PIEB2 0E PSTA 12 T2PER 1E ADRESL, The ADRESL register is not a writable register. 1F ADS1 A0~FF General purpose register (1) IAR (Indirect Address Register): R00 (2) RTCC (Real Time Counter/Counter Register): R01 (3) PC (Program Counter): R02, R0A Write PC --- from PCHLAT Write PC --- from PCHLAT LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK A11 A10~A8 A7~A0 Write PC --- from ALU LJUMP, LCALL --- from instruction word RTWI, RET, RTFI --- from STACK This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 4 2007/11 VER1.2 MDT10P7212 (4) STATUS (Status register): R03 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 /PF Power down Flag bit 4 /TF WDT Timer overflow Flag bit 5 RBS0 Register Bank Select bit 0: 00h~7Fh (Bank0) 1: 80h~FFh (Bank1) 7-6 -- General purpose bit (5) MSR (Memory Bank Select Register): R04 Memory Bank Select Register: 0: 00h~7Fh (Bank0) 1: 80h~FFh (Bank1) b7 b6 b5 b4 b3 b2 b1 b0 Indirect Addressing Mode (6) PORT A: R05 PA5~PA0, I/O Register (7) PORT B: R06 PB7~PB0, I/O Register (8) PORT C: R07 PC4~PC0, I/O Register (9) PORT E: R09 PE2~PE0, I/O Register (10) PCHLAT: R0A (11) INTS (Interrupt Status Register): R0B Bit Symbol Function 0 RBIF PORT B change interrupt flag, Set when PB <7:4> inputs change 1 INTF Set when INT interrupt occurs 2 TIF Set when TMR0 overflows This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 5 2007/11 VER1.2 MDT10P7212 Bit Symbol 3 RBIE Function 0: Disable PB change interrupt 1: Enable PB change interrupt 4 INTS 0: Disable INT interrupt 1: Enable INT interrupt 5 TIS 0: Disable TMR0 interrupt 1: Enable TMR0 interrupt 6 PEIE 0: Disable all peripheral interrupt 1: Enable all peripheral interrupt 7 GIS 0: Disable global interrupt 1: Enable global interrupt (12) PIFB1 (Peripheral Interrupt Flag Bit): R0C Bit Symbol 0 TMR1IF Function TMR1 interrupt flag 0: TMR1 did not overflow 1: TMR1 overflowed 1 TMR2IF TMR2 interrupt flag 0: No TMR2 to T2PER match occurred 1: TMR2 to T2PER match occurred 2 CCP1IF CCP1 interrupt flag 0: No TMR1 capture/compare occurred 1: A TMR1 capture/compare occurred 5~3 -- 6 ADIF Unimplemented, read as ‘0’ A/D interrupt flag 0: A/D conversion is not complete 1: A/D conversion completed 7 -- Unimplemented, read as ‘0’ (13) TMR1L: R0E The LSB of the 16-bit TMR1 (14) TMR1H: R0F The MSB of the 16-bit TMR1 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 6 2007/11 VER1.2 MDT10P7212 (15) T1STA: R10 Bit Symbol 0 TMR1ON Function 0: Stop TMR1 1: Enable TMR1 1 TMR1CLK 0: Internal clock (Fosc/4) 1: External clock from pin PC0 2 /T1SYNC TMR1CLK = 1 0: Synchronize external clock 1: Do not synchronize external clock TMR1CLK = 0 This bit is ignored 3 T1OSCEN 0: TMR1 Oscillator is shut off 1: TMR1 Oscillator is enable 5~4 T1CKPS1 1 1 = 1:8 Prescale value ~ 1 0 = 1:4 Prescale value T1CKPS0 0 1 = 1:2 Prescale value 0 0 = 1:1 Prescale value 7~6 -- Unimplemented, read as ‘0’ (16) TMR2: R11 TMR2 register (17) T2STA: R12 Bit Symbol 1~0 T2CKPS1 0 0 = Prescaler is 1 ~ 0 1 = Prescaler is 4 T2CKPS0 1 x = Prescaler is 16 TMR2ON 0: TMR2 is off 2 Function 1: TMR2 is on 7~3 -- Unimplemented, read as ‘0’ (18) CCP1L: R15 Capture/Compare/PWM LSB (19) CCP1H: R16 Capture/Compare/PWM MSB This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 7 2007/11 VER1.2 MDT10P7212 (20) CCP1CTL: R17 Bit Symbol 3~0 CCP1M3 Function 0 0 0 0: CCP1 off ~ 0 1 0 0: Capture1 mode, every falling edge CCP1M0 0 1 0 1: Capture1 mode, every rising edge 0 1 1 0: Capture1 mode, every 4th rising edge 0 1 1 1: Capture1 mode, every 16th rising edge 1 0 0 0: Compare1 mode, set output on match 1 0 0 1: Compare1 mode, clear output on match 1 0 1 0: Compare1 mode, generate software interrupt on match 1 0 1 1: Compare1 mode, trigger special event 1 1 x x: PWM1 mode 5~4 7~6 PWM1LSB These bits are the two LSBs of the PWM1 duty cycle -- Unimplemented, read as ‘0’ (21) ADRESH: R1E A/D result register high byte, The ADRESH register is not a writable register. (22) ADS0 ( A/D Status Register ): R1F Bit Symbol 0 ADRUN Function 0: A/D converter module is shut off and consumes no operating current 1: A/D converter module is operating 1 2 -- Unimplemented, read as ‘0’ GO/DONEB 0: A/D conversion not in progress 1: A/D conversion in progress 5~3 CHS2~0 000: AIC0 001: AIC1 010: AIC2 011: AIC3 100: AIC4 101: AIC5 110: AIC6 111: AIC7 7~6 ASCS1~0 00: fosc/2 01: fosc/8 10: fosc/32 11: f RC (*Note) *Note: determined by OSC mode, HF: fosc/32, XT: fosc/8, RC: fosc/2, LF: fosc/2 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 8 2007/11 VER1.2 MDT10P7212 (23) TMR (Time Mode Register): R81 Bit Symbol Function Prescaler Value 2~0 PS2~0 3 PSC 4 TCE 5 TCS 6 IES 7 PBPH RTCC rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1 : 16 1 0 0 1 : 32 1 0 1 1 : 64 1 1 0 1 : 128 1 1 1 1 : 256 Prescaler assignment bit 0: RTCC 1: Watchdog Timer RTCC signal edge 0: Increment on low-to-high transition on RTCC pin 1: Increment on high-to-low transition on RTCC pin RTCC signal set 0: Internal instruction cycle clock 1: Transition on RTCC pin Interrupt edge select 0: Interrupt on falling edge on PB0 1: Interrupt on rising edge on PB0 PORTB7~0 pull-hi 0: PORTB7~0 pull-hi are enable 1: PORTB7~0 pull-hi are disable WDT rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 (24) CPIO A (Control Port I/O Mode Register): R85 ＝“0”, I/O pin in output mode ＝“1”, I/O pin in input mode (25) CPIO B (Control Port I/O Mode Register): R86 ＝“0”, I/O pin in output mode ＝“1”, I/O pin in input mode (26) CPIO C (Control Port I/O Mode Register): R87 ＝“0”, I/O pin in output mode ＝“1”, I/O pin in input mode This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 9 2007/11 VER1.2 MDT10P7212 (27) PIEB1: R8C Bit Symbol 0 TMR1IE Function TMR1 interrupt enable bit 0: Disable TMR1 interrupt 1: Enable TMR1 interrupt 1 TMR2IE TMR2 interrupt enable bit 0: Disable TMR2 interrupt 1: Enable TMR2 interrupt 2 CCP1IE CCP1 interrupt enable bit 0: Disable CCP1 interrupt 1: Enable CCP1 interrupt 5~3 -- 6 ADIE Unimplemented, read as ‘0’ A/D interrupt enable bit 0: Disable A/D interrupt 1: Enable A/D interrupt 7 -- Unimplemented, read as ‘0’ (28) PSTA: R8E Bit Symbol Function 0 PRDB 0: Power range-detector Reset occurred 1: No Power range-detector Reset Occurred 1 PORB 0: Power on Reset occurred 1: No Power on Reset occurred 7~2 -- Unimplemented, read as ‘0’ (29) T2PER: R92 Timer2 period (30) ADRESL: R9E A/D result register low byte, The ADRESL register is not a writable register. (31) ADS1 ( A/D Status Register ): R9F Bit 2~0 Symbol PAVM2~0 Function 0 0 0: PA0~3, PA5, PE0~2 = analog input, VREF = VDD 0 0 1: PA0~2, PA5, PE0~2 = analog input, VREF = PA3 0 1 0: PA0~3, PA5 = analog input, PE0~2 = digital I/O, VREF = VDD 0 1 1: PA0~2, PA5 = analog input, PE0~2 = digital I/O, VREF = PA3 1 0 0: PA0, 1, 3 = analog input, PA2, 5, PE0~2 = digital I/O, VREF = VDD 1 0 1: PA0, 1 = analog input, PA2, 5, PE0~2 = digital I/O, VREF = PA3 1 1 x: PA0~3, 5, PE0~2 = digital I/O 6~3 -- Unimplemented, read as ‘0’ This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 10 2007/11 VER1.2 MDT10P7212 Bit Symbol 7 ADFM Function A/D result format select 0: Left justified, bit 5~0 of ADRESL are read as “0” 1: Right justified, bit 7~2 of ADRESH are read as “0” (32) Configurable options for EPROM (Set by writer) Oscillator Type RC Oscillator HFXT Oscillator XTAL Oscillator LFXT Oscillator Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time Power-range control Power-range disable Power-range enable Oscillator-start Timer control 0ms 75ms Power-edge Detect Security state PED Disable Security Disable PED Enable Security Enable (B) Program Memory Address 000-FFF Description Program memory 000 The starting address of power on, external reset or WDT time-out reset 004 Interrupt vector This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 11 2007/11 VER1.2 MDT10P7212 8. Reset Condition for all Registers Register Address Power-On Reset, Power range detector Reset WDT Reset Wake-up from SLEEP IAR 00h N/A N/A N/A RTCC 01h xxxx xxxx uuuu uuuu uuuu uuuu 0Ah,02h 0000 0000 0000 0000 0000 0000 PC+1 STATUS 03h 0001 1xxx 000# #uuu 000# #uuu MSR 04h xxxx xxxx uuuu uuuu uuuu uuuu PORT A 05h --xx xxxx --uu uuuu --uu uuuu PORT B 06h xxxx xxxx uuuu uuuu uuuu uuuu PORT C 07h xxxx xxxx uuuu uuuu uuuu uuuu PCHLAT 0Ah ---0 0000 ---0 0000 ---u uuuu INTS 0Bh 0000 000x 0000 000u uuuu uuuu PIFB1 0Ch -000 0000 -000 0000 -uuu uuuu TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1STA 10h --00 0000 --uu uuuu --uu uuuu TMR2 11h 0000 0000 0000 0000 uuuu uuuu T2STA 12h ---- -000 ---- -uuu ---- -uuu CCP1L 15h xxxx xxxx uuuu uuuu uuuu uuuu CCP1H 16h xxxx xxxx uuuu uuuu uuuu uuuu CCP1CTL 17h --00 0000 --00 0000 --uu uuuu ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADS0 1Fh 0000 00-0 0000 00-0 uuuu uu-u TMR 81h 1111 1111 1111 1111 uuuu uuuu CPIOA 85h --11 1111 --11 1111 --uu uuuu CPIOB 86h 1111 1111 1111 1111 uuuu uuuu CPIOC 87h 1111 1111 1111 1111 uuuu uuuu PIEB1 8Ch -000 0000 -000 0000 -uuu uuuu PSTA 8Eh ---- --0u ---- --uu ---- --uu T2PER 92h 1111 1111 1111 1111 1111 1111 ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ADS1 9Fh 0--- -000 0--- -000 u--- -uuu PC Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 12 2007/11 VER1.2 MDT10P7212 #＝value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 PSTA: bit 1 PSTA: bit 0 WDT reset (not during SLEEP) 0 1 u u WDT reset during SLEEP 0 0 u u Power-on reset 1 1 0 x Power-range reset 1 1 u 0 Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” 9. Instruction Set Instruction Code Mnemonic Operands Function Operating Status 010000 00000000 NOP No operation None 010000 00000001 CLRWT Clear Watchdog timer 0→WT TF, PF 010000 00000010 SLEEP Sleep mode 0→WT, stop OSC TF, PF 010000 00000011 TMODE Load W to TMODE register W→TMODE None 010000 00000100 RET Return from subroutine Stack→PC None 010000 00000rrr CPIO R Control I/O port register W→CPIO r None 010001 1rrrrrrr STWR R Store W to register W→R None 011000 trrrrrrr LDR R, t Load register R→t Z 111010 iiiiiiii LDWI I Load immediate to W I→W None 010111 trrrrrrr SWAPR R, t Swap halves register [R(0~3) ↔R(4~7)]→t None 011001 trrrrrrr INCR R, t Increment register R + 1→t 011010 trrrrrrr INCRSZ R, t Increment register, skip if zero R + 1→t 011011 trrrrrrr ADDWR R, t Add W and register W + R→t 011100 trrrrrrr SUBWR R, t Subtract W from register R ﹣W→t or (R+/W+1 C, HC, Z →t) 011101 trrrrrrr DECR R, t Decrement register R ﹣1→t 011110 trrrrrrr DECRSZ R, t Decrement register, skip if zero R ﹣1→t 010010 trrrrrrr ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI i AND W and immediate i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI i Inclu. OR W and immediate i ∪ W→W Z 010100 trrrrrrr XORWR R, t Exclu. OR W and register R ♁ W→t Z 110110 iiiiiiii XORWI i Exclu. OR W and immediate i ♁ W→W Z 011111 trrrrrrr COMR R, t Complement register /R→t Z 010110 trrrrrrr RRR Rotate right register R(n) →R(n-1), C→R(7), R(0)→C C R, t Z None C, HC, Z Z None This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 13 2007/11 VER1.2 MDT10P7212 Instruction Code Mnemonic Operands Function Operating Status Rotate left register R(n)→r(n+1), C→R(0), R(7)→C C Clear working register 0→W Z Clear register 0→R Z R, b Bit clear 0→R(b) None R, b Bit set 1→R(b) None BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 100nnn nnnnnnnn LCALL n Long CALL subroutine n→PC, PC+1→Stack None 101nnn nnnnnnnn LJUMP n Long JUMP to address n→PC None 110111 iiiiiiii ADDWI i Add immediate to W W+i→W 110001 iiiiiiii RTWI Return, place immediate to W Stack→PC,i→W 111000 iiiiiiii SUBWI i Subtract W from immediate i-W→W 010000 00001001 RTFI Reture from interrupt Stack→PC,1→GIS 010101 trrrrrrr RLR 010000 1xxxxxxx CLRW 010001 0rrrrrrr CLRR 0000bb brrrrrrr BCR 0010bb brrrrrrr BSR 0001bb brrrrrrr R, t R i C,HC,Z None C,HC,Z None Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ b t : : 0 1 R : C : HC : Z : / : x : i : n : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don’t care Immediate data ( 8 bits ) Immediate address This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 14 2007/11 VER1.2