DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG SINGLE POWER SUPPLY DUAL OPERATIONAL AMPLIFIERS <R> DESCRIPTION The μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG are dual operational amplifiers which are designed to operate for a single power supply. It includes features of low-voltage operation, a common-mode input voltage that range from V− (GND) level, an output from a V− (GND) level that is determined by the output stage of class C pushpull circuit and a 50 μA(TYP.) constant current, and a low current consumption. In addition, this can operate at both positive and negative power supply and it can be extensively used in various amplifier circuits. The μ PC1251GR-9LG, μ PC1251MP-KAA which expands temperature type is suited for wide operating ambient temperature use, and μ PC358GR-9LG is used for general purposes. A DC parameter selection that is compatible to operational amplifiers is also available. μ PC451GR-9LG, μ PC324GR-9LG which are quad types with the same circuit configuration are also available as series of operational amplifiers. <R> FEATURES • Input Offset Voltage ±2 mV (TYP.) • Internal frequency compensation • Input Offset Current ±5 nA (TYP.) • Output short-circuit protection • Large Signal Voltage Gain 100000 (TYP.) • Small Package The mounting area is reduced to 40% or 66% compared to the conventional 8-pin plastic SOP as shown in the following diagram. Package Standard SOP TSSOP TSSOP (2.8 x 2.9) Subject part number μ PC1251G2, μ PC1251GR-9LG, μ PC1251MP-KAA μ PC358G2 μ PC358GR-9LG Outline comparison 6.5 5.2 (Mounting area ratio) (100%) 6.4 4.4 2.8 3.15 (60%) 4.0 2.9 (34%) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G17929EJ3V0DS00 (3rd edition) Date Published December 2007 NS Printed in Japan 2006, 2007 The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG <R> ORDERING INFORMATION Part Number μ PC1251GR-9LG-E1-A Note μ PC1251GR-9LG-E2-A Note Selected Grade Package Standard 8-pin plastic TSSOP (5.72 mm(225)) Package Type • 12 mm wide embossed taping • Pin 1 on draw-out side Standard 8-pin plastic TSSOP (5.72 mm(225)) • 12 mm wide embossed taping • Pin 1 at take-up side μ PC1251GR(5)-9LG-E1-A Note DC 8-pin plastic TSSOP (5.72 mm(225)) parameter selection μ PC1251GR(5)-9LG-E2-A Note DC • Pin 1 on draw-out side 8-pin plastic TSSOP (5.72 mm(225)) parameter selection μ PC1251MP-KAA-E1-A Note μ PC1251MP-KAA-E2-A Note Standard • 12 mm wide embossed taping • 12 mm wide embossed taping • Pin 1 at take-up side 8-pin plastic TSSOP (2.8 x 2.9) • 12 mm wide embossed taping • Pin 1 on draw-out side Standard 8-pin plastic TSSOP (2.8 x 2.9) • 12 mm wide embossed taping • Pin 1 at take-up side μ PC1251MP(5)-KAA-E1-A Note DC 8-pin plastic TSSOP (2.8 x 2.9) parameter selection μ PC1251MP(5)-KAA-E2-A Note DC • Pin 1 on draw-out side 8-pin plastic TSSOP (2.8 x 2.9) parameter selection μ PC358GR-9LG-E1-A Note μ PC358GR-9LG-E2-A Note Standard • 12 mm wide embossed taping • 12 mm wide embossed taping • Pin 1 at take-up side 8-pin plastic TSSOP(5.72 mm(225)) • 12 mm wide embossed taping • Pin 1 on draw-out side Standard 8-pin plastic TSSOP(5.72 mm(225)) • 12 mm wide embossed taping • Pin 1 at take-up side μ PC358GR(5)-9LG-E1-A Note DC 8-pin plastic TSSOP(5.72 mm(225)) parameter selection μ PC358GR(5)-9LG-E2-A Note DC • 12 mm wide embossed taping • Pin 1 on draw-out side 8-pin plastic TSSOP(5.72 mm(225)) parameter selection • 12 mm wide embossed taping • Pin 1 at take-up side Note Pb-free (This product does not contain Pb in the external electrode and other parts.) 2 Data Sheet G17929EJ3V0DS μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG EQUIVALENT CIRCUIT (1/2 Circuit) <R> PIN CONFIGURATION (Marking side) V+ 100 μ A 6 μA OUT1 6 μA II + Q7 Q4 Q1 II1 Q6 CC Q3 RSC OUT IN − Q11 Q10 Q8 8 V+ 7 OUT2 6 II2 5 IN2 1 Q5 Q2 1 − + 2 IN1 3 V− 4 2 + − Q13 Q12 Q9 50 μA V− <R> ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Parameter Symbol + Voltage between V and V − Note1 Differential Input Voltage Input Voltage Total Power Dissipation V −V μ PC1251MP-KAA, μ PC358GR-9LG, μ PC1251GR(5)-9LG μ PC1251MP(5)-KAA μ PC358GR(5)-9LG − VID Note2 Output applied Voltage + μ PC1251GR-9LG, Note3 Note4 Output Short Circuit Duration Note5 Unit −0.3 to +32 V ±32 V − − − + VI V − 0.3 to V + 32 VO V − 0.3 to V + 0.3 V PT 440 mW tS Indefinite s V Operating Ambient Temperature TA −40 to +125 −40 to +85 °C Storage Temperature Tstg −55 to +150 −55 to +125 °C Note1. Note that reverse connections of the power supply may damage ICs. + 2. The input voltage is allowed to input without damage or destruction independent of the magnitude of V . Either input signal is not allowed to go negative by more than 0.3 V. In addition, the input voltage that operates normally as an operational amplifier is within the Common Mode Input Voltage range of an electrical characteristic. 3. A range where input voltage can be applied to an output pin externally with no deterioration or damage to the feature (characteristic). The input voltage can be applied regardless of the electric supply voltage. This specification which includes the transition state such as electric power ON/OFF must be kept. 4. This is the value of when the glass epoxy substrate (size: 100 mm x 100 mm, thickness: 1 mm, 15% of the substrate area where only one side is copper foiled is filling wired) is mounted. Note that restrictions will be made to the following conditions for each product, and the derating ratio depending on the operating ambient temperature. μ PC1251GR-9LG: Derate at −5.5 mW/°C when TA > 69°C. (Junction − ambient thermal resistance Rth(J-A) = 183°C/W) μ PC1251MP-KAA: Derate at −4.8 mW/°C when TA > 58°C. (Junction − ambient thermal resistance Rth(J-A) = 208°C/W) μ PC358GR-9LG: Derate at −5.5 mW/°C when TA > 44°C. (Junction − ambient thermal resistance Rth(J-A) = 183°C/W) + 5. Short circuits from the output to V can cause destruction. Pay careful attention to the total power dissipation not to exceed the absolute maximum ratings, Note 4. Data Sheet G17929EJ3V0DS 3 μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG RECOMMENDED OPERATING CONDITIONS Parameter Symbol V Power Supply Voltage (Split) − Power Supply Voltage (V = GND) V ± MIN. MAX. Unit ±1.5 ±15 V +3 +30 V + TYP. <R> ELECTRICAL CHARACTERISTICS μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG (TA = 25°C, V+ = +5 V, V− = GND) Parameter Symbol Conditions MIN. RS = 0 Ω TYP. MAX. Unit ±2 ±7 mV Input Offset Voltage VIO Input Offset Current IIO ±5 ±50 nA IB 14 250 nA 1.2 mA Input Bias Current Note1 Large Signal Voltage Gain Circuit Current Note2 AV RL ≥ 2 kΩ ICC RL = ∞, IO = 0 A 25000 100000 0.7 Common Mode Rejection Ratio CMR 65 70 Supply Voltage Rejection Ratio SVR 65 100 Output Voltage Swing VO RL = 2 kΩ (Connect to GND) dB dB + V − 1.5 0 + V − 1.5 V Common Mode lnput Voltage Range VICM Output Source Current IO SOURCE VIN (+) = +1 V, VIN (−) = 0 V 20 40 mA Output Sink Current IO SINK1 VIN (−) = +1 V, VIN (+) = 0 V 10 20 mA IO SINK2 VIN (−) = +1 V, VIN (+) = 0 V, VO = 200 mV 12 50 μA 120 dB Channel Separation 0 V f = 1 to 20 kHz μ PC1251GR(5)-9LG, μ PC1251MP(5)-KAA, μ PC358GR(5)-9LG (TA = 25°C, V+ = +5 V, V− = GND) Parameter Symbol Input Offset Voltage VIO Input Offset Current IIO Input Bias Current Note1 Large Signal Voltage Gain Circuit Current Note2 Conditions MIN. RS = 0 Ω IB AV RL ≥ 2 kΩ ICC RL = ∞, IO = 0 A 50000 TYP. MAX. Unit ±2 ±3 mV ±5 ±50 nA 14 60 nA 0.9 mA 100000 0.7 Common Mode Rejection Ratio CMR 65 70 Supply Voltage Rejection Ratio SVR 65 100 Output Voltage Swing VO RL = 2 kΩ (Connect to GND) dB dB + V − 1.5 0 + V − 1.4 V Common Mode lnput Voltage Range VICM Output Source Current IO SOURCE VIN (+) = +1 V, VIN (−) = 0 V 30 40 mA Output Sink Current IO SINK1 VIN (−) = +1 V, VIN (+) = 0 V 15 20 mA IO SINK2 VIN (−) = +1 V, VIN (+) = 0 V, VO = 200 mV 30 50 Channel Separation 0 V f = 1 to 20 kHz 70 120 μA dB Notes1. The input bias current flows in the direction where the IC flows out because the first stage is configured with a PNP transistor. 2. This is a current that flows in the internal circuit. This current will flow irrespective of the channel used. 4 Data Sheet G17929EJ3V0DS μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG <R> TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, TYP.) (Reference value) ICC vs. V+ PT vs. TA 2 RL = ∞ IO = 0 A μP G 58 C3 G 9L R- 300 ICC - Supply Current - mA 400 LG -9 R G 51 12 A PC KA μ P1M 25 C1 500 μP PT - Total Power Dissipation - mW 600 200 With 100 mm x 100 mm, thickness 1 mm glass epoxy 100 1.5 TA = 25°C 125°C 1 0.5 −40°C substrate (refer to "ABSOLUTE MAXIMUM RATINGS Note 4" ) 0 0 20 40 60 80 0 100 120 140 0 TA - Operating Ambient Temperature - °C 10 30 40 − V - Power Supply Voltage - V (V = GND) VIO vs. V+ VIO vs. TA 3 VIO - Input Offset Voltage - mV 3 VIO - Input Offset Voltage - mV 20 + 2 1 0 -1 -2 2 1 0 -1 V+ = +5 V, V− = GND each 5 samples data -2 -3 -3 0 10 20 30 -50 40 0 50 100 150 V+ - Power Supply Voltage - V (V− = GND) TA - Operating Ambient Temperature - °C IB vs. V+ IB vs. TA 30 30 IB - Input Bias Current - nA IB - Input Bias Current - nA V+ = +15 V 20 10 0 V− = GND 20 10 0 0 10 + 20 30 40 − V - Power Supply Voltage - V (V = GND) Data Sheet G17929EJ3V0DS -50 0 50 100 150 TA - Operating Ambient Temperature - °C 5 μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG AV vs. V+ IO SHORT vs. TA 160 IO SHORT − RL = 20 kΩ + AV - Voltage Gain - dB IO SHORT - Output Short Current - mA 70 60 50 40 120 2 kΩ 80 40 30 0 -20 0 20 40 60 0 80 10 20 30 40 V+ - Power Supply Voltage - V (V− = GND) TA - Operating Ambient Temperature - °C AV, φ vs. f AV - Voltage Gain - dB, φ - Phase Margin - deg. 140 V ± = ±15 V 120 ±15 V φ 100 ±7.5 V AV 80 ±2.5 V ±7.5 V 60 ±2.5 V 40 20 0 0.1 1 10 100 1k 10 k 100 k 1M f - Frequency - Hz VO vs. f 100 kΩ 1 kΩ 15 +15 V − +7 V + VIN VO 2 kΩ 10 5 0 1k 3 5 10 k 30 50 100 k 3005001 M CMR - Common Mode Rejection Ratio - dB VO - Output Voltage Signal - Vp-p 20 CMR vs. f 120 100 f - Frequency - Hz 6 80 60 40 20 0 100 1k 10 k 100 k f - Frequency - Hz Data Sheet G17929EJ3V0DS 1M μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG SR - TA 0.4 4 RL ≥ 2 kΩ V + = +15 V 3 SR - Slew Rate - V/μs VIN - Input Voltage - V VO - Output Voltage - V PULSE RESPONSE 2 1 0 3 2 SR + 0.2 0.1 V ± = ±15 V VO = ±10 V 1 20 0 40 60 0 -50 80 ΔVO vs. IO SOURCE 5 V+ ΔVO - Output Voltage to V+ - V 25°C V+ 125°C V+ /2 0.01 0.01 100 VO vs. IO SINK V+ = +15 V 0.1 50 TA - Operating Ambient Temperature - °C TA = −40°C 1 0 t - time - μs 10 VO - Output Voltage - V SR − 0.3 0.1 1 IO SINK − + VO 10 100 4 V+ /2 ΔVO + − IO SOURCE 3 TA = −40°C 2 25°C 1 125°C 0 0.01 0.1 1 10 100 IO SOURCE - Output Source Current - mA IO SINK - Output Sink Current - mA Data Sheet G17929EJ3V0DS 7 μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG <R> PRECAUTIONS FOR USE O The process of unused circuits If there is an unused circuit, the following connection is recommended. Process example of unused circuits V+ V+ R − + R V− To potentials within the range of common-mode input voltage (VICM) V− Remark A midpoint potential of V+ and V− is applied to this example. O Ratings of input/output pin voltage When the voltage of input/output pin exceeds the absolute maximum rating, it may cause degradation of characteristics or damages, by a conduction of a parasitic diode within an IC. In addition, when the input pin may be lower than V−, or the output pin may exceed the power supply voltage, it is recommended to make a clump circuit by a diode whose forward voltage is low (e.g.: Schottky diode) for protection. O Range of common-mode input voltage When the supply voltage does not meet the condition of electrical characteristics, the range of common-mode input voltage is as follows. VICM (TYP.): V− to V+ − 1.5 (V) (TA = 25°C) During designing, temperature characteristics for use with allowance. O The maximum output voltage The range of the TYP. value of the maximum output voltage when the supply voltage does not meet the condition of electrical characteristics is as follows: VOm+ (TYP.): V+ − 1.5 (V) (TA = 25°C), VOm− (TYP.) (IO SINK ≤ 50 μA): Approx. V− (V) (TA = 25°C) During designing, consider variations in characteristics and temperature characteristics for use with allowance. In addition, also note that the output voltage range (VOm+ − VOm−) becomes narrow when an output current increases. O Operation of output This IC consist an output level of a class C push-pull. Therefore, when a load resistance is connected to the midpoint potential of V+, V−, a crossover distortion occurs at the transition state of output current flow direction (source, sink). O Handling of ICs When stress is added to ICs due to warpage or bending of a board, the characteristic fluctuates due to piezoelectric effect. Therefore, pay attention to warpage or bending of a board. 8 Data Sheet G17929EJ3V0DS μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG PACKAGE DRAWINGS (Unit: mm) 8-PIN PLASTIC TSSOP (5.72mm (225)) D D1 detail of lead end A3 5 8 c θ L Lp 4 1 (UNIT:mm) e ZD b x M S HE A E A2 S y S A1 NOTE Each lead centerline is located within 0.10mm of its true position at maximum material condition. L1 ITEM D DIMENSIONS 3.15±0.15 D1 3.00±0.10 E 4.40±0.10 HE 6.40±0.20 A 1.20 MAX. A1 0.10±0.05 A2 1.00±0.05 A3 0.25 b +0.06 0.24 −0.05 c 0.145±0.055 L 0.50 Lp 0.60±0.15 L1 θ 1.00±0.20 3° +5° −3° e 0.65 x 0.10 y 0.10 ZD Data Sheet G17929EJ3V0DS 0.60 P8GR-65-9LG 9 μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG <R> 8-PIN PLASTIC TSSOP(2.8x2.9) D1 D detail of lead end 5 8 A3 E θ 4 1 Lp A HE A2 L1 S e A1 b S y S c x M S ZD (UNIT:mm) ITEM DIMENSIONS D D1 2.90 3.00 ± 0.20 E NOTE Each lead centerline is located within 0.10 mm of its true position at maximum material condition. 2.80 e 4.00 ± 0.20 0.65 b 0.22 ± 0.05 HE A 1.03 MAX. A1 0.08 ± 0.05 A2 0.85 ± 0.05 A3 L1 0.25 c Lp x y ZD 0.60 ± 0.20 0.145 + 0.05 0.03 0.37 ±0.10 0.10 0.10 + 5° 3° 3° 0.525 P8MP-65-KAA NEC Electronics Corporation 2006 10 Data Sheet G17929EJ3V0DS μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG <R> RECOMMENDED SOLDERING CONDITIONS The μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Type of Surface Mount Device μ PC1251GR-9LG-A μ PC358GR-9LG-A Note , μ PC1251GR(5)-9LG-A Note μ PC1251MP-KAA-A , μ PC358GR(5)-9LG-A Note , Note Note , μ PC1251MP(5)-KAA-A : 8-pin plastic TSSOP (5.72 mm (225)) Note : 8-pin plastic TSSOP (2.8 x 2.9) Process Infrared ray reflow Conditions Symbol Peak temperature: 260°C, Reflow time: 60 seconds or less (at 220°C or higher), IR60-00-3 Maximum number of reflow processes: 3 times. Wave soldering Solder temperature: 260°C or below, Flow time: 10 seconds or less, Maximum WS60-00-1 number of flow processes: 1 time, Pre-heating temperature: 120°C or below (Package surface temperature). Partial heating method Pin temperature: 350°C or below, P350 Heat time: 3 seconds or less (Per each side of the device). Note Pb-free (This product does not contain Pb in external electrode and other parts.) Caution Apply only one kind of soldering condition to a device, except for “partial heating method”, or the device will be damaged by heat stress. Remark Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. <R> REFERENCE DOCUMENTS Document Name Document No. QUALITY GRADES ON NEC SEMICONDUCTOR DEVICES C11531E SEMICONDUCTOR DEVICE MOUNT MANUAL http://www.necel.com/pkg/en/mount/index.html NEC SEMICONDUCTOR DEVICE RELIABILITY/QUALITY CONTROL IEI-1212 SYSTEM-STANDARD LINEAR IC REVIEW OF QUALITY AND RELIABILITY HANDBOOK C12769E NEC SEMICONDUCTOR DEVICE RELIBIALITY/QUALITY CONTROL C10983E SYSTEM Data Sheet G17929EJ3V0DS 11 μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG • The information in this document is current as of December, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1