SM5819HQF 6-channel DSD-PCM Converter OVERVIEW The SM5819HQF is a 6-channel DSD data (64fs) to 4fs, 2fs or fs PCM data converter. During conversion, decimation filtering is performed using a filter with selectable fixed coefficients (3 sets). Also, DSD inputs and PCM outputs are available for use in master/slave clock mode operation, in a wide range of system configurations, making it easy to construct a multi-channel DSD/PCM reproduction system. VSS EXIFLR EXICSW EXISLR EXILRCK EXIBCK VDDH EXIMCK VSS MCK TOUT2 VDDL 36 35 34 33 32 31 30 29 28 27 26 25 17 MCKOUT DIRDSCK 45 16 VSS SYNC 46 15 FMTPCM INIT 47 14 DIRPCK VSS 48 13 VDDL PACKAGE DIMENSIONS (Unit: mm) 9 ± 0.4 + 0.075 0.125 − 0.025 7 ± 0.1 Multi-channel SA-CD players SA-CD-compatible AV amplifiers 1.4 ± 0.1 ■ 7 ± 0.1 APPLICATIONS ■ ORDERING INFORMATION Device Package SM5819HQF 48 -pin QFP VSS 12 44 TOUT1 11 VDDH DSISR TEST3 10 18 9 43 TEST2 PBCK DSISL 8 19 TEST1 42 7 PLRCK DSISW VDDH 20 6 41 XMTPCM POSLR DSICT 5 21 DSGAIN 40 0.5 0.08 0.5 ± 0.2 ■ POCSW DSIFR 1.7 MAX ■ 22 9 ± 0.4 ■ 39 0 ~ 10 0.1 ■ ■ POFLR DSIFL 4 ■ VSS 23 SELEXT ■ 24 38 3 ■ 37 SEL4FS ■ VDDL DSBCK 2 ■ (Top view) 1 ■ 512fs (22.5792MHz, fs = 44.1kHz), 1:2 to 2:1 duty master clock DSD input and PCM output clock master/slave switching 3-system external data input (3-wire format), PCM output data/BCK/LRCK external input and internal filter output switching (BCK and LRCK are common to all 3 external PCM data inputs) Decimation filter coefficients • Fixed coefficients: 4fs-1/2fs-1/fs-1 PCM output mute operation PCM output format: [MSB-first left-justified 32bit] or [IIS 32-bit] (IIS 32-bit output bit clock frequency = 64 × word clock frequency) FIR filter coefficients • 64fs → 4fs/2fs/fs: 960th-order (6-channel) • ROM coefficients: 24 valid data bits (4-bit MSB extension at 4fs, 5-bit MSB extension at 2fs/fs) +6dB DSD gain switching function External/Internal system clock output switching 3.3V (3.0 to 3.6V) and 2.5V (2.3 to 2.7V) power supplies −40 to 85°C operating temperature range 48-pin QFP package VDDL ■ PINOUT SEL1FS FEATURES + 0.09 0.18 − 0.05 NIPPON PRECISION CIRCUITS INC.—1 SM5819HQF PIN DESCRIPTION No. Name I/O Property1 Input voltage 1 VDDL − − 2.5V Core power supply 2 SEL1FS I PD 3.3V PCM output rate select 1 L: 2fs/4fs, H: fs 3 SEL4FS I PD 3.3V PCM output rate select 2 L: 2fs, H: 4fs 4 SELEXT I PD 3.3V fs/2fs/4fs output and external data output select L: fs/2fs/4fs data, H: external data (EXI**) 5 DSGAIN I PD 3.3V DSD signal gain setting L: 100% modulation = 0dB, H: 50% modulation = 0dB 6 XMTPCM I PD 3.3V PCM output mute control input L: Mute ON, H: Mute OFF 7 VDDH − − 3.3V I/O power supply 8 TEST1 I PD 3.3V Test input 1 (must be open or tie LOW for normal operation) 9 TEST2 I PD 3.3V Test input 2 (must be open or tie LOW for normal operation) 10 TEST3 I PD 3.3V Test input 3 (must be open or tie LOW for normal operation) 11 TOUT1 O − − Test output 1 12 VSS − − − Ground 13 VDDL − − 2.5V Core power supply 14 DIRPCK I PD 3.3V PCM output PBCK/PLRCK I/O select L: Output (master mode), H: Input (slave mode) 15 FMTPCM I PD 3.3V PCM output format select L: MSB-first left-justified 32-bit, H: IIS 32-bit 16 VSS − − − Ground 17 MCKOUT O 12mA − System clock output (selected by SELEXT) Description 18 VDDH − − 3.3V I/O power supply 19 PBCK I/O S, 6mA 3.3V PCM output BCK bit clock 20 PLRCK I/O S, 6mA 3.3V PCM output LRCK word clock 21 POSLR O 2mA − PCM data output: surround left/right-channel 22 POCSW O 2mA − PCM data output: center/subwoofer channel 23 POFLR O 2mA − PCM data output: front left/right-channel 24 VSS − − − Ground 25 VDDL − − 2.5V 26 TOUT2 O − − 27 MCK I − 3.3V 28 VSS − − − 29 EXIMCK I − 3.3V Core power supply Test output 2 Master clock input: 512fs (22.5792MHz, fs = 44.1kHz) Ground External system clock input 30 VDDH − − 3.3V I/O power supply 31 EXIBCK I S 3.3V External PCM data BCK bit clock input 32 EXILRCK I S 3.3V External PCM data LRCK word clock input 33 EXISLR I − 3.3V External PCM data input: surround left/right-channel 34 EXICSW I − 3.3V External PCM data input: center/subwoofer channel 35 EXIFLR I − 3.3V External PCM data input: front left/right-channel 36 VSS − − − 37 VDDL − − 2.5V Core power supply 38 DSBCK I/O S, 6mA 3.3V DSD data input bit clock. Controlled by DIRDSCK Ground NIPPON PRECISION CIRCUITS INC.—2 SM5819HQF No. Name I/O Property1 Input voltage 39 DSIFL I − 3.3V DSD data input: front left-channel 40 DSIFR I − 3.3V DSD data input: front right-channel Description 41 DSICT I − 3.3V DSD data input: center channel 42 DSISW I − 3.3V DSD data input: subwoofer channel 43 DSISL I − 3.3V DSD data input: surround left-channel 44 DSISR I − 3.3V DSD data input: surround right-channel 45 DIRDSCK I PD 3.3V DSBCK I/O select L: input (slave), H: output (master) 46 SYNC I S, PU 3.3V Forced synchronization input (active-HIGH edge) Initialization input: Active-LOW, Resync on “L” → “H” 47 INIT I S, PU 3.3V 48 VSS − − − Ground 1. S = Schmitt, PU = pull-up resistor, PD = pull-down resistor, mA = output current NIPPON PRECISION CIRCUITS INC.—3 SM5819HQF BLOCK DIAGRAM DSIFL DSIFR DSICT PCM MUTE DSISL DSISR DSISW PCM I/F FIR FILTER and DOWN SAMPLING UNIT DSGAIN SEL1FS FMTPCM SEL4FS ROM 24bit 1440word (fs 480w) (2fs 480w) (4fs 480w) POFLR INT/EXT. DATA SELECT XMTPCM POCSW EXIFLR EXISLR EXICSW SELEXT EXILRCK EXIBCK EXIMCK PLRCK INT/EXT. CLOCK SELECT SYNC INIT DIRDSCK DSBCK MCK TEST1 TEST2 TEST3 POSLR PBCK MCKOUT CLOCK GENERATOR and TIMING CONTROL DIRPCK (Internal Clocks) TEST CONTROL TOUT1 TOUT2 NIPPON PRECISION CIRCUITS INC.—4 SM5819HQF SPECIFICATIONS Absolute Maximum Ratings VSS = 0V Parameter Symbol Rating Unit Supply voltage 1 VDDH –0.3 to 4.0 V Supply voltage 2 VDDL –0.3 to 3.0 V Input voltage (3.3V) VIN –0.3 to VDDH + 0.5 V Power dissipation PD 200 mW TSTG –55 to 125 °C Symbol Rating Unit Supply voltage 1 VDDH 3.0 to 3.6 V Supply voltage 2 VDDL 2.3 to 2.7 V Operating temperature TOPR –40 to 85 °C Storage temperature range Recommended Operating Conditions VSS = 0V Parameter DC Electrical Characteristics VDDH = 3.0 to 3.6V, VDDL = 2.3 to 2.7V, VSS = 0V, TOPR = –40 to 85°C unless otherwise noted. Parameter Current consumption 1 Current consumption 2 Input voltage Schmitt-trigger voltage Pin Symbol VDDH IDDH Rating Condition All pins no load VDDL IDDL “H" level (*1) VIH VDDH = 3.6V “L" level (*1) VIL VDDH = 3.0V Positive (*2) VT+ Unit min typ max – – 5 mA – – 60 mA 2.0 – – V – – 0.8 V 1.1 – 2.4 V (*2) VT– 0.6 – 1.8 V (*2) VH 0.1 – – V "H" level (*3) VOH IOH = –2mA (Type1) IOH = –6mA (Type2) IOH = –12mA (Type3) VDDH – 0.4 – – V "L" level (*3) VOL IOL = +2mA (Type1) IOL = +6mA (Type2) IOL = +12mA (Type3) – – 0.4 V (*1, 2) ILI –5 – 5 µA Pull-down resistor (*4) RPD VI = VDDH 60 120 288 kΩ Pull-up resistor (*5) RPU VI = VSS 60 120 288 kΩ Negative Hysteresis voltage Output voltage Input leakage current Pin summary (*1) Input pins and bidirectional (input/output) pins in input mode (*2) Inputs with Schmitt characteristic and bidirectional (input/output) pins in input mode (*3) Output pins and bidirectional (input/output) pins in output mode Type 3: MCKOUT Type 2: DSBCK, PBCK, PLRCK Type 1: Outputs excluding those above (*4) Inputs with pull-down resistor (*5) Inputs with pull-up resistor NIPPON PRECISION CIRCUITS INC.—5 SM5819HQF AC Electrical Characteristics VDDH = 3.0 to 3.6V, VDDL = 2.3 to 2.7V, VSS = 0V, TOPR = –40 to 85°C, fs = 44.1kHz unless otherwise noted. When DSBCK and PLRCK clocks are supplied by external clock input, their frequencies are related to the MCK input frequency by the following frequency divider ratios. (DSBCK) cycle = 8 × MCK cycle (64fs) (PLRCK) cycle [4fs mode] = 128 × MCK cycle (4fs) (PLRCK) cycle [2fs mode] = 256 × MCK cycle (2fs) (PLRCK) cycle [fs mode] = 512 × MCK cycle (fs) System clock ■ MCK pin Rating Parameter Symbol Unit min typ max "H"-level pulsewidth tMCWH 13 – – ns "L"-level pulsewidth tMCWL 13 – – ns Pulse cycle tMCY 40 44.29 (1/512fs) – ns Rise/fall time t r , tf – – 10 ns tMCY tMCWH tMCWL 0.9VDDH 0.5VDDH 0.1VDDH MCK tr tf External system clock ■ EXIMCK pin Rating Parameter Symbol Unit min typ max "H"-level pulsewidth tECWH 13 – – ns "L"-level pulsewidth tECWL 13 – – ns Pulse cycle tECY 40 – – ns Rise/fall time ter , tef – – 10 ns tECY tECWH tECWL EXIMCK ter tef 0.9VDDH 0.5VDDH 0.1VDDH NIPPON PRECISION CIRCUITS INC.—6 SM5819HQF DSD input ■ ■ DSBCK pin DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins Rating Parameter Symbol Unit min typ max DSD clock pulsewidth tDSCW 150 177.16 – ns DSD clock pulse cycle tDSCY 300 354.31 (1/64fs) – ns DSD data setup time tDSS 50 – – ns DSD data hold time tDSH 50 – – ns tDSCY tDSCW tDSCW DSBCK tDSS tDSH DSI** DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins Note. DSD clock pulsewidth and DSD clock pulse cycle when DSBCK is in input mode. Note. The data, with DSBCK timing above, enters the internal circuits on the falling edge of the MCK clock. Consequently, if the timing changes, the circuit must be resynchronized using INIT or SYNC. NIPPON PRECISION CIRCUITS INC.—7 SM5819HQF PCM output ■ PLRCK, PBCK, POFLR, POSLR, POCSW pins Rating Parameter Symbol Unit min typ max 40 44.29 – ns 40 88.58 – ns fs 40 177.15 – ns 4fs 80 88.58 (1/256fs) – ns 80 177.15 (1/128fs) – ns 80 354.31 (1/64fs) – ns 4fs BCK clock pulsewidth BCK clock pulse cycle 2fs tPBCW 2fs tPBCY fs Word CK setup time tPLBS 30 – – ns Word CK hold time tPLBH 10 – – ns Bit CK data delay time tPBDLY 0 – 15 ns Word CK data delay time tPLDLY 0 – 15 ns tPBCY tPBCW tPBCW PBCK tPLBH tPLBS PLRCK tPLDLY tPBDLY PO** PO**: POFLR, POSLR, POCSW pins Note. The PCM output relationship applies when the external inputs (EXI**) are not in through mode. Note. fs/2fs/4fs bit clock and word clock relationship applies when PBCK and PLRCK are in input mode. NIPPON PRECISION CIRCUITS INC.—8 SM5819HQF Clock outputs ■ MCKOUT, DSBCK, PLRCK, PBCK pins Rating Parameter Symbol Unit min typ max MCKOUT output delay time tCKODLY 0 – 10 ns Word/bit clock output delay time tCKDLY 0 – 10 ns tTHDLY MAX Unit MCK tCKODLY tCKODLY MCKOUT tCKDLY Word/Bit clock outputs Note. Applies when MCK clock is output on MCKOUT in through mode. Note. Applies when each word/bit clock on DSBCK, PBCK, PLRCK is in output mode. Through-mode output ■ MCKOUT, PBCK, PLRCK, POFLR, POSLR, POCSW pins Through inputs Through outputs Condition EXIMCK MCKOUT 10 ns EXIBCK PBCK 10 ns EXIWCK PLRCK 10 ns PCM outputs with external inputs selected EXIFLR POFLR 15 ns EXISLR POSLR 15 ns EXICSW POCSW 15 ns Through mode input tTHDLY tTHDLY Through mode output NIPPON PRECISION CIRCUITS INC.—9 SM5819HQF Initialization and resynchronization ■ INIT, SYNC pins Rating Parameter Symbol Unit min typ max Initialization time tINTM 6 × tMCY – – ns Resynchronization pulsewidth tSYCW 6 × tMCY – – ns VDDH 3.0V tINTM tINTM INIT tSYCW SYNC NIPPON PRECISION CIRCUITS INC.—10 SM5819HQF FUNCTIONAL DESCRIPTION Data Input/Output Formats DSD input format DSD input data is read in on the rising edge of the DSBCK bit clock. (1/64fs) DSBCK DSI** DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins PCM output format The PCM output format can be assigned to either of two types below using FMTPCM. The output data is in 32bit 2s complement form. The PLRCK and PBCK frequencies are set in response to the fs/2fs/4fs switch mode. However, when external inputs are selected, the inputs are passed to the output in through mode, regardless of the assigned format. (1) MSB-first left-justified 32-bit (FMTPCM = “L”) (1/fs, 1/2fs, or 1/4fs) PLRCK PBCK PO** 31 30 29 28 2 1 0 31 30 29 28 2 1 0 31 30 LSB MSB Lch (POSLR, POFLR) Center (POCSW) Rch (POSLR, POFLR) SubWoofer (POCSW) PO**: POFLR, POSLR, POCSW pins ■ ■ If more than 32 bit clock cycles are input during a word clock cycle HIGH-level or LOW-level pulse, all bits after the 32nd bit are output as “0”. When PLRCK and PBCK are set to output mode, the number of bit clock cycles during a word clock HIGHlevel or LOW-level pulse is fixed at 32. (2) IIS 32-bit (FMTPCM = “H”) (1/fs, 1/2fs, or 1/4fs) PLRCK PBCK PO** 1 0 31 30 29 4 3 2 1 MSB 0 31 30 29 4 3 2 1 0 31 LSB Lch (POSLR, POFLR) Center (POCSW) Rch (POSLR, POFLR) SubWoofer (POCSW) PO**: POFLR, POSLR, POCSW pins ■ In this format, there are 32 bit clock cycles per word clock cycle regardless of the input/output settings. NIPPON PRECISION CIRCUITS INC.—11 SM5819HQF Data Output Selection PCM output selection The PCM output and decimation filter processing is set by SEL4FS, SEL1FS and SELEXT, as shown in the following table. Setting ■ ■ ■ Clock output PCM output system Filter processing SEL1FS SEL4FS SELEXT POFLR POSLR POCSW PLRCK PBCK L H L DSIFL DSIFR DSISL DSISR DSICT DSISW 4fs MCK 4fs 960th-order L L L DSIFL DSIFR DSISL DSISR DSICT DSISW 2fs MCK 2fs 960th-order H L or H L DSIFL DSIFR DSISL DSISR DSICT DSISW fs MCK fs 960th-order L or H L or H H EXIFLR EXISLR EXICSW EXILRCK EXIBCK EXIMCK Invalid MCKOUT The external data setting (SELEXT) has priority over the 4fs/2fs/fs selection setting (SEL1FS, SEL4FS). Also, the fs setting (SEL1FS) has priority over the 4fs/2fs setting (SEL4FS). In the case of 4fs mode, the PCM data is a setting which passes through passband. When the DSGAIN is set to HIGH, it may clip depending on signal. Therefore, please use at DSGAIN = LOW. Clock Input/Output Selection and Resynchronization Operation DSD clock input/output switching The DSD input bit clock (DSBCK) can be switched between input and output by DIRDSCK. Setting I/O state DIRDSCK DSBCK L Input (Slave) H Output (Master) PCM clock input/output switching The PCM output word clock (PLRCK) and bit clock (PBCK) can be switched between input and output by DIRPCK. Setting I/O state DIRPCK PLRCK PBCK L Output (Master) H Input (Slave) However, when external data is selected using SELEXT, the clocks PLRCK and PBCK are switched to outputs, regardless of the DIRPCK setting, thus care must be exercised with external connections. NIPPON PRECISION CIRCUITS INC.—12 SM5819HQF Input clock sync operation and resynchronization The internal computation and interface processing for data output is event driven, with the word boundary edge of the word clock as the trigger. This ensures the output signals are synchronized, regardless of the word clock and bit clock input/output settings. The DSD input comprises data read into a buffer on the rising edge of the DSBCK bit clock (BUF_A) and data in another buffer internally delayed by half a bit clock cycle (BUF_B), and then a buffer is selected when the PCM output event occurs in order to avoid DSD input signal transitions. Synchronization of whichever data buffer is selected occurs when the word boundary edge of the word clock is detected after the first DSBCK falling edge following a rising edge on INIT or SYNC. ;;;; ;;;; ;;;; ;;;; DSI** ;;;; ;;;; ;;;; SNYC/INIT D (n) ;;;;;;;; ;;;;;;;; ;;;;;;;; D (n+1) ;;;;;;;; D (n+2) ;;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;;; ;;;;;;;; D (n+3) ;;;;;;;; ;;;;;;;; D (n+3) ;;; ;;; ;;; ;;; DSBCK ;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;; ;;;;;;;;;;;;;;; DA (n+1) DA (n+2) DA (n) ;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;; (BUF_B) ;;;;;;;;;;;;;; DB (n-1) DB (n) DB (n+1) ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; (IN_PHASE) ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (PCM_SEL) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Select "BUF_A") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (BUF_A) PLRCK (Filter Input) DA (n+3) DB (n+2) DB (n+2) (Word boundary edge) ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;; DA (n-1) DA (n) DA (n+1) ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;; DB (n+1) DB (n+2) DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins Figure 1. Input timing synchronization operation using INIT and SYNC 1) On the first DSBCK falling edge after a rising edge of SYNC or INIT, (IN_PHASE) is a phase reference signal for input data buffer selection. 2) Then, the input data buffer selected is determined by the logic level of IN_PHASE when the first PLRCK word boundary edge is detected. When synchronization is adjusted using INIT or SYNC (resynchronization), 1 DSD data unit may be lost or repeated depending on the phase difference between input/output clocks. The individual outputs should be muted by a minimum interval, given below, to avoid these data glitches. [4fs PCM output] 36 clock cycles in PLRCK (4fs) mode [2fs PCM output] 18 clock cycles in PLRCK (2fs) mode [fs PCM output] 10 clock cycles in PLRCK (fs) mode NIPPON PRECISION CIRCUITS INC.—13 SM5819HQF External input data and external system clock output switching (1) Switching to external input data When SELEXT is switched LOW to HIGH, the PCM data output is immediately switched to external input data. PLRCK and PBCK are similarly switched immediately to EXILRCK and EXIBCK in through mode, respectively, regardless of the DIRPCK setting. (2) Switching to external system clock The MCKOUT system clock output can be switched between MCK and EXIMCK using SELEXT, as given below. SELEXT = “L”: MCK output SELEXT = “H”: EXIMCK output Note that neither MCK nor EXIMCK clock should be stopped during the switching interval to prevent a micro-pulse being generated when switching. The switching interval lasts from when SELEXT changes state until both clocks have made 4 transitions. During this interval, the LOW-level clock pulsewidth of the first clock is extended until the rising edge of the second clock occurs. When the switching interval ends, the unused clock may then be stopped. MCK O FF ON EXIMCK SELEXT (MCK OFF) (EXIMCK ON) MCKOUT (Switching time) Figure 2. MCK → EXIMCK switching ON MCK EXIMCK F OF SELEXT (EXIMCK OFF) (MCK ON) MCKOUT (Switching time) Figure 3. EXIMCK → MCK switching NIPPON PRECISION CIRCUITS INC.—14 SM5819HQF DSD Gain Switching The PCM output can be adjusted such that 0dB corresponds to 50% modulation level DSD input signal using DSGAIN, as given below. DSGAIN = “L” : 100% modulation = 0dB (PCM) DSGAIN = “H” : 50% modulation = 0dB (PCM) * with +6dB internal amplification 0dB when DSGAIN="L" [7FFFFFFFh] +1.0 0dB when DSGAIN="H" +0.5 [7FFFFFFFh] 0 [00000000h] -0.5 [80000000h] -1.0 [00000000h] [80000000h] Figure 4. DSD modulation level Note. When DSGAIN = “H”, note that any input DSD signal with modulation of 50% level or higher will be amplitude limited, resulting in output signal clipping. Note. In the case of 4fs mode, the PCM data is a setting which passes through passband. When the DSGAIN is set to HIGH, it may clip depending on signal. Therefore, please use at DSGAIN = LOW. Mute Function The PCM outputs can be muted using XMTPCM, as given below. Muting is applied immediately before output. When PCM muting is set ON, the PCM outputs are directly set to value “0”. XMTPCM = “L” : all PCM outputs muting ON XMTPCM = “H” : all PCM outputs muting OFF The mute function is only active for internal computation of fs/2fs/4fs output. It is inactive for external input to output connection in through mode. Initialization Operation The power must be applied in order of VDDL and VDDH. Please avoid the continuous power supply injection of only VDDH. (less than 1 second) After power is applied, INIT must be held LOW for the rated interval to initialize the device. During initialization, the outputs have the following states. Pin PCM data outputs state LOW in internal data output mode External input to output connection in through mode DSBCK HIGH in output (master) mode PBCK HIGH in internal data output mode External bit clock input to output connection in through mode PLRCK LOW in 32-bit left-justified output mode HIGH in IIS output mode External word clock input to output connection in through mode MCKOUT MCK or EXIMCK, whichever is currently selected. When INIT goes HIGH, synchronization operation begins as described in the section “Input clock sync operation and resynchronization”. Note that if the PCM signal muting is ON during initialization, muting operation continues until it is released. The system clock input on MCK must be applied during initialization. NIPPON PRECISION CIRCUITS INC.—15 SM5819HQF BUILT-IN FILTER CHARACTERISTICS Filter Mode Cutoff Characteristics [dB] 0 10 20 30 40 50 60 70 80 90 100 [kHz] 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 0 fs 2fs 4fs 10 20 30 40 50 60 70 [kHz] 1 0 [dB] -1 -2 fs 2fs 4fs -3 -4 -5 NIPPON PRECISION CIRCUITS INC.—16 SM5819HQF Filter Mode Ripple Characteristics 0 5 10 15 20 25 30 35 40 45 50 [kHz] -0.008680 -0.008682 -0.008684 -0.008686 [dB] -0.008688 fs 2fs -0.008690 -0.008692 -0.008694 -0.008696 -0.008698 -0.008700 0 5 10 15 20 25 30 35 40 45 50 [kHz] 0.000010 0.000008 0.000006 0.000004 [dB] 0.000002 0.000000 4fs -0.000002 -0.000004 -0.000006 -0.000008 -0.000010 Note. In the case of 4fs mode, the PCM data is a setting which passes through passband. When the DSGAIN is set to HIGH, it may clip depending on signal. Therefore, please use at DSGAIN = LOW. NIPPON PRECISION CIRCUITS INC.—17 SM5819HQF Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from NIPPON PRECISION CIRCUITS INC. (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome, Koto-ku, Tokyo 135-8430, Japan Telephone: +81-3-3642-6661 Facsimile: +81-3-3642-6698 http://www.npc.co.jp/ Email: [email protected] NC0407AE 2004.10 NIPPON PRECISION CIRCUITS INC.—18