MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 D D D D Interface to External ROM/EPROM (Up to 8 MBytes) 8-Bit Microprocessor with 61 instructions 32 Twelve-Bit Words and 992 Bytes of RAM 4K Internal ROM D D D 3.3V to 6.5V CMOS Technology for Low Power Dissipation 28 Software-Configurable I/O Lines 10-kHz or 8-kHz Speech Sample Rate description The MSP50C30 combines an 8-bit microprocessor, two speech synthesizers, ROM, RAM, and I/O in a low-cost single-chip system. The architecture uses the same arithmetic logic unit (ALU) for the two synthesizers and the microprocessor, thus reducing chip area and cost and enabling the microprocessor to do a multiply operation in 0.8 µs. The MSP50C30 features two independent channels of linear predictive coding (LPC), which synthesize high-quality speech at a low data rate. Pulse-code modulation (PCM) can produce music or sound effects. For more information, see the MSP50C30 User’s Guide (literature number SPSU012). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC NC NC NC NC NC OA0 PD3 PD2 PD1 PD0 VDD DAC– DAC+ VSS PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 OSC OUT NC NC NC NC NC NC NC PA1 PA2 PA3 PA4 PA5 PA6 NC NC PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 OSC IN NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC NC NC NC OA17 OA18 OA19 OA20 OA21 OA22 VSS ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 INIT VDD PA0 NC NC NC NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC OA16 OA15 OA14 OA13 OA12 OA11 OA10 OA9 OA8 OA7 OA6 OA5 OA4 OA3 OA2 OA1 NC NC PJM PACKAGE (TOP VIEW) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 8 V Supply current, IDD or ISS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground. 2. The total supply current includes the current out of all the I/O terminals and DAC terminals as well as the operating current of the device. recommended operating conditions (MSP50C32, MSP50C33, MSP50x34) VDD VIH VIL Supply voltage† High-level input voltage Low-level input voltage MAX 3.3 6.5 VDD = 3.3 V VDD = 5 V 2.5 3.3 3.8 5 VDD = 6 V VDD = 3.3 V 4.5 6 0 0.65 VDD = 5 V VDD = 6 V 0 1 0 1.3 0 70 TA Operating free-air temperature Device functionality Rspeaker Minimum speaker impedance Direct speaker drive using 2 pin push-pull DAC option † Unless otherwise noted, all voltages are with respect to VSS. 2 MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 32 UNIT V V V °C Ω MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VT T+ Positive going threshold voltage (INIT) Positive-going VDD = 3.5 V VDD = 6 V VT T– Negative going threshold voltage (INIT) Negative-going VDD = 3.5 V VDD = 6 V 1.6 Vh hys Hysteresis ( VT T+ – VT T– ) (INIT) VDD = 3.5 V VDD = 6 V 0.4 IIkg Input leakage current (except for OSC IN) Istandby Standby current (INIT low, SETOFF) IDD† Supply current IOH High level output current (PA, High-level (PA PB) VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, IOL Low level output current (PA, Low-level (PA PB) VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, IOH High level output current (D/A) High-level VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, IOL Low level output current (D/A) Low-level Pullup resistance 2 VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, UNIT V 3.4 V 2.3 V 1.1 VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, MAX 2 µA 10 µA 2.1 mA 3.1 4.5 VOH = 2.75 V VOH = 4.5 V –4 –12 –5 –14 VOH = 5.5 V VOH = 2.2 V –6 – 15 –8 –20 VOH = 3.33 V VOH = 4 V –14 – 40 – 20 – 51 VOL = 0.5 V VOL = 0.5 V 5 9 5 9 VOL = 0.5 V VOL = 1.1 V 5 9 10 19 VOL = 1.67 V VOL = 2 V 20 29 25 35 VOH = 2.75 V VOH = 4.5 V – 30 –50 –35 –60 VOH = 5.5 V VOH = 2.3 V –40 – 65 – 50 –90 –90 – 140 – 100 – 150 VOL = 0.5 V VOL = 0.5 V 50 80 70 90 VOL = 0.5 V VOL = 1 V 80 110 100 140 VOH = 4 V VOH = 5 V VOL = 1 V VOL = 1 V VDD = 6 V, Resistors selected by software and connected between terminal and VDD mA mA mA mA mA mA mA mA 140 150 10 20 50 kΩ fosc(low) (l ) Oscillator frequency freq enc ‡ VDD = 5 V, TA = 25°C, Target frequency = 15.36 MHz 14 89 14.89 15 36 15.36 15 86 15.86 MHz fosc(high) (hi h) Oscillator frequency freq enc ‡ VDD = 5 V, TA = 25°C, Target frequency = 19.2 MHz 18 62 18.62 19 2 19.2 19 7 19.7 MHz † Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited. ‡ The frequency of the internal clock has a temperature coefficient of approximately – 0.2 % / °C and a VDD coefficient of approximately ±1%/V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 switching characteristics PARAMETER tr tf Rise time Fall time TEST CONDITIONS MIN NOM PA, PB, PC, PD, D/A VDD = 3.3 V, CL = 100 pF, 10% to 90% 50 OA VDD = 3.3 V, CL = 50 pF, 10% to 90% 50 PA, PB, PC, PD, D/A VDD = 3.3 V, CL = 100 pF, 10% to 90% 50 OA VDD = 3.3 V, CL = 50 pF, 10% to 90% 50 MAX UNIT ns ns timing requirements MIN MAX UNIT Initialization tINIT INIT pulsed low while the MSP50x3x has power applied (see Figure 1) 1 µs Setup time prior to wakeup terminal negative transition (see Figure 2) 1 µs Wakeup tsu(wakeup) External Interrupt tsu(interrupt) (i t t) Setup time prior to B1 terminal negative transition (see Figure 3) fclock = 15.36 MHz fclock = 19.2 MHz 1 µs 1.5 Writing (Slave Mode) tsu1(B1) tsu(d) Setup time, B1 low before B0 goes low (see Figure 4) th1(B1) th(d) Hold time, B1 low after B0 goes high (see Figure 4) Hold time, data valid after B0 goes high (see Figure 4) tw tr Pulse duration, B0 low (see Figure 4) Rise time, B0 (see Figure 4) 50 ns tf Fall time, B0 (see Figure 4) 50 ns Setup time, data valid before B0 goes high (see Figure 4) 20 ns 100 ns 20 ns 30 ns 100 ns Reading (Slave Mode) tsu2(B1) th2(B1) Setup time, B1 before B0 goes low (see Figure 5) 20 Hold time, B1 after B0 goes high (see Figure 5) 20 tdis tw Output disable time, data valid after B0 goes high (see Figure 5) tr tf Rise time, B0 (see Figure 5) 50 ns Fall time, B0 (see Figure 5) 50 ns td Delay time for B0 low to data valid (see Figure 5) 50 ns 400 ns Pulse duration, B0 low (see Figure 5) 0 ns ns 30 100 ns ns External ROM ta(ROM) 4 ROM access time POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION INIT tINIT Figure 1. Initialization Timing Diagram Wakeup tsu(wakeup) Figure 2. Wakeup Terminal Setup Timing Diagram B1 tsu(interrupt) Figure 3. External Interrupt Terminal Setup Timing Diagram B1 th1(B1) tsu1(B1) tw B0 tf tr tsu(d) th(d) PA Data Valid Figure 4. Write Timing Diagram (Slave Mode) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION B1 tsu2(B1) th2(B1) tw B0 tf tr tdis td PA Data Valid Figure 5. Read Timing Diagram (Slave Mode) 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 MECHANICAL DATA PJM (R-PQFP-G100) PLASTIC QUAD FLATPACK 0,38 0,22 0,65 80 0,13 M 51 50 81 12,35 TYP 100 14,20 13,80 17,45 16,95 31 1 30 0,16 NOM 18,85 TYP 20,20 19,80 23,45 22,95 2,90 2,50 Gage Plane 0,25 0,25 MIN 0°– 7° 1,03 0,73 Seating Plane 0,10 3,40 MAX 4040022 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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