54ACT11827, 74ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS SCAS078 – NOVEMBER 1989 – REVISED APRIL 1993 • • • • • • • 54ACT11827 . . . JT PACKAGE 74ACT11827 . . . DW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Ceramic 300-mil DIPs Y1 Y2 Y3 Y4 Y5 GND GND GND GND Y6 Y7 Y8 Y9 Y10 t description These 10-bit buffers/bus drivers provide highperformance bus interface for wide data paths or buses carrying parity. The ′ACT11827 provides inverted data. The 54ACT11827 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74ACT11827 is characterized for operation from – 40°C to 85°C. G2 A OUTPUT Y L L H H L L L L X H X Z H X X Z 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 G1 A1 A2 A3 A4 A5 VCC VCC A6 A7 A8 A9 A10 G2 A2 A1 G1 Y1 Y2 Y3 Y4 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 A8 A9 A10 G2 Y10 Y9 Y8 Y5 GND GND GND GND Y6 Y7 G1 27 54ACT11827 . . . FK PACKAGE (TOP VIEW) FUNCTION TABLE INPUTS 28 2 A3 A4 A5 V CC V CC A6 A7 The 3-state control gate is a 2-input NOR such that if either G1 or G2 is high, all ten outputs are in the high-impedance state. 1 EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 54ACT11827, 74ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS SCAS078 – NOVEMBER 1989 – REVISED APRIL 1993 logic symbol† G1 G2 28 logic diagram (positive logic) & G1 15 G2 EN A1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 27 1 26 2 25 3 24 4 23 5 20 10 19 11 18 12 17 13 16 14 Y1 Y2 A2 Y3 Y4 A3 Y5 Y6 A4 Y7 Y8 A5 Y9 Y10 A6 A7 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. A8 A9 A10 28 15 27 1 26 2 Y2 25 3 Y3 24 4 23 5 Y1 Y4 Y5 20 10 Y6 19 11 Y7 18 12 Y8 17 13 16 14 Y9 Y10 Pin numbers shown are for the DW, JT, and NT packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 250 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C } Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54ACT11827, 74ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS SCAS078 – NOVEMBER 1989 – REVISED APRIL 1993 recommended operating conditions 54ACT11827 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current IOL Dt /Dv Low-level output current TA Operating free-air temperature High-level input voltage 74ACT11827 MIN 2 2 0.8 Input transition rise or fall rate UNIT V V 0.8 V VCC VCC V – 24 – 24 mA 24 24 mA VCC VCC 0 0 V 0 10 0 10 ns/ V – 55 125 – 40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = – 50 mA VOH VOL IOH = – 24 mA VCC MIN TA = 25°C TYP MAX 54ACT11827 MIN MAX 74ACT11827 MIN 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 4.5 V 3.94 3.7 3.8 5.5 V 4.94 4.7 4.8 MAX V IOH = – 50 mA† IOH = – 75 mA† 5.5 V IOL = 50 mA 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 IOL = 24 mA UNIT 3.85 5.5 V 3.85 V IOL = 50 mA† IOL = 75 mA† 5.5 V IOZ II VO = VCC or GND VI = VCC or GND 5.5 V ± 0.5 ± 10 ±5 5.5 V ± 0.1 ±1 ±1 ICC VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at GND or VCC 5.5 V 8 160 80 mA mA mA 5.5 V 0.9 1 1 mA DICC‡ Ci VI = VCC or GND VO = VCC or GND 1.65 5.5 V 5V 1.65 4 Co 5V 10 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC. pF pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 54ACT11827, 74ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS SCAS078 – NOVEMBER 1989 – REVISED APRIL 1993 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL G Y tPHZ tPLZ G Y MIN TA = 25°C TYP MAX 54ACT11827 74ACT11827 MIN MAX MIN MAX 3.8 6.3 8 3.8 9.9 3.8 9.2 2.7 6.9 9.5 2.7 11.9 2.7 11.2 2.6 6.4 9.2 2.6 12.2 2.6 11.3 3.2 8 11.2 3.2 15.1 3.2 14 6.1 8.8 11.1 6.1 12.9 6.1 12 5.8 8.3 10.6 5.8 12.4 5.8 11.6 UNIT ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d TEST CONDITIONS Outputs enabled Power dissipation capacitance CL = 50 pF, pF Outputs disabled TYP 35 f = 1 MHz 10 UNIT pF PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND LOAD CIRCUIT Output Control (low-level enabling) 3V 1.5 V 1.5 V 0V tPLH tPHL VOH Output S1 Open 2 × VCC GND 500 Ω CL = 50 pF (see Note A) Input (see Note B) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 50% VCC 50% VCC VOL 3V 0V tPZL [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note C) Output Waveform 2 S1 at GND (see Note C) 1.5 V 1.5 V 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. 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