Obsolete Device 24FC65 64K 5.0V 1 MHz I2C™ Smart Serial™ EEPROM FEATURES The Microchip Technology Inc. 24FC65 is a “smart” 8K 8x 8 Serial Electrically Erasable PROM (EEPROM) with a high-speed 1MHz SE2.bus whose protocol is functionally equivalent to the industry-standard I2C bus. This device has been developed for advanced applications such as personal communications, and provides the systems designer with flexibility through the use of many new user-programmable features. The 24FC65 offers a relocatable 4K-bit block of ultra-high-endurance memory for data that changes frequently. The remainder of the array, or 60K bits, is rated at 1,000,000 ERASE/WRITE (E/W) cycles guaranteed. The 24FC65 features an input cache for fast write loads with a capacity of eight pages, or 64 bytes. This device also features programmable security options for E/W protection of critical data and/or code of up to fifteen 4K blocks. Functional A0 1 8 VCC A1 2 7 NC A2 3 6 SCL VSS 4 5 SDA A0 1 8 VCC A1 2 7 NC A2 3 6 SCL VSS 4 5 SDA SOIC 24FC65 DESCRIPTION PDIP 24FC65 • Voltage operating range: 4.5V to 5.5V - Maximum write current 3 mA at 5.5V - Maximum read current 150 µA at 5.5V - Standby current 1 µA typical • 1 MHz SE2.bus two wire protocol • Up to eight devices may be connected to the same bus for up to 512K bits total memory • Programmable block security options • Programmable endurance options • Schmitt trigger inputs for noise suppression • Self-timed ERASE and WRITE cycles • Power on/off data protection circuitry • Endurance: - 10,000,000 E/W cycles guaranteed for a 4K block - 1,000,000 E/W cycles guaranteed for a 60K block • Variable page size up to 64 bytes • 8 byte x 8 line input cache (64 bytes) for fast write loads • <3 ms typical write cycle time, byte or page • Electrostatic discharge protection > 4000V • Data retention > 200 years • 8-pin PDIP/SOIC packages • Temperature ranges - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C PACKAGE TYPES BLOCK DIAGRAM A0 A1 A2 I/O CONTROL LOGIC MEMORY CONTROL LOGIC HV GENERATOR XDEC EEPROM ARRAY PAGE LATCHES I/O SDA SCL CACHE YDEC VCC VSS SENSE AMP R/W CONTROL address lines allow the connection of up to eight 24FC65's on the same bus for up to 512K bits contiguous EEPROM memory. The 24FC65 is available in the standard 8-pin plastic DIP and 8-pin surface mount SOIC package. I2C is a trademark of Philips Corporation. Smart Serial is a trademark of Microchip Technology Inc. 2004 Microchip Technology Inc. DS21125E-page 1 24FC65 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* TABLE 1-1: Name Function A0,A1,A2 VSS SDA SCL VCC NC VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................-65°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD protection on all pins ..................................................≥ 4 kV *Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: PIN FUNCTION TABLE User Configurable Chip Selects Ground Serial Address/Data I/O Serial Clock +4.5V to 5.5V Power Supply No Internal Connection DC CHARACTERISTICS VCC = +4.5V to +5.5V Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Parameter A0, A1, A2, SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of SCL and SDA Low level output voltage of SDA Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Symbol Min Max Units VIH VIL VHYS VOL ILI ILO CINT 0.7 VCC — 0.05 VCC — -10 -10 — — 0.3 Vcc — 0.40 10 10 10 V V V V µA µA pF ICC Write ICC Read ICCS — — — 3 150 5 mA µA µA Conditions (Note) IOL = 3.0 mA VIN = 0.1V to VCC VOUT = 0.1V to VCC VCC = 5.0V (Note) Tamb = 25°C, FCLK = 1 MHz VCC = 5.5V, SCL = 1 MHZ VCC = 5.5V, SCL = 1 MHz VCC = 5.5V, SCL = SDA =VCC A0, A1, A2 = VSS Note: This parameter is periodically sampled and not 100% tested. FIGURE 1-1: BUS TIMING START/STOP SCL VHYS THD:STA TSU:STO TSU:STA SDA START DS21125E-page 2 STOP 2004 Microchip Technology Inc. 24FC65 TABLE 1-3: AC CHARACTERISTICS 1 MHz Bus Parameter Symbol Units Min Max 1000 — — 300 100 — kHz ns ns ns ns ns — — — — 350 — ns ns ns ns ns ns Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START hold time TLOW TR TF THD:STA 0 500 500 — — 250 START setup time Data input hold time Data input setup time STOP setup time Output valid from clock Bus free time TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF 250 0 100 250 — 500 FCLK THIGH Remarks (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START (Note 2) Time the bus must be free before a new transmission can start ms/page (Note 3) — 5 Write cycle time TWR Endurance High Endurance Block 10M — cycles 25°C, Vcc = 5.0V, Block Mode Rest of Array 1M — (Note 4) Note 1: Not 100 percent tested. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 100 ns) of the falling edge of SCL to avoid unintended generation of START or STOPs. 3: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write cache for total time. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website. FIGURE 1-2: BUS TIMING DATA TF TR THIGH TLOW SCL TSU:STA THD:DAT TSU:DAT THD:STA SDA IN TSP TSU:STO TBUF TAA TAA SDA OUT 2004 Microchip Technology Inc. DS21125E-page 3 24FC65 2.0 FUNCTIONAL DESCRIPTION The 24FC65 supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOPs, while the 24FC65 works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. 3.0 BUS CHARACTERISTICS 3.4 Data Valid (D) The state of the data line represents valid data when, after a START, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START and terminated with a STOP. The number of the data bytes transferred between the START and STOPs is determined by the master device. The following bus protocol has been defined: 3.5 • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP. Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Accordingly, the following bus conditions have been defined (Figure 3-1). 3.1 Bus not Busy (A) Both data and clock lines remain HIGH. 3.2 Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START. All commands must be preceded by a START. 3.3 Note: Acknowledge The 24FC65 does not generate any acknowledge bits if an internal programming cycle is in progress. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24FC65) must leave the data line HIGH to enable the master to generate the STOP. Stop Data Transfer (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP. All operations must be ended with a STOP. FIGURE 3-1: (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) (D) (C) (A) SCL SDA START Condition DS21125E-page 4 Address Data Allowed or to Change Acknowledge Valid STOP Condition 2004 Microchip Technology Inc. 24FC65 3.6 Device Addressing A control byte is the first byte received following the START from the master device. The control byte consists of a four bit control code, for the 24FC65 this is set as 1010 binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used by the master device to select which of the eight devices are to be accessed. These bits are in effect the three most significant bits of the word address. The last bit of the control byte (R/W) defines the operation to be performed. When set to a one a read operation is selected, when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 4-1). Because only A12..A0 are used, the upper three address bits must be zeros. The most significant bit of the most significant byte is transferred first. Following the START, the 24FC65 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a 1010 code and appropriate device select bits, the slave device (24FC65) outputs an acknowledge signal on the SDA line. Depending upon the state of the R/W bit, the 24FC65 will select a read or write operation. Operation Control Code Device Select R/W Read 1010 Device Address 1 Write 1010 Device Address 0 FIGURE 3-2: CONTROL BYTE ALLOCATION START READ/WRITE SLAVE ADDRESS 1 0 1 0 A2 R/W A1 A A0 X = Don’t care FIGURE 4-1: 4.0 WRITE OPERATION 4.1 Byte Write Following the START from the master, the control code (four bits), the device select (three bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver (24FC65) that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24FC65. The next byte is the least significant address byte. After receiving another acknowledge signal from the 24FC65 the master device will transmit the data word to be written into the addressed memory location. The 24FC65 acknowledges again and the master generates a STOP. This initiates the internal write cycle, and during this time the 24FC65 will not generate acknowledge signals (Figure 4-1). 4.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24FC65 in the same way as in a byte write. But instead of generating a STOP the master transmits up to eight pages of eight data bytes each (64 bytes total) which are temporarily stored in the on-chip page cache of the 24FC65. They will be written from the cache into the EEPROM array after the master has transmitted a STOP. After the receipt of each word, the six lower order address pointer bits are internally incremented by one. The higher order seven bits of the word address remain constant. If the master should transmit more than eight bytes prior to generating the STOP (writing across a page boundary), the address counter (lower three bits) will roll over and the pointer will be incremented to point to the next line in the cache. This can continue to occur up to eight times or until the cache is full, at which time a STOP should be generated by the master. If a STOP is not received, the cache pointer will roll over to the first line (byte 0) of the cache, and any further data received will overwrite previously captured data. The STOP can be sent at any time during the transfer. As with the byte write operation, once the STOP is received an internal write cycle will begin. The 64 byte cache will continue to capture data until a STOP occurs or the operation is aborted (Figure 4-2). BYTE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S BUS ACTIVITY 2004 Microchip Technology Inc. CONTROL BYTE WORD ADDRESS (1) WORD ADDRESS (0) S T O P DATA 0 0 0 A C K P A C K A C K A C K DS21125E-page 5 24FC65 FIGURE 4-2: PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 7-1) S T BUS A ACTIVITY: R MASTER T SDA LINE WORD ADDRESS (1) CONTROL BYTE S WORD ADDRESS (0) P 0 0 0 A C K BUS ACTIVITY: FIGURE 4-3: A C K A C K A C K A C K CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S CONTROL BYTE FIGURE 4-4: S T O P DATA n P N O A C K BUS ACTIVITY S T BUS A ACTIVITY: R MASTER T S T O P DATA n+7 DATA n A C K RANDOM READ WORD ADDRESS (1) CONTROL BYTE SDA LINE S WORD ADDRESS (0) CONTROL BYTE S T O P DATA n S 0 0 0 A C K A C K BUS ACTIVITY: FIGURE 4-5: S T A R T P A C K N O A C K A C K SEQUENTIAL READ BUS ACTIVITY MASTER DATA n DATA n+2 DATA n+1 S T O P DATA n+X CONTROL BYTE P SDA LINE BUS ACTIVITY A C K A C K A C K A C K N O A C K DS21125E-page 6 2004 Microchip Technology Inc. 24FC65 5.0 READ OPERATION Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 5.1 Current Address Read The 24FC65 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24FC65 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a STOP and the 24FC65 discontinues transmission (Figure 4-3). 5.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24FC65 as part of a write operation (R/W bit set to 0). After the word address is sent, the master generates a START following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24FC65 will then issue an acknowledge and transmit the eight bit data word. The master will not acknowledge the transfer but does generate a STOP which causes the 24FC65 to discontinue transmission (Figure 4-4). 5.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24FC65 transmits the first data byte, the master issues an acknowledge as opposed to the STOP used in a random read. This acknowledge directs the 24FC65 to transmit the next sequentially addressed 8 bit word (Figure 4-5). Following the final byte transmitted to the master, the master will NOT generate an acknowledge but will generate a STOP. To provide sequential reads the 24FC65 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. 2004 Microchip Technology Inc. 5.4 Contiguous Addressing Across Multiple Devices The device select bits A2, A1, A0 can be used to expand the contiguous address space for up to 512K-bits by adding up to eight 24FC65's on the same bus. In this case, software can use A0 of the control byte as address bit A13, A1 as address bit A14, and A2 as address bit A15. 5.5 Noise Protection The SCL and SDA inputs incorporate Schmitt triggers which suppress noise spikes to assure proper device operation even on a noisy bus. 5.6 High Endurance Block The location of the high-endurance block within the memory map is programmed by setting the leading bit 7 (S/HE) of the configuration byte to 0. The upper bits of the address loaded in this command will determine which 4K block within the memory map will be set to high endurance (Figure 8-1). This block will be capable of 10,000,000 erase/write cycles guaranteed. Note: 5.7 The High Endurance Block cannot be changed after the security option has been set. If the H.E. block is not programmed by the user, the default location is the highest block of memory. Security Options The 24FC65 has a sophisticated mechanism for write-protecting portions of the array. This write protect function is programmable and allows the user to protect 0-15 contiguous 4K blocks. The user sets the security option by sending to the device the starting block number for the protected region and the number of blocks to be protected. All parts will come from the factory in the default configuration with the starting block number set to 15 and the number of protected blocks set to zero. THE SECURITY OPTION CAN BE SET ONLY ONCE. To invoke the security option, a write command is sent to the device with the leading bit (bit7) of the first address byte set to a 1 (Figure 8-1). Bits 1-4 of the first address byte define the starting block number for the protected region. For example, if the starting block number is to be set to 5, the first address byte would be 1XX0101X. Bits 0, 5 and 6 of the first address byte are disregarded by the device and can be either high or low. The device will acknowledge after the first address byte. A byte of don't care bits is then sent by the master, with the device acknowledging afterwards. The third byte sent to the device has bit7 (S/HE) set high and bit6 (R) set low. Bits 4 and 5 are don't cares and bits 0-3 define the number of blocks to be write protected. For example, if three blocks are to be protected, the third DS21125E-page 7 24FC65 byte would be 10XX0011. After the third byte is sent to the device, it will acknowledge and a STOP bit is then sent by the master to complete the command. During a normal write sequence, if an attempt is made to write to a protected address, no data will be written and the device will not report an error or abort the command. If a write command is attempted across a secure boundary, unprotected addresses will be written and protected addresses will not. 5.8 Security Configuration Read The status of the secure portion of memory can be read by using the same technique as programming this option except the READ bit (bit 6) of the configuration byte is set to a one. After the configuration byte is sent, the device will acknowledge and then send two bytes of data to the master just as in a normal read sequence. The master must acknowledge the first byte and not acknowledge the second, and then send a stop bit to end the sequence. The upper four bits of both of these bytes will always be read as '1's. The lower four bits of the first byte contains the starting secure block. The lower four bits of the second byte contains the number of secure blocks. The default starting secure block is fifteen and the default number of secure blocks is zero (Figure 8-1). 6.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the STOP for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a START followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 6-1 for flow diagram. FIGURE 6-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation DS21125E-page 8 2004 Microchip Technology Inc. 24FC65 7.0 PAGE CACHE AND ARRAY MAPPING The cache is a 64 byte (8 pages x 8 bytes) FIFO buffer. The cache allows the loading of up to 64 bytes of data before the write cycle is actually begun, effectively providing a 64-byte burst write at the maximum bus rate. Whenever a write command is initiated, the cache starts loading and will continue to load until a stop bit is received to start the internal write cycle. The total length of the write cycle will depend on how many pages are loaded into the cache before the stop bit is given. Maximum cycle time for each page is 5 ms. Even if a page is only partially loaded, it will still require the same cycle time as a full page. If more than 64 bytes of data are loaded before the stop bit is given, the address pointer will wrap around' to the beginning of cache page 0 and existing bytes in the cache will be overwritten. The device will not respond to any commands while the write cycle is in progress. 7.1 Cache Write Starting at a Page Boundary If a write command begins at a page boundary (address bits A2, A1 and A0 are zero), then all data loaded into the cache will be written to the array in sequential addresses. This includes writing across a 4K block boundary. In the example shown below, (Figure 7-1) a write command is initiated starting at byte 0 of page 3 with a fully loaded cache (64 bytes). The first byte in the cache is written to byte 0 of page 3 (of the array), with the remaining pages in the cache written to sequential pages in the array. A write cycle is executed after each page is written. Since the write begins at page 3 and 8 pages are loaded into the cache, the last 3 pages of the cache are written to the next row in the array. 2004 Microchip Technology Inc. 7.2 Cache Write Starting at a Non-Page Boundary When a write command is initiated that does not begin at a page boundary (i.e., address bits A2, A1 and A0 are not all zero), it is important to note how the data is loaded into the cache, and how the data in the cache is written to the array. When a write command begins, the first byte loaded into the cache is always loaded into page 0. The byte within page 0 of the cache where the load begins is determined by the three least significant address bits (A2, A1, A0) that were sent as part of the write command. If the write command does not start at byte 0 of a page and the cache is fully loaded, then the last byte(s) loaded into the cache will roll around to page 0 of the cache and fill the remaining empty bytes. If more than 64 bytes of data are loaded into the cache, data already loaded will be overwritten. In the example shown in Figure 7-2, a write command has been initiated starting at byte 2 of page 3 in the array with a fully loaded cache of 64 bytes. Since the cache started loading at byte 2, the last two bytes loaded into the cache will ’roll over' and be loaded into the first two bytes of page 0 (of the cache). When the stop bit is sent, page 0 of the cache is written to page 3 of the array. The remaining pages in the cache are then loaded sequentially to the array. A write cycle is executed after each page is written. If a partially loaded page in the cache remains when the STOP bit is sent, only the bytes that have been loaded will be written to the array. 7.3 Power Management The design incorporates a power standby mode when not in use and automatically powers off after the normal termination of any operation when a stop bit is received and all internal functions are complete. This includes any error conditions, i.e. not receiving an acknowledge or STOP per the two-wire bus specification. The device also incorporates VDD monitor circuitry to prevent inadvertent writes (data corruption) during low-voltage conditions. The VDD monitor circuitry is powered off when the device is in standby mode in order to further reduce power consumption. DS21125E-page 9 24FC65 FIGURE 7-1: 1 CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY Write command initiated at byte 0 of page 3 in the array; First data byte is loaded into the cache byte 0. 2 64 bytes of data are loaded into cache. cache page 0 cache byte 0 3 cache byte 1 • • • cache byte 7 cache page 1 bytes 8-15 cache page 2 bytes 16-23 Write from cache into array initiated by STOP bit. Page 0 of cache written to page 3 of array. Write cycle is executed after every page is written. page 0 page 1 page 2 byte 0 byte 1 • • • page 0 page 1 page 2 page 3 4 • • • cache page 7 bytes 56-63 Remaining pages in cache are written to sequential pages in array. byte 7 page 4 • • • page 7 array row n page 4 • • • page 7 array row n + 1 5 Last page in cache written to page 2 in next row. FIGURE 7-2: CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY 1 3 cache byte 0 Write command initiated; 64 bytes of data loaded into cache starting at byte 2 of page 0. cache byte 1 cache byte 2 Last 2 bytes loaded into page 0 of cache. 4 • • • cache byte 7 cache page 1 bytes 8-15 2 Last 2 bytes ‘roll ever’ to beginning. cache page 2 bytes 16-23 Write from cache into array initiated by STOP bit. Page 0 of cache written to page 3 of array. Write cycle is executed after every page is written. • • • 5 cache page 7 bytes 56-63 Remaining bytes in cache are written sequentially to array. array row n page 0 page 1 page 2 byte 0 byte 1 byte 2 byte 3 byte 4 • • • byte 7 page 4 • • • page 7 page 0 page 1 page 2 page 3 page 4 • • • page 7 array row n+1 6 Last 3 pages in cache written to next row in array. DS21125E-page 10 2004 Microchip Technology Inc. 24FC65 8.0 PIN DESCRIPTIONS 8.2 8.1 A0, A1, A2 Chip Address Inputs This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to VCC (typical 2 KΩ, must consider total bus capacitance and maximum rise/fall times). The A0..A2 inputs are used by the 24FC65 for multiple device operation and conform to the two-wire bus standard. The levels applied to these pins define the address block occupied by the device in the address map. A particular device is selected by transmitting the corresponding bits (A2, A1, A0) in the control byte (Figure 3-2 and Figure 8-1). SDA Serial Address/Data Input/Output For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOPs. 8.3 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. FIGURE 8-1: CONTROL SEQUENCE BIT ASSIGNMENTS A A A R 1 0 1 0 2 1 0 W CONFIGURATION BYTE ADDRESS BYTE 1 ADDRESS BYTE 0 A A A A A S 0 0 12 11 10 9 8 A A 7 • • • • • • 0 CONTROL BYTE B B B B R X X 3 2 1 0 S/HE Slave Address Device Select Bits Block Count Security Read S t a r t No ACK S Data from Device t o p Acknowledge from Master Acknowledges from Device Data from Device R A A A A A A A A B B B C N NN N 1 1 X X X X X XC 1 1 1 1 B 1 0 1 0 2 1 0 0 C 1 X X X X X X XC X X X X X X X XC 3 2 1 0 K 1 1 1 1 3 2 1 0 K K K K S/HE Starting Block Number of Number Blocks to Security Write Protect S Acknowledges from Device t S a t r o t R p A A A A A A N NN N A B B B 1 0 1 0 2 1 0 0 C 1 X X B X X X X X X X XC 1 0 X X 3 2 1 0 C 3 2 1 0 XC K K K K S/HE Starting Block Number of Number Blocks to Protect High Endurance Block Read S t a r t No ACK Acknowledges from Device S Data from Device t o p R A A A A A A A A B B B C 1 0 1 0 2 1 0 0 C 1 X X X X X X XC X X X X X X X XC 0 1 X X X X X XC 1 1 1 1 B 3 2 1 0 K K K K K S/HE High Endurance Block Number High Endurance Block Write S t a r t Acknowledges from Device R A A A A A A A B XC C 0 0 X X 0 0 0 0C 1 0 1 0 2 1 0 0 C 1 X X B B B X X X X X X X X 3 2 1 0 K K K K S/HE High Endurance Block Number 2004 Microchip Technology Inc. S t o p DS21125E-page 11 24FC65 24FC65 Product Identification System To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices. 24FC65 – /P Package: Temperature Range: Device: P = Plastic DIP (300 mil Body) SM = Plastic SOIC (207 mil Body, EIAJ standard) Blank = 0°C to +70°C I = -40°C to +85°C 24FC65 24FC65T 64K, 1MHz I2C Serial EEPROM 64K, 1MHz I2C Serial EEPROM (Tape & Reel) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Web Site (www.microchip.com) DS21125E-page 12 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. DS21125E-page 13 WORLDWIDE SALES AND SERVICE AMERICAS China - Beijing Singapore Corporate Office Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. 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