NSC DP84244N

DP84240/DP84244 Octal TRI-STATEÉ MOS Drivers
General Description
Features
The DP84240 and DP84244 are octal TRI-STATE drivers
which are designed for heavy capacitive load applications
such as fast data buffers or as memory address drivers. The
DP84240 is an inverting driver which is pin-compatible with
both the 74S240 and AM2965. The DP84244 is a non-inverting driver which is pin-compatible with the 74S244 and
AM2966. These parts are fabricated using an oxide isolation
process, for much faster speeds, and are specified for
250 pF and 500 pF load capacitances.
Y
Y
Y
Y
Y
Y
Y
Y
tpd specified with 250 pF and 500 pF loads
Output specified from 0.8V to 2.7V
Designed for symmetric rise and fall times at 500 pF
Outputs glitch free at power up and power down
PNP inputs reduce DC loading on bus lines
Low static and dynamic input capacitance
Low skew times between edges and pins
AC parameters specified with all outputs switching
simultaneously
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
Connection Diagram
Truth Table
DP84240
Inputs
Outputs
Y
G
A
H
X
Z
L
L
H
L
H
L
H e High Level
L e Low Level
X e Don’t Care
Z e High Impedance
TL/F/5219 – 1
Top View
Order Number DP84240J or DP84240N
See NS Package Numbers J20A or N20A
DP84244
G
Inputs
A
Outputs
Y
H
X
Z
L
L
L
L
H
H
TL/F/5219 – 2
Top View
Order Number DP84244J or DP84244N
See NS Package Numbers J20A or N20A
C1995 National Semiconductor Corporation
TL/F/5219
RRD-B30M105/Printed in U. S. A.
DP84240/DP84244 Octal TRI-STATE MOS Drivers
March 1986
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
VCC Supply Voltage
TA Ambient Temperature
Supply Voltage, VCC
Min
4.5
0
Max
5.5
a 70
Units
V
§C
7.0V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Storage Temperature Range
Power Dissipation
Cavity Package
Molded Package
Lead Temperature (soldering, 10 sec.)
7.0V
b 1.5V
b 65§ C to a 150§ C
1150 mW
1300 mW
300§ C
Electrical Characteristics VCC e 5V g 10%, 0 s TA s 70§ C. (Notes 2 and 3.)
Symbol
Parameter
VIN(1)
Logical ‘‘1’’ Input Voltage
VIN(0)
Logical ‘‘0’’ Input Voltage
IIN(1)
Logical ‘‘1’’ Input Current
Conditions
Min
Typ
Max
2.0
VIN e 2.7V
Units
V
0.1
VIN e 7.0V
0.8
V
20
mA
100
mA
IIN(0)
Logical ‘‘0’’ Input Current
0 s VIN s 0.4V
b 50
b 200
mA
VCLAMP
Input Clamp Voltage
IIN e b18 mA
b1
b 1.2
V
VOH
Logical ‘‘1’’ Output Voltage
IOH e b100 mA
IOH e b1 mA
VOL
Logical ‘‘0’’ Output Voltage
IOL e 10 mA
IOL e 12 mA
I1D
Logical ‘‘1’’ Drive Current
VOUT e 1.5V
b 75
b 250
mA
I0D
Logical ‘‘0’’ Drive Current
VOUT e 1.5V
a 100
a 150
mA
Hi-Z
TRI-STATE Output Current
0.4V s VOUT s 2.7V
b 100
ICC
Supply Current
DP84240
All Outputs Open
All Outputs High
All Outputs Low
All Outputs Hi-Z
16
74
80
50
125
125
All Outputs High
All Outputs Low
All Outputs Hi-Z
40
100
115
75
130
150
DP84244
VCC – 1.15
VCC b1.5
4.3
3.9
0.2
0.3
V
0.4
0.5
a 100
V
mA
mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: All currents into device pins shown as positive; all currents out of device pins shown as negative; all voltages referenced to ground unless otherwise noted.
All values shown as max. or min. are on an absolute value basis.
Note 3: Typical characteristics are taken at VCC e 5.0V and TA e 25§ C.
Note 4: The output-to-output skew is primarily a function of the number of outputs switching and the capacitive loading on those outputs. See Figures 5 and 6 for
the switching time variations.
2
Switching Characteristics VCC e 5V g 10%, 0 s TA s 70§ C, all outputs loaded with specified load capacitance and all eight outputs switching simultaneously. (Note 3.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CL e 250 pF
CL e 500 pF
9
10
16
20
27
33
ns
CL e 250 pF
CL e 500 pF
9
12
16
20
25
31
ns
Figures 2 & 4, S e 1, CL e 50 pF
11
24
ns
Figures 2 & 4, S e 2, CL e 50 pF
12
24
ns
Output Enable Time to LOW
Figures 2 & 4, S e 1, CL e 500 pF
30
45
ns
Output Enable Time to HIGH
Figures 2 & 4, S e 2, CL e 500 pF
23
35
ns
Output-to-Output Skew (Note 4)
Figures 1 & 3, CL e 500 pF
3
tPLH
Propagation Delay from
LOW-to-HIGH Output
tPHL
Propagation Delay from
HIGH-to-LOW Output
tPLZ
Output Disable Time from LOW
tPHZ
Output Disable Time from HIGH
tPZL
tPZH
tSKEW
Figures 1 & 3
ns
Capacitance TA e 25§ C, f e 1 MHz, VCC e 5V g 10%. (Note 3.)
Typ
Units
CIN
Parameter
All Other Inputs Tied Low
Conditions
6
pF
COUT
Output in TRI-STATE Mode
20
pF
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: All currents into device pins shown as positive; all currents out of device pins shown as negative; all voltages referenced to ground unless otherwise noted.
All values shown as max. or min. are on an absolute value basis.
Note 3: Typical characteristics are taken at VCC e 5.0V and TA e 25§ C.
Note 4: The output-to-output skew is primarily a function of the number of outputs switching and the capacitive loading on those outputs. See Figures 5 and 6 for
the switching time variations.
3
Switching Test Circuits
TL/F/5219 – 3
TL/F/5219 – 4
*CL INCLUDES PROBE AND JIG CAPACITANCES
FIGURE 1. Capacitive Load Switching
FIGURE 2. TRI-STATE Enable/Disable
Typical Switching Characteristics
Voltage Waveforms
TL/F/5219 – 5
TL/F/5219 – 6
FIGURE 3. Output Drive Levels
FIGURE 4. TRI-STATE Control Levels
TL/F/5219 – 7
TL/F/5219 – 8
FIGURE 5. tPLH Measured to 2.7V on Output vs. CL
FIGURE 6. tPHL Measured to 0.8V on Output vs. CL
4
Typical Switching Characteristics (Continued)
TL/F/5219 – 9
TL/F/5219 – 10
FIGURE 7. Typical Power Dissipation for DP84240 at
VCC e 5.5V (All 8 drivers switching simultaneously)
FIGURE 8. Typical Power Dissipation for DP84244 at
VCC e 5.5V (All 8 drivers switching simultaneously)
Typical Application
DP84244 used as a buffer in a large memory array (greater than 88 dynamic RAMs)
TL/F/5219 – 11
5
DP84240/DP84244 Octal TRI-STATE MOS Drivers
Physical Dimensions inches (millimeters)
20-Lead Dual-In-Line Package (J)
Order Number DP84240J/DP84244J
NS Package Number J20A
LIFE SUPPORT POLICY
20-Lead Dual-In-Line Package (N)
Order Number DP84240N/DP84244N
NS Package Number N20A
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