ADC088S102 8-Channel, 500 kSPS to 1 MSPS, 8-Bit A/D Converter General Description Features The ADC088S102 is a low-power, eight-channel CMOS 8-bit analog-to-digital converter specified for conversion throughput rates of 500 kSPS to 1 MSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to eight input signals at inputs IN0 through IN7. n n n n n The output serial data is straight binary and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE™, and many common DSP serial interfaces. The ADC088S102 may be operated with independent analog and digital supplies. The analog supply (VA) can range from +2.7V to +5.25V, and the digital supply (VD) can range from +2.7V to VA. Normal power consumption using a +3V or +5V supply is 1.8 mW and 8.0 mW, respectively. The powerdown feature reduces the power consumption to 0.03 µW using a +3V supply and 0.15 µW using a +5V supply. Key Specifications The ADC088S102 is packaged in a 16-lead TSSOP package. Operation over the extended industrial temperature range of −40˚C to +105˚C is guaranteed. n n n n Eight input channels Variable power management Independent analog and digital supplies SPI/QSPI/MICROWIRE/DSP compatible Packaged in 16-lead TSSOP Conversion Rate DNL (VA = VD = 5.0 V) INL (VA = VD = 5.0 V) Power Consumption — 3V Supply — 5V Supply 500 kSPS to 1 MSPS ± 0.3 LSB (max) ± 0.2 LSB (max) 1.8 mW (typ) 8.0 mW (typ) Applications n n n n n Automotive Navigation Portable Systems Medical Instruments Mobile Communications Instrumentation and Control Systems Connection Diagram 20166505 Ordering Information Order Code Temperature Range Description ADC088S102CIMT −40˚C to +105˚C 16-Lead TSSOP Package ADC088S102CIMTX −40˚C to +105˚C 16-Lead TSSOP Package, Tape & Reel ADC088S102EVAL Evaluation Board TRI-STATE ® is a trademark of National Semiconductor Corporation. MICROWIRE™ is a trademark of National Semiconductor Corporation. QSPI™ and SPI™ are trademarks of Motorola, Inc. © 2005 National Semiconductor Corporation DS201665 www.national.com ADC088S102 8-Channel, 500 kSPS to 1 MSPS, 8-Bit A/D Converter September 2005 ADC088S102 Block Diagram 20166507 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to VREF. 16 SCLK Digital clock input. The guaranteed performance range of frequencies for this input is 8 MHz to 16 MHz. This clock directly controls the conversion and readout processes. 15 DOUT Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK pin. 14 DIN Digital data input. The ADC088S102’s Control Register is loaded through this pin on rising edges of the SCLK pin. 1 CS Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low. VA Positive analog supply pin. This voltage is also used as the reference voltage. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with 1 µF and 0.1 µF monolithic ceramic capacitors located within 1 cm of the power pin. VD Positive digital supply pin. This pin should be connected to a +2.7V to VA supply, and bypassed to GND with a 0.1 µF monolithic ceramic capacitor located within 1 cm of the power pin. DIGITAL I/O POWER SUPPLY 2 13 3 AGND The ground return for the analog supply and signals. 12 DGND The ground return for the digital supply and signals. www.national.com 2 Operating Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Temperature Analog Supply Voltage VA −0.3V to 6.5V Digital Supply Voltage VD −0.3V to VA + 0.3V, max 6.5V Voltage on Any Pin to GND Power Dissipation at TA = 25˚C 2500V 250V Soldering Temperature, Infrared, 10 seconds (Note 6) 260˚C Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C +2.7V to VA 0V to VA 0V to VA Clock Frequency 8 MHz to 16 MHz Package Thermal Resistance See (Note 4) ESD Susceptibility (Note 5) Human Body Model Machine Model +2.7V to +5.25V Analog Input Voltage ± 10 mA ± 20 mA Package Input Current(Note 3) VA Supply Voltage VD Supply Voltage Digital Input Voltage −0.3V to VA +0.3V Input Current at Any Pin (Note 3) −40˚C ≤ TA ≤ +105˚C Package θJA 16-lead TSSOP on 4-layer, 2 oz. PCB 96˚C / W Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) ADC088S102 Converter Electrical Characteristics (Note 8) The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 kSPS to 1 MSPS, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Typical Limits (Note 7) Units 8 Bits STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL Integral Non-Linearity (End Point Method) ± 0.05 ± 0.2 LSB (max) DNL Differential Non-Linearity ± 0.06 Offset Error OEM Offset Error Match FSE Full Scale Error FSEM Full Scale Error Match ± 0.3 ± 0.7 ± 0.2 ± 0.6 ± 0.2 LSB (max) VOFF +0.6 ± 0.02 +0.5 ± 0.02 LSB (max) LSB (max) LSB (max) LSB (max) DYNAMIC CONVERTER CHARACTERISTICS FPBW Full Power Bandwidth (−3dB) SINAD Signal-to-Noise Plus Distortion Ratio fIN = 40.2 kHz, −0.02 dBFS 49.6 49.2 dB (min) SNR Signal-to-Noise Ratio fIN = 40.2 kHz, −0.02 dBFS 49.6 49.3 dB (min) THD Total Harmonic Distortion fIN = 40.2 kHz, −0.02 dBFS −71.2 −63.7 dB (max) SFDR Spurious-Free Dynamic Range fIN = 40.2 kHz, −0.02 dBFS 67.9 63.9 dB (min) ENOB Effective Number of Bits fIN = 40.2 kHz 7.95 7.88 Bits (min) ISO Channel-to-Channel Isolation fIN = 20 kHz 69.6 dB Intermodulation Distortion, Second Order Terms fa = 19.5 kHz, fb = 20.5 kHz −75.5 dB Intermodulation Distortion, Third Order Terms fa = 19.5 kHz, fb = 20.5 kHz −71.8 dB IMD 8 MHz ANALOG INPUT CHARACTERISTICS VIN Input Range IDCL DC Leakage Current CINA Input Capacitance 0 to VA V ±1 µA (max) Track Mode 33 pF Hold Mode 3 pF 3 www.national.com ADC088S102 Absolute Maximum Ratings (Note 1) ADC088S102 ADC088S102 Converter Electrical Characteristics (Note 8) (Continued) The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 kSPS to 1 MSPS, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Limits (Note 7) Units VA = VD = +2.7V to +3.6V 2.1 V (min) Parameter Conditions Typical DIGITAL INPUT CHARACTERISTICS VIH Input High Voltage VA = VD = +4.75V to +5.25V 2.4 V (min) VIL Input Low Voltage VA = VD = +2.7V to +5.25V 0.8 V (max) IIN Input Current VIN = 0V or VD ± 0.01 ±1 µA (max) CIND Digital Input Capacitance 2 4 pF (max) DIGITAL OUTPUT CHARACTERISTICS VOH Output High Voltage ISOURCE = 200 µA VOL Output Low Voltage ISINK = 200 µA to 1.0 mA, IOZH, IOZL Hi-Impedance Output Leakage Current COUT Hi-Impedance Output Capacitance (Note 8) 2 Output Coding VD − 0.5 V (min) 0.4 V (max) ±1 µA (max) 4 pF (max) Straight (Natural) Binary POWER SUPPLY CHARACTERISTICS (CL = 10 pF) VA, VD Analog and Digital Supply Voltages Total Supply Current Normal Mode ( CS low) I A + ID Total Supply Current Shutdown Mode (CS high) Power Consumption Normal Mode ( CS low) PC Power Consumption Shutdown Mode (CS high) V A ≥ VD 2.7 V (min) 5.25 V (max) VA = VD = +2.7V to +3.6V, fSAMPLE = 1 MSPS, fIN = 40 kHz 0.6 1.2 mA (max) VA = VD = +4.75V to +5.25V, fSAMPLE = 1 MSPS, fIN = 40 kHz 1.6 2.2 mA (max) VA = VD = +2.7V to +3.6V, fSCLK = 0 kSPS 10 nA VA = VD = +4.75V to +5.25V, fSCLK = 0 kSPS 30 nA VA = VD = +3.0V fSAMPLE = 1 MSPS, fIN = 40 kHz 1.8 3.6 mW (max) VA = VD = +5.0V fSAMPLE = 1 MSPS, fIN = 40 kHz 8.0 11.0 mW (max) VA = VD = +3.0V fSCLK = 0 kSPS 0.03 µW VA = VD = +5.0V fSCLK = 0 kSPS 0.15 µW AC ELECTRICAL CHARACTERISTICS fSCLKMIN Minimum Clock Frequency fSCLK Maximum Clock Frequency fS Sample Rate Continuous Mode tCONVERT Conversion (Hold) Time DC SCLK Duty Cycle tACQ Acquisition (Track) Time Throughput Time tAD 0.8 50 www.national.com 500 kSPS (min) 1 MSPS (max) 13 SCLK cycles 40 % (min) 70 60 % (max) 3 SCLK cycles 16 SCLK cycles 4 4 MHz (min) MHz (max) 30 Acquisition Time + Conversion Time Aperture Delay 8 16 ns The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 kSPS to 1 MSPS, and CL = 50pF. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Typical Limits (Note 7) Units tCSH CS Hold Time after SCLK Rising Edge (Note 9) 0 10 ns (min) tCSS CS Setup Time prior to SCLK Rising Edge (Note 9) 5 10 ns (min) tEN CS Falling Edge to DOUT enabled 5 30 ns (max) tDACC DOUT Access Time after SCLK Falling Edge 17 27 ns (max) tDHLD DOUT Hold Time after SCLK Falling Edge 4 tDS DIN Setup Time prior to SCLK Rising Edge 3 10 ns (min) tDH DIN Hold Time after SCLK Rising Edge 3 10 ns (min) tCH SCLK High Time 0.4 x tSCLK ns (min) tCL SCLK Low Time 0.4 x tSCLK ns (min) tDIS CS Rising Edge to DOUT High-Impedance ns (typ) DOUT falling 2.4 20 ns (max) DOUT rising 0.9 20 ns (max) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. In the 16-pin TSSOP, θJA is 96˚C/W, so PDMAX = 1,200 mW at 25˚C and 625 mW at the maximum operating ambient temperature of 105˚C. Note that the power consumption of this device under normal operation is a maximum of 12 mW. The values for maximum power dissipation listed above will be reached only when the ADC088S102 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO ohms Note 6: Reflow temperature profiles are different for lead-free packages. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 9: Clock may be in any state (high or low) when CS goes high. Setup and hold restrictions apply only to CS going low. 5 www.national.com ADC088S102 ADC088S102 Timing Specifications ADC088S102 Timing Diagrams 20166551 FIGURE 1. ADC088S102 Operational Timing Diagram 20166506 FIGURE 2. ADC088S102 Serial Timing Diagram 20166550 FIGURE 3. SCLK and CS Timing Parameters www.national.com 6 APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is internally acquired or held for conversion. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC088S102 is guaranteed not to have any missing codes. CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB). SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. CHANNEL-TO-CHANNEL ISOLATION is resistance to coupling of energy from one channel into another channel. CROSSTALK is the coupling of energy from one channel into another channel. This is similar to Channel-to-Channel Isolation, except for the sign of the data. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum that is not present at the input, including harmonics but excluding d.c. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5 LSB), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2 LSB below the first code transition) through positive full scale (1⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to an individual ADC input at the same time. It is defined as the ratio of the power in either the where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the acquisition time plus the conversion time. 7 www.national.com ADC088S102 ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold capacitor is charged by the input voltage. second or the third order intermodulation products to the sum of the power in both of the original frequencies. Second order products are fa ± fb, where fa and fb are the two sine wave input frequencies. Third order products are (2fa ± fb ) and (fa ± 2fb). IMD is usually expressed in dB. Specification Definitions ADC088S102 Typical Performance Characteristics VA = VD = +5.0V, TA = +25˚C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated. DNL DNL 20166540 20166541 INL INL 20166542 20166543 DNL vs. Supply INL vs. Supply 20166521 www.national.com 20166520 8 SNR vs. Supply THD vs. Supply 20166522 20166532 ENOB vs. Supply DNL vs. VD with VA = 5.0 V 20166533 20166530 INL vs. VD with VA = 5.0 V DNL vs. SCLK Duty Cycle 20166531 20166555 9 www.national.com ADC088S102 Typical Performance Characteristics VA = VD = +5.0V, TA = +25˚C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated. (Continued) ADC088S102 Typical Performance Characteristics VA = VD = +5.0V, TA = +25˚C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated. (Continued) INL vs. SCLK Duty Cycle SNR vs. SCLK Duty Cycle 20166558 20166561 THD vs. SCLK Duty Cycle ENOB vs. SCLK Duty Cycle 20166564 20166552 DNL vs. SCLK INL vs. SCLK 20166556 www.national.com 20166559 10 SNR vs. SCLK THD vs. SCLK 20166562 20166565 ENOB vs. SCLK DNL vs. Temperature 20166553 20166557 INL vs. Temperature SNR vs. Temperature 20166560 20166563 11 www.national.com ADC088S102 Typical Performance Characteristics VA = VD = +5.0V, TA = +25˚C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated. (Continued) ADC088S102 Typical Performance Characteristics VA = VD = +5.0V, TA = +25˚C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated. (Continued) THD vs. Temperature ENOB vs. Temperature 20166566 20166554 SNR vs. Input Frequency THD vs. Input Frequency 20166523 20166524 ENOB vs. Input Frequency Power Consumption vs. SCLK 20166525 www.national.com 20166544 12 The ADC088S102 is a successive-approximation analog-todigital converter designed around a charge-redistribution digital-to-analog converter. 1.1 ADC088S102 OPERATION Simplified schematics of the ADC088S102 in both track and hold operation are shown in Figure 4 and Figure 5 respectively. In Figure 4, the ADC088S102 is in track mode: switch SW1 connects the sampling capacitor to one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The ADC088S102 is in this state for the first three SCLK cycles after CS is brought low. 20166509 FIGURE 4. ADC088S102 in Track Mode 20166510 FIGURE 5. ADC088S102 in Hold Mode 1.2 SERIAL INTERFACE An operational timing diagram and a serial interface timing diagram for the ADC088S102 are shown in The Timing Diagrams section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC088S102’s Control Register is placed on DIN, the serial data input pin. New data is written to DIN with each conversion. A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC’s DOUT pin is in a high impedance state when CS is high and is active when CS is low. Thus, CS acts as an output enable. Similarly, SCLK is internally gated off when CS is brought high. During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock out leading zeros, falling edges 5 through 12 clock out the conversion result, MSB first, and falling edges 13 through 16 clock out trailing zeros. If there is more than one conversion in a frame (continuous conversion mode), the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK. "N" is an integer value. The ADC088S102 enters track mode under three different conditions. In Figure 1, CS goes low with SCLK high and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as the first falling edge of SCLK. In the third condition, CS and SCLK go low simulta13 www.national.com ADC088S102 Figure 5 shows the ADC088S102 in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The ADC088S102 is in this state for the last thirteen SCLK cycles after CS is brought low. 1.0 Functional Description ADC088S102 1.0 Functional Description after the fall of CS. The control register is loaded with data indicating the input channel to be converted on the subsequent conversion (see Tables 1, 2, 3). (Continued) neously and the ADC enters track mode. While there is no timing restriction with respect to the falling edges of CS and SCLK, see Figure 3 for setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK. The user does not need to incorporate a power-up delay or dummy conversions as the ADC088S102 is able to acquire the input signal to full resolution in the first conversion immediately following power-up. The first conversion result after power-up will be that of IN0. During each conversion, data is clocked into a control register through the DIN pin on the first 8 rising edges of SCLK TABLE 1. Control Register Bits Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC TABLE 2. Control Register Bit Descriptions Bit #: Symbol: Description 7, 6, 2, 1, 0 DONTC Don’t care. The values of these bits do not affect the device. These three bits determine which input channel will be sampled and converted at the next conversion cycle. The mapping between codes and channels is shown in Table 3. 5 ADD2 4 ADD1 3 ADD0 TABLE 3. Input Channel Selection ADD2 ADD1 ADD0 Input Channel 0 0 0 IN0 (Default) 0 0 1 IN1 0 1 0 IN2 0 1 1 IN3 1 0 0 IN4 1 0 1 IN5 1 1 0 IN6 1 1 1 IN7 1.4 ANALOG INPUTS An equivalent circuit for one of the ADC088S102’s input channels is shown in Figure 7. Diodes D1 and D2 provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to VA. Going beyond this range will cause the ESD diodes to conduct and result in erratic operation. The capacitor C1 in Figure 7 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1 is the on resistance of the multiplexer and track / hold switch and is typically 500 ohms. Capacitor C2 is the ADC088S102 sampling capacitor, and is typically 30 pF. The ADC088S102 will deliver best performance when driven by a low-impedance source (less than 100 ohms). This is especially important when using the ADC088S102 to sample dynamic signals. Also important when sampling dynamic signals is a bandpass or low-pass filter which reduces harmonics and noise in the input. These filters are often referred to as anti-aliasing filters. 1.3 ADC088S102 TRANSFER FUNCTION The output format of the ADC088S102 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC088S102 is VA / 256. The ideal transfer characteristic is shown in Figure 6. The transition from an output code of 0000 0000 to a code of 0000 0001 is at 1/2 LSB, or a voltage of VA / 512. Other code transitions occur at steps of one LSB. 20166514 FIGURE 7. Equivalent Input Circuit 1.5 DIGITAL INPUTS AND OUTPUTS The ADC088S102’s digital inputs (SCLK, CS, and DIN) have an operating range of 0 V to VA. They are not prone to latch-up and may be asserted before the digital supply (VD) without any risk. The digital output (DOUT) operating range is controlled by VD. The output high voltage is VD - 0.5V (min) while the output low voltage is 0.4V (max). 20166511 FIGURE 6. Ideal Transfer Characteristic www.national.com 14 2.1 TYPICAL APPLICATION CIRCUIT To minimize the error caused by the changing input capacitance of the ADC088S102, a capacitor is connected from each input pin to ground. The capacitor, which is much larger than the input capacitance of the ADC088S102 when in track mode, provides the current to quickly charge the sampling capacitor of the ADC088S102. An isolation resistor is added to isolate the load capacitance from the input source. A typical application is shown in Figure 8. The split analog and digital supply pins are both powered in this example by the National LP2950 low-dropout voltage regulator. The analog supply is bypassed with a capacitor network located close to the ADC088S102. The digital supply is separated from the analog supply by an isolation resistor and bypassed with additional capacitors. The ADC088S102 uses the analog supply (VA) as its reference voltage, so it is very impor- 20166513 FIGURE 8. Typical Application Circuit Power Consumption vs. SCLK curve in the Typical Performance Curves section shows the typical power consumption of the ADC088S102. To calculate the power consumption (PC), simply multiply the fraction of time spent in the normal mode (tN) by the normal mode power consumption (PN), and add the fraction of time spent in shutdown mode (tS) multiplied by the shutdown mode power consumption (PS) as shown in Figure 9. 2.2 POWER SUPPLY CONSIDERATIONS There are three major power supply concerns with this product: power supply sequencing, power management, and the effect of digital supply noise on the analog supply. 2.2.1 Power Supply Sequence The ADC088S102 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised to ensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital supply (VD) cannot exceed the analog supply (VA) by more than 300 mV, not even on a transient basis. Therefore, VA must ramp up before or concurrently with VD. 20166515 2.2.2 Power Management The ADC088S102 is fully powered-up whenever CS is low and fully powered-down whenever CS is high, with one exception. If operating in continuous conversion mode, the ADC088S102 automatically enters power-down mode between SCLK’s 16th falling edge of a conversion and the SCLK’s 1st falling edge of the subsequent conversion (see Figure 1). In continuous conversion mode, the ADC088S102 can perform multiple conversions back to back. Each conversion requires 16 SCLK cycles and the ADC088S102 will perform conversions continuously as long as CS is held low. Continuous mode offers maximum throughput. In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical specifications. The FIGURE 9. Power Consumption Equation 2.2.3 Power Supply Noise Considerations The charging of any output load capacitance requires current from the digital supply, VD. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if the analog and digital supplies are tied directly together, the noise on the digital supply will be coupled directly into the analog supply, causing greater performance degradation than would noise on the digital supply alone. Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger the 15 www.national.com ADC088S102 tant that VA be kept as clean as possible. Due to the low power requirements of the ADC088S102, it is also possible to use a precision reference as a power supply. 2.0 Applications Information ADC088S102 2.0 Applications Information mance degradation of the ADC088S102 due to supply noise, do not use the same supply for the ADC088S102 that is used for digital logic. Generally, analog and digital lines should cross each other at 90˚ to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clock line should also be treated as a transmission line and be properly terminated. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. (Continued) output capacitance, the more current flows through the die substrate and the greater the noise coupled into the analog channel. The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100 Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge current of the output capacitance and improve noise performance. Since the series resistor and the load capacitance form a low frequency pole, verify signal integrity once the series resistor has been added. We recommend the use of a single, uniform ground plane and the use of split power planes. The power planes should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed over the analog power plane. All digital circuitry and I/O lines should be placed over the digital power plane. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short traces and enter the analog ground plane at a single, quiet point. 2.3 LAYOUT AND GROUNDING Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise generated could have significant impact upon system noise performance. To avoid perfor- www.national.com 16 inches (millimeters) unless otherwise noted 16-Lead TSSOP Order Number ADC088S102CIMT, ADC088S102CIMTX NS Package Number MTC16 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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